configs: Fix spelling mistakes.

Replace "fequency" to "frequency".

Change-Id: I307c8b6d8e60cfcb213f22aca3f6abd43c6b5b1e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58229
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
GWDx
2022-03-27 20:53:13 +08:00
committed by WenDi Gan
parent e32de65973
commit 1680d7dab4
8 changed files with 8 additions and 8 deletions

View File

@@ -49,7 +49,7 @@ options = parser.parse_args()
system = System()
# use timing mode for the interaction between requestor-responder ports
system.mem_mode = 'timing'
# set the clock fequency of the system
# set the clock frequency of the system
clk = '1GHz'
vd = VoltageDomain(voltage='1V')
system.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd)

View File

@@ -50,7 +50,7 @@ def build_system(options):
system = System()
# use timing mode for the interaction between requestor-responder ports
system.mem_mode = 'timing'
# set the clock fequency of the system
# set the clock frequency of the system
clk = '100GHz'
vd = VoltageDomain(voltage='1V')
system.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd)

View File

@@ -43,7 +43,7 @@ from m5.objects import *
# create the system we are going to simulate
system = System()
# Set the clock fequency of the system (and all of its children)
# Set the clock frequency of the system (and all of its children)
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = '1GHz'
system.clk_domain.voltage_domain = VoltageDomain()

View File

@@ -70,7 +70,7 @@ args = SimpleOpts.parse_args()
# create the system we are going to simulate
system = System()
# Set the clock fequency of the system (and all of its children)
# Set the clock frequency of the system (and all of its children)
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = '1GHz'
system.clk_domain.voltage_domain = VoltageDomain()

View File

@@ -39,7 +39,7 @@ from m5.objects import *
# create the system we are going to simulate
system = System()
# Set the clock fequency of the system (and all of its children)
# Set the clock frequency of the system (and all of its children)
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = '1GHz'
system.clk_domain.voltage_domain = VoltageDomain()

View File

@@ -39,7 +39,7 @@ from m5.objects import *
# create the system we are going to simulate
system = System()
# Set the clock fequency of the system (and all of its children)
# Set the clock frequency of the system (and all of its children)
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = '1GHz'
system.clk_domain.voltage_domain = VoltageDomain()

View File

@@ -44,7 +44,7 @@ from test_caches import TestCacheSystem
# create the system we are going to simulate
system = System()
# Set the clock fequency of the system (and all of its children)
# Set the clock frequency of the system (and all of its children)
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = '1GHz'
system.clk_domain.voltage_domain = VoltageDomain()

View File

@@ -53,7 +53,7 @@ from msi_caches import MyCacheSystem
# create the system we are going to simulate
system = System()
# Set the clock fequency of the system (and all of its children)
# Set the clock frequency of the system (and all of its children)
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = '1GHz'
system.clk_domain.voltage_domain = VoltageDomain()