The LDS is capable of handling out-of-bounds accesses,
that is, accesses that are outside the bounds of the
chunk allocated to a WG. Currently, the simulator asserts
on these accesses. This patch changes the behavior of the
LDS to return 0 for reads and dropping writes that are
out-of-bounds.
Change-Id: I5f467d0f52113e8565e1a3029e82fb89cc6f07ea
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29940
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Ubuntu 20.04 contains GCC verisons 9 and 10, which are not easily
obtainable (at least through APT) on Ubuntu 18.04. Therefore, a
Dockerfile for obtaining GCC versions in Ubuntu 20.04 has been added.
The orignal GCC version Dockerfile (Ubuntu 18.04) has been kept as
GCC versions 4.8, 5, and 6 are not obtainable, via APT, on Ubuntu
20.04. A complete migration to the 20.04 Dockerfile is not possible
until these earlier GCC versions are dropped.
The Docker images for GCC Versions 9 and 10 can be found here:
https://gcr.io/gem5-test/gcc-version-10https://gcr.io/gem5-test/gcc-version-9
The other Dockerfile directories have been renamed for consistency.
Change-Id: I569249331095ee62d1be5be479c7ba7da0077422
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30514
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
This script runs a series of compilations on gem5. The following
compilers are tested:
clang-9
clang-8
clang-7
clang-6
clang-5
clang-4
clang-3.9
gcc-9
gcc-8
gcc-7
gcc-6
gcc-5
gcc-4.8 (to be dropped soon:
https://gem5.atlassian.net/browse/GEM5-218)
They are tested by building the following build targets:
ARM
ARM_MESI_Three_Level
Garnet_standalone
GCN3_X86
MIPS
NULL_MESI_Two_Level
NULL_MOESI_CMP_directory
NULL_MOESI_CMP_token
NULL_MOESI_hammer
POWER
RISCV
SPARC
X86
X86_MOESI_AMD_BASE
For each, ".opt" and ".fast" compiler build settings are tested.
clang-9 and gcc-9 are tested against all targets with each build
setting. For the remaining compilers, a random build target is
chosen. After the script has run, the output of the tests can be
found in "compile-test-out".
Docker is required to run this script.
Change-Id: Id3bf4c89b9d424c87e9409930ee2aceaef72cb29
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30395
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The RubyPrefetcher uses makeNextStrideAddress() with
a negative stride to find prefetched address.
The type of this expression is:
uint64_t + uint32_t * int;
This gives wrong result due to implicit conversion.
Fix this with static cast and it works correctly:
uint64_t + int * int;
Change-Id: I36e17e00d5c66c3699fe1d5b287971225a162d04
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31314
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Motivation:
An AddressSizeFault on AArch32 can only happen during a table walk
since the register used as a base by LD/ST is always 32 bit wide.
On AArch64 on the other hand, addresses can be 64bit wide;
when MMU is off (no virtual memory) an invalid physical address
can be specified
Change-Id: Id3ef170e99202c6b0b511fa7205c754956861720
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31274
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This will still be technically possible with the right converters, but
this removes the tags, ignore file, and style checking hooks related to
mercurial. We no longer maintain a mercurial mirror of the main git
repository, and this support adds clutter and could diverge from the git
style hooks, etc, over time.
Change-Id: Icf4833c4f0fda51ea98989d1d741432ae3ddc6dd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31174
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This changeset drops fetches if there is no entry reserved in the
fetch buffer for that instruction. This can happen due to a fetch
attempted to be issued in the same cycle where a branch instruction
flushed the fetch buffer, while an ITLB or I-cache request is still
pending.
Change-Id: I3b80dbd71af27ccf790b543bd5c034bb9b02624a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29932
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Onur Kayıran <onur.kayiran@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
These classes are all basically empty now that Alpha has been deleted,
except in cases where the arch versions had copied versions of the Alpha
code.
This change pulls all the generic logic out of the arch versions, making
the arch versions much simpler and making it clearer what the core
functionality of the class is, and what parts are architecture specific
details.
In the future, the way the StackTrace class is instantiated should be
delegated to the Workload class so that ISA agnostic code doesn't need
to know about a particular ISA's StackTrace class, and so that
StackTrace logic can, at least theoretically, be specialized for a
particular workload. The way a stack trace is collected could vary from
OS to OS, for example.
Change-Id: Id8108f94e9fe8baf9b4056f2b6404571e9fa52f1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30961
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
KVM_CAP_ARM_USER_IRQ is a KVM extension introduced in newer versions of
Linux (>= 4.12). It supports delivering interrupt from the kernel-space
timer to the user-space GIC, which means that it will be unnecessary to
use the memory-mapped timer and emulate it in gem5 anymore.
Using the option provided by this change, Linux is able to boot with 1
CPU successfully, and the speed is slightly faster then the memory-
mapped timer option. However, multicore seems to hang during boot and
still needs more investigation to be enabled.
JIRA: https://gem5.atlassian.net/browse/GEM5-663
Change-Id: I146bbcce3cf66f8f5ebee04ea5f1b9f54868721a
Signed-off-by: Hsuan Hsu <hsuan.hsu@mediatek.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30921
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
The memory-mapped timer emulated by gem5 is driven by the underlying
gem5 tick, which means that we must align the tick with the host time
to make the timer interrupt fire at a nearly native rate.
In each KVM execution round, the number of ticks incremented is
directly calculated from the number of instructions executed. However,
when a guest CPU switches to idle state, KVM seems to stay in kernel-
space until the POSIX timer set up in user-space raises an expiration
signal, instead of trapping to user-space immediately; and somehow the
instruction count is just too low to match the elapsed host time. This
makes the gem5 tick increment very slowly when the guest is idle and
drastically slow down workloads being sensitive to the guest time which
is driven by timer interrupt.
Before switching to KVM to execute the guest code, gem5 programs the
POSIX timer to expire according to the remaining ticks before the next
event in the event queue. Based on this, we can come up with the
following solution: If KVM returns to user-space due to POSIX timer
expiration, it must be time to process the next gem5 event, so we just
fast-forward the tick (by scheduling the next CPU tick event) to that
event directly without calculating from the instruction count.
There is one more related issue needed to be solved. The KVM exit
reason, KVM_EXIT_INTR, was treated as the case where the KVM execution
was disturbed by POSIX timer expiration. However, there exists a case
where the exit reason is KVM_EXIT_INTR but the POSIX timer has not
expired. Its cause is still unknown, but it can be observed via the
"old_value" argument returned by timer_settime() when disarming the
POSIX timer. In addition, it seems to happen often when a guest CPU is
not in idle state. When this happens, the above tick event scheduling
incorrectly treats KVM_EXIT_INTR as POSIX timer expiration and fast-
forwards the tick to process the next event too early. This makes the
guest feel external events come too fast, and will sometimes cause
trouble. One example is the VSYNC interrupt from HDLCD. The guest seems
to get stuck in VSYNC handling if the KVM CPU is not given enough time
between each VSYNC interrupt to complete a service. (Honestly I did not
dig in to see how the guest handled the VSYNC interrupt and how the
above situation became trouble. I just observed from the debug trace of
GIC & HDLCD & timer, and made this conclusion.) This change also uses
a workaround to detect POSIX timer expiration correctly to make the
guest work with HDLCD.
JIRA: https://gem5.atlassian.net/browse/GEM5-663
Change-Id: I6159238a36fc18c0c881d177a742d8a7745a23ca
Signed-off-by: Hsuan Hsu <hsuan.hsu@mediatek.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30919
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
We should also deal with change of the imask bit, or we will lose timer
interrupt if the timer expires before the guest kernel unmasks the bit.
More precisely, consider the following common pattern in timer interrupt
handling:
1. Set the interrupt mask bit (CNTV_CTL.IMASK)
2. Reprogram the downcounter (CNTV_TVAL) for the next interrupt
3. Clear the interrupt mask bit (CNTV_CTL.IMASK)
The timer can expires between step 2 & 3 if the value programmed in step
2 is small enough, and this seems very likely to happen in KVM mode. If
we don't check for timer expiration right after unmasking, we will miss
the only chance to inject the interrupt.
JIRA: https://gem5.atlassian.net/browse/GEM5-663
Change-Id: I75e8253bb78d15ae72cb985ed132f896d8e92ca6
Signed-off-by: Hsuan Hsu <hsuan.hsu@mediatek.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30918
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This patch adds the ability for a host-OS process external to gem5
to access the backing store via POSIX shared memory.
The new param shared_backstore of the System object is the filename
of the shared memory (i.e., the first argument to shm_open()).
Change-Id: I98c948a32a15049a4515e6c02a14595fb5fe379f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30994
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Some ARM instructions were using quiesce and quiesceSkip pseudo
instruction bodies instead of implementing the one line of each of those
functions themselves. This creates two problems. First, it adds an
artificial depedence on the pseudo instruction implementations. Second,
it would confusing cause pseudo instruction DPRINTFs to fire when normal
instructions were executing.
This change simply replaces the calls with their targets one line
implementation, with some very minor duplication from multiple call
sights factored out into a local variable.
Change-Id: I596eafd8714227fa7f69edd542108598c9809b11
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27790
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
When restoring a checkpoint containing a generic timer, the checkpoint
expects to connect the timer to the same number of CPUs that were
present when the checkpoint was taken. If the number of CPUs in the
new simulation is different, deserialization will fail. In the case
that the number of CPUs expected by the checkpoint is greater than the
number of CPUs present, this will cause a segmentation fault caused by
reading off the end of the list of Thread Contexts.
This commit fixes the problem by checking the number of CPUs present
in the simulation matches the number of CPUs expected by the generic
timer checkpoint. If there is a mismatch, a fatal error is triggered
with an informative message to the user.
Change-Id: Iff9ad68d64e67b3df51682b7e4e272e5f355bcd6
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30576
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
The O3 model uses ReExec faults to flush the pipeline and restart
after a memory ordering violation, e.g. due to an incoming snoop.
These, just like branch mispredict flushes, are not architectural
faults but micro-architectural events, and should therefore not
show up on the instruction tracing interface.
This adds a check on faulting instructions in commit, to verify
if the instruction faulted due to ReExec, to avoid tracing it.
Change-Id: I1d3eaffb0ff22411e0e16a69ef07961924c88c10
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30554
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
The util/pbs directory has a set of python scripts which were written to
submit jobs to the PBS pool at the University of Michigan. They aren't
incredibly specialized for that environment, but they do have a little
bit of hard coding which, for instance, uses paths which are only
meaningful there.
The util/batch directory was added alongside a seemingly unrelated
change (perhaps by accident?) and is a slightly updated copy of util/pbs
which also (or instead?) supports OAR.
The qdo script seems to be a script for managing job queues on PBS
and/or OAR, and is also tuned to the UofM environment, for instance
insisting that a path starts with /n/poolfs so that files are available
on an NFS volume shared with the pool.
All three of these scripts could potentially be useful with modification
in a similar environment, but also all three are unmaintained. The
environment in UofM may no longer actually match the expectations of
these scripts, and even if it does/did, gem5 may no longer be 100%
compatible with them.
If these scripts sit in util not being used by anyone, they add clutter
and complexity without adding any value. If someone really needs to know
what was once in them, they can be recovered from revision control.
Change-Id: I0192bd119893f7a41fcb820f4cf408609b03cd27
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30957
Reviewed-by: Steve Reinhardt <stever@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
