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arch-arm: Add Check for AddressSize Fault

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This patch add a check for AddressSize Fault during translation when
MMU is disabled.

Change-Id: Iff3a1543df010b086813869b4b6c4fe776e74499
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30619
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Jordi Vaquero
2020-06-23 11:27:35 +02:00
parent 046645a4db
commit 6002f733cc
2 changed files with 19 additions and 1 deletions
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18
src/arch/arm/tlb.cc
View File

@@ -1011,12 +1011,30 @@ TLB::translateMmuOff(ThreadContext *tc, const RequestPtr &req, Mode mode,
TLB::ArmTranslationType tranType, Addr vaddr, bool long_desc_format)
{
bool is_fetch = (mode == Execute);
bool is_atomic = req->isAtomic();
req->setPaddr(vaddr);
// When the MMU is off the security attribute corresponds to the
// security state of the processor
if (isSecure)
req->setFlags(Request::SECURE);
bool selbit = bits(vaddr, 55);
TCR tcr1 = tc->readMiscReg(MISCREG_TCR_EL1);
int topbit = computeAddrTop(tc, selbit, is_fetch, tcr1, currEL(tc));
int addr_sz = bits(vaddr, topbit, MaxPhysAddrRange);
if (addr_sz != 0){
Fault f;
if (is_fetch)
f = std::make_shared<PrefetchAbort>(vaddr,
ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
else
f = std::make_shared<DataAbort>( vaddr,
TlbEntry::DomainType::NoAccess,
is_atomic ? false : mode==Write,
ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
return f;
}
// @todo: double check this (ARM ARM issue C B3.2.1)
if (long_desc_format || sctlr.tre == 0 || nmrr.ir0 == 0 ||
nmrr.or0 == 0 || prrr.tr0 != 0x2) {

2
src/arch/arm/utility.hh
View File

@@ -237,7 +237,7 @@ Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
bool isInstr);
int computeAddrTop(ThreadContext *tc, bool selbit, bool isInstr,
TTBCR tcr, ExceptionLevel el);
TCR tcr, ExceptionLevel el);
static inline bool
inSecureState(SCR scr, CPSR cpsr)