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arm: Don't use pseudo instructions to implement regular instructions.

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Some ARM instructions were using quiesce and quiesceSkip pseudo
instruction bodies instead of implementing the one line of each of those
functions themselves. This creates two problems. First, it adds an
artificial depedence on the pseudo instruction implementations. Second,
it would confusing cause pseudo instruction DPRINTFs to fire when normal
instructions were executing.

This change simply replaces the calls with their targets one line
implementation, with some very minor duplication from multiple call
sights factored out into a local variable.

Change-Id: I596eafd8714227fa7f69edd542108598c9809b11
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27790
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2020-04-12 22:05:00 -07:00
parent 27e65633f1
commit cc3e12b504
2 changed files with 13 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
src/arch/arm/isa/insts/misc.isa
View File

@@ -721,18 +721,19 @@ let {{
// WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending,
ThreadContext *tc = xc->tcBase();
Tick next_cycle = tc->getCpuPtr()->nextCycle();
if (SevMailbox == 1) {
SevMailbox = 0;
PseudoInst::quiesceSkip(tc);
tc->quiesceTick(next_cycle + 1);
} else if (tc->getCpuPtr()->getInterruptController(
tc->threadId())->checkInterrupts()) {
PseudoInst::quiesceSkip(tc);
tc->quiesceTick(next_cycle + 1);
} else {
fault = trapWFx(tc, cpsr, scr, true);
if (fault == NoFault) {
PseudoInst::quiesce(tc);
tc->quiesce();
} else {
PseudoInst::quiesceSkip(tc);
tc->quiesceTick(next_cycle + 1);
}
}
'''
@@ -760,15 +761,16 @@ let {{
ThreadContext *tc = xc->tcBase();
auto *ic = dynamic_cast<ArmISA::Interrupts *>(
tc->getCpuPtr()->getInterruptController(tc->threadId()));
Tick next_cycle = tc->getCpuPtr()->nextCycle();
if (ic->checkWfiWake(hcr, cpsr, scr)) {
PseudoInst::quiesceSkip(tc);
tc->quiesceTick(next_cycle + 1);
} else {
fault = trapWFx(tc, cpsr, scr, false);
if (fault == NoFault) {
PseudoInst::quiesce(tc);
tc->quiesce();
ArmSystem::callSetStandByWfi(tc);
} else {
PseudoInst::quiesceSkip(tc);
tc->quiesceTick(next_cycle + 1);
}
}
tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);

6
src/arch/arm/isa/templates/pred.isa
View File

@@ -206,7 +206,8 @@ def template QuiescePredOpExecute {{
}
} else {
xc->setPredicate(false);
PseudoInst::quiesceSkip(xc->tcBase());
ThreadContext *tc = xc->tcBase();
tc->quiesceTick(tc->getCpuPtr()->nextCycle() + 1);
}
return fault;
@@ -233,7 +234,8 @@ def template QuiescePredOpExecuteWithFixup {{
} else {
xc->setPredicate(false);
%(pred_fixup)s;
PseudoInst::quiesceSkip(xc->tcBase());
ThreadContext *tc = xc->tcBase();
tc->quiesceTick(tc->getCpuPtr()->nextCycle() + 1);
}
return fault;