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dev-arm: Move GICv2 intConfig for consistency

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Every other helper is placed below the respective array storage

JIRA: https://gem5.atlassian.net/browse/GEM5-667

Change-Id: I398ac23eb68d84a8e0ed856550bfac8e403a86b3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31054
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2020-07-07 10:10:09 +01:00
parent a6721c7a73
commit 548e2884ec
2 changed files with 5 additions and 5 deletions
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2
src/dev/arm/gic_v2.cc
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@@ -72,7 +72,7 @@ GicV2::GicV2(const Params *p)
enabled(false), haveGem5Extensions(p->gem5_extensions),
itLines(p->it_lines),
intEnabled {}, pendingInt {}, activeInt {},
intPriority {}, cpuTarget {}, intConfig {},
intPriority {}, intConfig {}, cpuTarget {},
cpuSgiPending {}, cpuSgiActive {},
cpuSgiPendingExt {}, cpuSgiActiveExt {},
cpuPpiPending {}, cpuPpiActive {},

8
src/dev/arm/gic_v2.hh
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@@ -281,6 +281,10 @@ class GicV2 : public BaseGic, public BaseGicRegisters
}
}
/** 2 bit per interrupt signaling if it's level or edge sensitive
* and if it is 1:N or N:N */
uint32_t intConfig[INT_BITS_MAX*2];
/** GICD_ICFGRn
* get 2 bit config associated to an interrupt.
*/
@@ -319,10 +323,6 @@ class GicV2 : public BaseGic, public BaseGicRegisters
}
}
/** 2 bit per interrupt signaling if it's level or edge sensitive
* and if it is 1:N or N:N */
uint32_t intConfig[INT_BITS_MAX*2];
bool isLevelSensitive(ContextID ctx, uint32_t ix) {
if (ix == SPURIOUS_INT) {
return false;