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arch-arm: AddressSize check on translateMmuOff for AArch64 only

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Motivation:
An AddressSizeFault on AArch32 can only happen during a table walk
since the register used as a base by LD/ST is always 32 bit wide.
On AArch64 on the other hand, addresses can be 64bit wide;
when MMU is off (no virtual memory) an invalid physical address
can be specified

Change-Id: Id3ef170e99202c6b0b511fa7205c754956861720
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31274
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2020-07-14 17:09:11 +01:00
parent 981bdda174
commit 3ce7333a36
1 changed files with 17 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
src/arch/arm/tlb.cc
View File

@@ -1018,21 +1018,23 @@ TLB::translateMmuOff(ThreadContext *tc, const RequestPtr &req, Mode mode,
if (isSecure)
req->setFlags(Request::SECURE);
bool selbit = bits(vaddr, 55);
TCR tcr1 = tc->readMiscReg(MISCREG_TCR_EL1);
int topbit = computeAddrTop(tc, selbit, is_fetch, tcr1, currEL(tc));
int addr_sz = bits(vaddr, topbit, MaxPhysAddrRange);
if (addr_sz != 0){
Fault f;
if (is_fetch)
f = std::make_shared<PrefetchAbort>(vaddr,
ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
else
f = std::make_shared<DataAbort>( vaddr,
TlbEntry::DomainType::NoAccess,
is_atomic ? false : mode==Write,
ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
return f;
if (aarch64) {
bool selbit = bits(vaddr, 55);
TCR tcr1 = tc->readMiscReg(MISCREG_TCR_EL1);
int topbit = computeAddrTop(tc, selbit, is_fetch, tcr1, currEL(tc));
int addr_sz = bits(vaddr, topbit, MaxPhysAddrRange);
if (addr_sz != 0){
Fault f;
if (is_fetch)
f = std::make_shared<PrefetchAbort>(vaddr,
ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
else
f = std::make_shared<DataAbort>( vaddr,
TlbEntry::DomainType::NoAccess,
is_atomic ? false : mode==Write,
ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
return f;
}
}
// @todo: double check this (ARM ARM issue C B3.2.1)