diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index db0d55c972..ca97849356 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1018,21 +1018,23 @@ TLB::translateMmuOff(ThreadContext *tc, const RequestPtr &req, Mode mode,
     if (isSecure)
         req->setFlags(Request::SECURE);
 
-    bool selbit = bits(vaddr, 55);
-    TCR tcr1 = tc->readMiscReg(MISCREG_TCR_EL1);
-    int topbit = computeAddrTop(tc, selbit, is_fetch, tcr1, currEL(tc));
-    int addr_sz = bits(vaddr, topbit, MaxPhysAddrRange);
-    if (addr_sz != 0){
-        Fault f;
-        if (is_fetch)
-            f = std::make_shared<PrefetchAbort>(vaddr,
-                ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
-        else
-            f = std::make_shared<DataAbort>( vaddr,
-                TlbEntry::DomainType::NoAccess,
-                is_atomic ? false : mode==Write,
-                ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
-        return f;
+    if (aarch64) {
+        bool selbit = bits(vaddr, 55);
+        TCR tcr1 = tc->readMiscReg(MISCREG_TCR_EL1);
+        int topbit = computeAddrTop(tc, selbit, is_fetch, tcr1, currEL(tc));
+        int addr_sz = bits(vaddr, topbit, MaxPhysAddrRange);
+        if (addr_sz != 0){
+            Fault f;
+            if (is_fetch)
+                f = std::make_shared<PrefetchAbort>(vaddr,
+                    ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
+            else
+                f = std::make_shared<DataAbort>( vaddr,
+                    TlbEntry::DomainType::NoAccess,
+                    is_atomic ? false : mode==Write,
+                    ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
+            return f;
+        }
     }
 
     // @todo: double check this (ARM ARM issue C B3.2.1)