derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

mem-ruby: Add support for MemSync reqs in VIPER

Browse Source 
Change-Id: Ib129e82be5348c641a8ae18093324bcedfb38abe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29939
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Tony Gutierrez
2019-05-02 19:03:50 -04:00
committed by Anthony Gutierrez
parent 75257c7a42
commit a408b1ada7
3 changed files with 22 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

33
src/mem/ruby/system/GPUCoalescer.cc
View File

@@ -553,24 +553,25 @@ GPUCoalescer::makeRequest(PacketPtr pkt)
assert(pkt->req->hasInstSeqNum());
if (pkt->cmd == MemCmd::MemSyncReq) {
// let the child coalescer handle MemSyncReq because this is
// cache coherence protocol specific
return RequestStatus_Issued;
}
// otherwise, this must be either read or write command
assert(pkt->isRead() || pkt->isWrite());
// issue mem_sync requests immediately to the cache system without
// going through uncoalescedTable like normal LD/ST/Atomic requests
issueMemSyncRequest(pkt);
} else {
// otherwise, this must be either read or write command
assert(pkt->isRead() || pkt->isWrite());
// the pkt is temporarily stored in the uncoalesced table until
// it's picked for coalescing process later in this cycle or in a
// future cycle
uncoalescedTable.insertPacket(pkt);
DPRINTF(GPUCoalescer, "Put pkt with addr 0x%X to uncoalescedTable\n",
pkt->getAddr());
// the pkt is temporarily stored in the uncoalesced table until
// it's picked for coalescing process later in this cycle or in a
// future cycle
uncoalescedTable.insertPacket(pkt);
DPRINTF(GPUCoalescer, "Put pkt with addr 0x%X to uncoalescedTable\n",
pkt->getAddr());
// we schedule an issue event here to process the uncoalesced table
// and try to issue Ruby request to cache system
if (!issueEvent.scheduled()) {
schedule(issueEvent, curTick());
// we schedule an issue event here to process the uncoalesced table
// and try to issue Ruby request to cache system
if (!issueEvent.scheduled()) {
schedule(issueEvent, curTick());
}
}
// we always return RequestStatus_Issued in this coalescer

2
src/mem/ruby/system/GPUCoalescer.hh
View File

@@ -367,7 +367,7 @@ class GPUCoalescer : public RubyPort
// since the two following issue functions are protocol-specific,
// they must be implemented in a derived coalescer
virtual void issueRequest(CoalescedRequest* crequest) = 0;
// virtual void issueMemSyncRequest(PacketPtr pkt) = 0;
virtual void issueMemSyncRequest(PacketPtr pkt) {}
void kernelCallback(int wavefront_id);

8
src/mem/ruby/system/RubyPort.cc
View File

@@ -251,7 +251,7 @@ RubyPort::MemSlavePort::recvTimingReq(PacketPtr pkt)
}
// Check for pio requests and directly send them to the dedicated
// pio port.
if (pkt->cmd != MemCmd::MemFenceReq) {
if (pkt->cmd != MemCmd::MemSyncReq) {
if (!isPhysMemAddress(pkt)) {
assert(ruby_port->memMasterPort.isConnected());
DPRINTF(RubyPort, "Request address %#x assumed to be a "
@@ -312,7 +312,7 @@ RubyPort::MemSlavePort::recvAtomic(PacketPtr pkt)
// Check for pio requests and directly send them to the dedicated
// pio port.
if (pkt->cmd != MemCmd::MemFenceReq) {
if (pkt->cmd != MemCmd::MemSyncReq) {
if (!isPhysMemAddress(pkt)) {
assert(ruby_port->memMasterPort.isConnected());
DPRINTF(RubyPort, "Request address %#x assumed to be a "
@@ -539,7 +539,7 @@ RubyPort::MemSlavePort::hitCallback(PacketPtr pkt)
}
// Flush, acquire, release requests don't access physical memory
if (pkt->isFlush() || pkt->cmd == MemCmd::MemFenceReq) {
if (pkt->isFlush() || pkt->cmd == MemCmd::MemSyncReq) {
accessPhysMem = false;
}
@@ -649,4 +649,4 @@ RubyPort::functionalWrite(Packet *func_pkt)
}
}
return num_written;
}
}