Commit Graph

12328 Commits

Author SHA1 Message Date
Yu-hsin Wang
636d0c3745 base: improve gdb exception information
Even it is an unknow exception for GDB, we still can try to cast it
to std::exception and print some information from `what()`.

Change-Id: Ie0cdc978eb1b3e130bc2153eae99025dcd0109f7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48825
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-02 02:07:17 +00:00
Yu-hsin Wang
29e3e03a97 fastmodel: replace memory space id lookup with getMemorySpaceId
Change-Id: Ib16ea3b92dadc149461fc40f8d85554b7afed656
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48868
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-02 02:07:17 +00:00
Yu-hsin Wang
43c6225da3 fastmodel: correct memory access space id
Change-Id: Ie513c44c362baddc0690cd97a2657f9ccdd06e96
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48823
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-02 02:07:17 +00:00
Yu-hsin Wang
32db3b4042 fastmodel: add memory space id map and getter
Change-Id: Ia9bd467b72ed59ba2b3d2aaf402761779c4e76e9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48867
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-02 02:07:04 +00:00
Gabe Black
e24db5dedd dev: Fix style in i8254xGBE.cc.
Add missing spaces, remove excess spaces.

Change-Id: I9841a80172d3f1edfe68d9d4571535fe253f465e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48926
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-01 17:49:08 +00:00
Gabe Black
c81fd8e076 dev: Fix style in pktfifo.hh.
Put return types of multi-line functions on their own line.

Change-Id: I6c9cade720bd1c7aaa09c42b838c9bd83da7bc8f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48925
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-01 17:48:56 +00:00
Gabe Black
78c85d3bfa dev: Fix style in i8254xGBe_defs.hh.
Functions with more than one line in them put on a single line, lines
over 79 characters, missing spaces after ","s.

Change-Id: If3a1bf7d9b9068608ca70edf9577c0b2e1b44306
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48924
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-01 17:48:44 +00:00
Gabe Black
2cde260198 scons: Stop generating THE_ISA_STR in config/the_isa.hh.
This macro is no longer used or needed.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1056

Change-Id: Ib90f739c2d0df4c655239e55ecfe0da486ee3bf7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48885
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-31 18:07:07 +00:00
Gabe Black
a9af2e8810 sim: Don't serialize a root.isa string in checkpoints.
We are moving away from having a single ISA in a simulation. That means
it will no longer make sense to have a single, particular ISA at the
root of the object hierarchy which applies to the entire simulation.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1056

Change-Id: If4d354ac423e7ab4d3efbc6544d4feea93f56ab3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48884
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-31 18:06:52 +00:00
Tom Rollet
a366e66272 scons: fix hook for 'deprecated' attribute
On the new release, the compilation is polluted by the same warning:
    > ''deprecated' attribute directive ignored

It seems that the hook added in this patch does not work:
https://gem5-review.googlesource.com/c/public/gem5/+/45246/1..7

The snippet of code compile with TryCompile on g++{8,9}.
It probably comes from the fact that the compilation
only creates a warning and not an error.

By adding temporarily '-Werror' for this compilation test,
it filters the faulty gcc versions.

Change-Id: I2b8b7a1a7e06df437b76e98d212947f4f9452311
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48843
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-30 16:22:26 +00:00
Giacomo Travaglini
6add43e0f9 cpu: MiscReg read/writes polluting ExecContext integer stats
Change-Id: Ic505c1157f9008f19bfc500b8f20334c63a64106
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48686
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-30 14:43:48 +00:00
Nathanael Premillieu
2462e650ba mem-cache: reuse local variable in QueuedPrefetcher
Reuse local variable for PA in Queued::translationComplete.

Change-Id: Id3c0333ac1bf019ac21162aedf69f6019c818e30
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48684
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
2021-07-30 13:13:37 +00:00
Nathanael Premillieu
393a964266 mem-cache: print VA and PA in the prefetch queues
As prefetcher can use VA and need translation, it is
interesting to see both VA and PA when printing the queues.
PA is printed as 0 if translation has not happened yet.
Also fix a bug when the pkt is not yet created.

Change-Id: I7cd225379c2930a8d6a7882efdb3dc7bc49fb8a3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48683
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
2021-07-30 07:35:48 +00:00
Gabe Black
555cdefb34 scons: Stop providing an "m5" hard link to the gem5 binary.
gem5 has been called gem5 for a long time, and the m5 binary has not
properly existed for a long time as well. Users have had a very long
time to move to the new binary name, so it should be safe to remove this
bit of legacy cruft.

Change-Id: I8a8ac14f29d25d48afa9db0d906ed4056ac8e961
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48119
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-30 04:51:05 +00:00
Bobby R. Bruce
cec0d074a4 misc: Updated gem5 versioning information for develop branch
Change-Id: I17382ac18dcdce4cdf8c3366886cd41fbcd7d946
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48813
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-30 04:44:09 +00:00
Jason Lowe-Power
eb24bca44e Merge "misc: Merge branch 'release-staging-v21-1' into develop" into develop 2021-07-30 04:44:09 +00:00
Gabriel Busnot
55bb9ebe7b base: Define the gem5_assert macro
gem5_assert is a drop-in replacement for regular assert, except that
the condition must always be valid, compilable code. It allows to
perform clean-up before exiting using the exit method of ExitLogger.

The need for clean-up is detailed in the following issue:
https://gem5.atlassian.net/browse/GEM5-968

Change-Id: Icad1719c0e6fbb066471d1fecfb12eedd65aa690
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45027
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-30 01:01:30 +00:00
Gabe Black
d54dd3bb52 base: Always compile the condition of chatty_assert.
The condition must always be valid code and will always exist to
satisfy the compiler as far as what variables are used, etc, but it
will only actually be evaluated if NDEBUG is not set.

Change-Id: Ia5a6273c95f2e7bf1b7443751fed38c62e73b351
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48605
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-30 01:01:30 +00:00
Matt Sinclair
97760cb5a3 gpu-compute: fix typo in compute driver comments
Change-Id: I550c6c81ffb2ee9143a2676f93385a8b90c4ddd5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48023
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-29 20:00:20 +00:00
Gabe Black
ea2bc1b63f sim,base: Deprecate the GEM5_DEPRECATED_ENUM_VAL attribute.
The deprecated attribute didn't work on versions of gcc older than 6,
but we now require version 7 or newer, so we don't need the macro any
more.

This change collapses the two uses of it in sim/aux_vector.hh, and marks
the macro as deprecated by extending the message string in the
underlying deprecated attribute.

Change-Id: I3bc9835ba19ad9534c7725e17a3558a749a94ca5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48514
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
2021-07-29 10:17:51 +00:00
Gabe Black
00876fff20 misc: Replace the GEM5_VAR_USED macro with [[maybe_unused]].
The [[maybe_unused]] attribute is now standard, so we can use that
directly without hiding it behind a macro.

Change-Id: If24ffd7e50bdb503cb3e6ea61f226ea794e84b8f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48511
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-29 10:17:51 +00:00
Gabe Black
9f92e2f28e base: Deprecate the GEM5_NO_DISCARD macro.
The now standard [[nodiscard]] attribute can be used directly instead.
Unfortunately, I can't think of any way to actually mark the old macro
as deprecated, since it still has to expand to an attribute which
applies to the following function.

Change-Id: Icbbe3e3d182d845f289727724fef080722093683
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48510
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-07-29 10:17:51 +00:00
Yu-hsin Wang
8fa9dceaa8 fastmodel: Remove CortexA76 unpresented resource
Change-Id: I8fde5f90cca45df9430c5f4159fa6e8319ad12df
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44527
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-29 05:46:45 +00:00
Bobby R. Bruce
76ceda55f7 misc: Merge branch 'release-staging-v21-1' into develop
Change-Id: I0f69d3d0863f77c02ac8089fb4dccee3aa70a4ea
2021-07-28 17:37:04 -07:00
Jan Vrany
a5789cc8e1 base: Change prototype of BaseRemoteGDB::trap()
Change the return type of BaseRemoteGDB::trap() to void since the
return value was never used by any of the callers. Also change the
name of second parameter to signum since its value is reported back
to GDB in "S" packet.

Change-Id: I81acfac24ffe62e4ffae6b74bf33f1f07ada3ca7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48180
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-28 09:02:40 +00:00
Giacomo Travaglini
46a8bc2f56 arch: Provide an alternative view of the TLBs in the BaseMMU
It is possible from the MMU to traverse the entire hierarchy of
TLBs, starting from the DTB and ITB (generally speaking from the
first level) up to the last level via the nextLevel pointer. So
in theory no extra data should be stored in the BaseMMU.

This design makes some operations a bit more complex. For example
if we have a unified (I+D) L2, it will be pointed by both ITB and
DTB. If we want to invalidate all TLB entries, we should be
careful to not invalidate L2 twice, but if we simply follow the
next level pointer, we might do so. This is not a problem from
a functional perspective but alters the TLB statistics (a single
invalidation is recorded twice)

We then provide a different view of the set of TLBs in the system.
At the init phase we traverse the TLB hierarchy and we add every
TLB to the appropriate set. This makes invalidation (and any
operation targeting a specific kind of TLBs) easier.

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: Ieb833c2328e9daeaf50a32b79b970f77f3e874f7
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48146
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2021-07-28 08:13:09 +00:00
Giacomo Travaglini
76996ea806 arch: Add a nextLevel pointer to BaseTLB
This is a step towards supporting multi-level TLBs:
Every TLB will have a pointer to the next level TLB in the
hierarchy.

Example:

* L1 I-TLB
* L1 D-TLB
* L2 shared TLB (I+D)

l2 = BaseTLB()
itb = BaseTLB(next_level=l2)
dtb = BaseTLB(next_level=l2)

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I398a17919564aad4b18efb8dace096965781ece1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48145
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2021-07-28 08:13:09 +00:00
Giacomo Travaglini
1320dc4278 arch-arm: Remove unused parameter from TLB::insert
Change-Id: Iab395834fe8b3fabf4f5f666af1b8790af08182d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48144
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-07-28 08:13:09 +00:00
Giacomo Travaglini
65195c8011 arch-arm, configs: Remove ArmITB/ArmDTB
Removing ArmITB and ArmDTB makes sense as it implies a fixed 2 TLBs
system; by using the generic ArmTLB class we open up to a more generic
configuration

This is also aligning to the other ISAs

Change-Id: Ifc5cf7c41484d4f45b14d1766833ad4c4f7e9e86
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48143
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2021-07-28 08:13:09 +00:00
Giacomo Travaglini
9964a3aca7 arch: Add TypeTLB Param in BaseTLB
This patch is adding an enum Param in the BaseTLB to tag which kind of
translation entries the TLB is holding

* instruction: holding instruction entries
* data: holding data entries
* unified: holding instruction and data entries

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I033f840652f354523f48e9eb78033ea759b5d0e0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48142
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-28 08:13:09 +00:00
Giacomo Travaglini
870f93301f arch-arm: Move translation logic from the ArmTLB to the ArmMMU
This patch is moving most of the TLB code to the MMU.
In this way the TLB stops being the main translating agent and becomes a
simple "passive" translation cache.

All the logic behind virtual memory translation, like

* Checking permission/alignment
* Issuing page table walks
* etc

Is now embedded in the MMU model. This will allow us to stack multiple
TLBs and to compose arbitrary hierarchies as their sole purpose now is
to cache translations

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I687c639a56263d5e3bb6633dd8c9666c85edba3a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48141
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-28 08:13:09 +00:00
Gabe Black
b3b81196aa misc: Replace type_traits.hh XX::value with XX_v.
Now that we're using c++17, the type_traits with a ::value member have
a _v alias which reduces verbosity. Or on other words

std::is_integral<T>::value

can be replaced with

std::is_integral_v<T>

Make this substitution throughout the code base. In places where gem5
introduced it's own similar templates, add a V alias, spelled
differently to match gem5's internal style.

gem5: :IsVarArgs<T>::value => gem5::IsVarArgsV<T>
Change-Id: I1d84ffc4a236ad699471569e7916ec17fe5f109a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48604
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-28 01:48:03 +00:00
Yu-hsin Wang
8b53b8bcdf fastmodel: Use Iris API to access memory
Memory space is not always outside of the CPU. For example the tightly
coupled memory (TCM) is inside of the core. To make gdb access those
kind of memory, we should use Iris memory API to read and write memory.
If we access a memory address not inside the CPU with Iris memory API.
The CPU would fire a request via amba transport_dbg. So the change also
covers the original behavior.

Change-Id: Ie223ab12f9a746ebafa21026a8680222f6ebd593
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45581
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-28 00:33:02 +00:00
Gabe Black
7901e56206 dev: Drop include of drm/drm.h in kfd_ioctl.h.
I don't have this header on one of the machines I build on, so this is
breaking the build for me. Removing this include seems to make the
build succeed, implying that it's not actually necessary. I looked at
the file it's used in and didn't see anything that looked like it came
from this header file.

Change-Id: If4a29063d6d0d25904183cab78c9713ff1f8daa6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48603
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-27 21:34:58 +00:00
Gabe Black
2f42e79956 mem: Use the new "debug" namespace, and not "Debug".
The "Debug" namespace is deprecated and has been replaced by "debug".

Change-Id: Ic8e9082361a6717f3b07990dbaa1a66b0926f000
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48647
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-27 21:32:21 +00:00
Gabe Black
be3e6174d6 fastmodel: Minimally implement reading MiscRegs for the CortexR52.
This currently supports only the CPSR and SPSR currently. The CPSR is
needed to be able to read the PC since that also reads other related
info which ultimately comes from the CPSR. The SPSR is also set up
since it was easy to do at the same time.

Change-Id: I977fde47c81927f4972d4da2e781df306dfa3f4e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46139
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-27 21:29:06 +00:00
Bobby R. Bruce
5586b84298 misc: Update the version to v21.1.0.0
Change-Id: I4174611bdaf68673f77a446e979776ad502ae20b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48583
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-27 18:20:12 +00:00
Yu-hsin Wang
4560cf8531 fastmodel: add iris readMem and writeMem function
Iris memory API allows us to access the memory inside the core, for
example the tightly coupled memory (TCM). If we access a memory address
which is not in the CPU, it also fire a request to memory system.

Change-Id: I5925214534a10e3a55b780c3d4ed06e7559aafe0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45268
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-27 01:07:11 +00:00
Giacomo Travaglini
4ae8db4aa4 arch, arch-arm: Make BaseMMU translate methods virtual
As we are shifting towards making the MMU the main translating
agent, we need to make those methods virtual to let all ISAs
move their TLB::translate* methods to the MMU class

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I50c84784546e8148230d79efe4bf010d0e36d6ab
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48140
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-26 23:29:46 +00:00
Kyle Roarty
906bb599d4 sim-se: Properly handle a clone with the VFORK flag
When clone is called with the VFORK flag, the calling process is
suspended until the child process either exits, or calls execve.

This patch adds in a new variable to Process, which is used to store the
context of the calling process if this process is created through a
clone with VFORK set.

This patch also adds the required support in clone to suspend the
calling thread, and in exitImpl and execveFunc to wake up the calling
thread when the child thread calls either of those functions

Change-Id: I85af67544ea1d5df7102dcff1331b5a6f6f4fa7c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48346
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
2021-07-26 18:37:01 +00:00
Kyle Roarty
078dc689b9 sim-se: Fix execve syscall
There were three things preventing execve from working

Firstly, the entrypoint for the new program wasn't correct. This was
fixed by calling Process::init, which adds a bias to the entrypoint.

Secondly, the uname string wasn't being copied over. This meant when the
new executable tried to run, it would think the kernel was too old to
run on, and would error out. This was fixed by copying over the uname
string (the `release` string in Process) when creating the new process.

Additionally, this patch also ensures we copy over the uname string in
the clone implementation, as otherwise a cloned thread that called
execve would crash.

Finally, we choose to not delete the new ProcessParams or the old
Process. This is done both because it matches what is done in cloneFunc,
but also because deleting the old process results in a segfault later
on.

Change-Id: I4ca201da689e9e37671b4cb477dc76fa12eecf69
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48345
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-26 18:36:55 +00:00
Kyle Roarty
1577897265 arch-gcn3: Validate if scalar sources are scalar gprs
Scalar sources can either be a general-purpose register or a constant
register that holds a single value.

If we don't check for if the register is a general-purpose register,
it's possible that we get a constant register, which then causes all of
the register mapping code to break, as the constant registers aren't
supposed to be mapped like the general-purpose registers are.

This fix adds an isScalarReg check to the instruction encodings that
were missing it.

Change-Id: I3d7d5393aa324737301c3269cc227b60e8a159e4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48344
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
2021-07-26 18:36:24 +00:00
Kyle Roarty
9a7fc4ff69 arch-gcn3: Implement LDS accesses in Flat instructions
Add support for LDS accesses by allowing Flat instructions to dispatch
into the local memory pipeline if the requested address is in the group
aperture.

This requires implementing LDS accesses in the Flat initMemRead/Write
functions, in a similar fashion to the DS functions of the same name.

Because we now can potentially dispatch to the local memory pipeline,
this change also adds a check to regain any tokens we requested as a
flat instruction.

Change-Id: Id26191f7ee43291a5e5ca5f39af06af981ec23ab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48343
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-26 18:36:16 +00:00
Bobby R. Bruce
c0a3c70304 misc: Merge branch 'release-staging-v21-1' into develop
Change-Id: I6ba57d7f70be70ae43fab396780d18623679a59a
2021-07-26 09:48:25 -07:00
Gabe Black
59496b6136 mem,gpu-compute: Stop using the GEM5_NO_DISCARD macro.
The [[nodiscard]] attribute is now standard, so we can use that
directly.

Change-Id: I57f59935858facb2a15bf4712be4bfd584bf0c7e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48509
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-24 21:57:04 +00:00
Gabe Black
b17f4c3037 base: Deprecate the GEM5_DEPRECATED macro.
The [[deprecated()]] attribute is now standard, so we don't need to hide
it behind a macro.

Change-Id: Icfa6ad8b75ac64330f50f72fa310e104161bbf9d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48508
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-24 21:57:04 +00:00
Gabe Black
89529e6261 sim: Use the [[deprecated()]] attribute instead of GEM5_DEPRECATED.
The [[deprecated()]] attribute is now standard c++, so use that
directly.

Change-Id: I246551b05484a707ac9da05dc91af34d78aae1ff
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48507
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-24 21:57:04 +00:00
Gabe Black
5590f2a903 base: Deprecate the GEM5_FALLTHROUGH macro.
The [[fallthrough]] attribute is now standard.

Change-Id: I9ab115f0135256a701efaa9a6c7ba4e966283f4b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48506
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-24 21:57:04 +00:00
Gabe Black
cb266a099f misc: Replace GEM5_FALLTHROUGH with [[fallthrough]].
Now that the [[fallthrough]] attribute is standard (as of c++-17), we
can use it directly instead of hiding it behind a macro.

Change-Id: I4d11e35b619532b1a3fd8d042265e18c80d86f9b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48505
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-24 21:57:04 +00:00
Kyle Roarty
523a92f7f0 arch-gcn3: Implement large ds_read/write instructions
This implements the 96 and 128b ds_read/write instructions in a similar
fashion to the 3 and 4 dword flat_load/store instructions.

These instructions are treated as reads/writes of 3 or 4 dwords, instead
of as a single 96b/128b memory transaction, due to the limitations of
the VecOperand class used in the amdgpu code.

In order to handle treating the memory transaction as multiple dwords,
the patch also adds in new initMemRead/initMemWrite functions for ds
instructions. These are similar to the functions used in flat
instructions for the same purpose.

Change-Id: I0f2ba3cb7cf040abb876e6eae55a6d38149ee960
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48342
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Alex Dutu <alexandru.dutu@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
2021-07-24 17:27:02 +00:00