arch: Add a nextLevel pointer to BaseTLB

This is a step towards supporting multi-level TLBs:
Every TLB will have a pointer to the next level TLB in the
hierarchy.

Example:

* L1 I-TLB
* L1 D-TLB
* L2 shared TLB (I+D)

l2 = BaseTLB()
itb = BaseTLB(next_level=l2)
dtb = BaseTLB(next_level=l2)

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I398a17919564aad4b18efb8dace096965781ece1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48145
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

src/arch/generic/BaseTLB.py

@@ -67,3 +67,5 @@ class BaseTLB(SimObject):
                     '`master` is now called `mem_side_port`')
 
     entry_type = Param.TypeTLB("Instruction/Data/Unified TLB entries")
+
+    next_level = Param.BaseTLB(NULL, "next level")

src/arch/generic/tlb.hh

@@ -57,11 +57,13 @@ class BaseTLB : public SimObject
 {
   protected:
     BaseTLB(const BaseTLBParams &p)
-      : SimObject(p), _type(p.entry_type)
+      : SimObject(p), _type(p.entry_type), _nextLevel(p.next_level)
     {}
 
     TypeTLB _type;
 
+    BaseTLB *_nextLevel;
+
   public:
     virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
 
@@ -119,6 +121,8 @@ class BaseTLB : public SimObject
     void memInvalidate() { flushAll(); }
 
     TypeTLB type() const { return _type; }
+
+    BaseTLB* nextLevel() const { return _nextLevel; }
 };
 
 } // namespace gem5