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fastmodel: Remove CortexA76 unpresented resource

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Change-Id: I8fde5f90cca45df9430c5f4159fa6e8319ad12df
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44527
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Yu-hsin Wang
2021-04-15 18:27:33 +08:00
parent a5789cc8e1
commit 8fa9dceaa8
1 changed files with 2 additions and 2 deletions
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4
src/arch/arm/fastmodel/CortexA76/thread_context.cc
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@@ -530,7 +530,7 @@ Iris::ThreadContext::IdxNameMap CortexA76TC::miscRegIdxNameMap({
{ ArmISA::MISCREG_CNTV_CVAL, "CNTV_CVAL" },
{ ArmISA::MISCREG_CNTVOFF, "CNTVOFF" },
{ ArmISA::MISCREG_CNTHP_CVAL, "CNTHP_CVAL" },
{ ArmISA::MISCREG_CPUMERRSR, "CPUMERRSR" },
// ArmISA::MISCREG_CPUMERRSR?
{ ArmISA::MISCREG_L2MERRSR, "L2MERRSR" },
// AArch64 registers (Op0=2)
@@ -814,7 +814,7 @@ Iris::ThreadContext::IdxNameMap CortexA76TC::miscRegIdxNameMap({
// ArmISA::MISCREG_L2ACTLR_EL1?
{ ArmISA::MISCREG_CPUACTLR_EL1, "CPUACTLR_EL1" },
{ ArmISA::MISCREG_CPUECTLR_EL1, "CPUECTLR_EL1" },
{ ArmISA::MISCREG_CPUMERRSR_EL1, "CPUMERRSR_EL1" },
// ArmISA::MISCREG_CPUMERRSR_EL1?
{ ArmISA::MISCREG_L2MERRSR_EL1, "L2MERRSR_EL1" },
// ArmISA::MISCREG_CBAR_EL1?
{ ArmISA::MISCREG_CONTEXTIDR_EL2, "CONTEXTIDR_EL2" },