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4896 Commits

Author SHA1 Message Date
Giacomo Travaglini
4808a22dae arch-arm: Add utimes implementation to the Syscall Table 
Change-Id: If618bd4d746daa42e33ac91721ba2b23c6880bf6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51058
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
 2021-10-20 15:10:45 +00:00
Giacomo Travaglini
3627659ccb arch-arm: Add mknodat implementation to the Syscall Table 
Change-Id: Ib01443f5304da511ff41010d35bdda71e20e3f93
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51057
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
 2021-10-20 15:10:45 +00:00
Gabe Black
73025695c7 scons: Use tags to gate ISA files and not env['TARGET_ISA']. 
Change-Id: Ib81a4c570fbb050fa7d82919edacfed004c6800e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50336
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
 2021-10-19 20:41:03 +00:00
Gabe Black
305a81aae7 arch: Consolidate common debug flags. 
Consolidate debug flags which are defined separately in multiple ISAs in
arch/SConscript instead. This will prevent conflicts when more than one
ISA can be compiled at a time.

Change-Id: I70862c403d19f04bbcbabd74dd751ca92d1ed942
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50334
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2021-10-19 10:53:44 +00:00
Gabe Black
038bf7075a scons: Use unions to prevent debug flag destruction. 
When an object is a field in a union, it's the programmer's
resposibility to destroy it from the union's destructor. We can simply
neglect to do that and avoid having to use new to create the flags.

Also, we can define the flags as inline variables (a c++17 feature), and
then create a constexpr references to them. This lets us refer to debug
flags in constexpr objects, although we can't interact with them at, for
instance, construciton time or we'd lose our own constexpr-ness since
the actual object is not constexpr.

In c++20 we would hypothetically be able to use constexpr with new and
delete, but there may be additional restrictions that would make this
particular use impossible. Also this avoids leaking memory, which, even
though it's intentional, may confuse tools like valgrind.

Also, we need to ensure that all headers are included in some source
file so that they exist in the final executable, so that they show up in
the help, can be enabled/disabled, etc.

Change-Id: Ia43111d938e7af7140b1c17dd68135f426d0a1e9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49783
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jui-min Lee <fcrh@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-10-19 10:53:44 +00:00
Giacomo Travaglini
1b2083fc53 arch-arm: Add mknod implementation to the Syscall Table 
Change-Id: Ie5af5c4223e015d04aadda125f3131683a06463f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51055
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
 2021-10-19 08:48:49 +00:00
Giacomo Travaglini
dcf4e11a15 arch-arm: Add mkdirat implementation to the Syscall Table 
Change-Id: I1323faf583b1dd1192515f6e598e1616dc14de11
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51054
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
 2021-10-19 08:48:49 +00:00
Giacomo Travaglini
6c9792d333 arch-arm: EL2&0 invalidations do not depend on VMID 
When the PE is executing in host mode (HCR.E2H = HCR.TGE = 1)
The invalidation shouldn't depend on the current VMID

Change-Id: I3433485cc8f8dedb657139bcc3d71e05e9d7e4f1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51671
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2021-10-18 13:47:18 +00:00
Giacomo Travaglini
655349a9ca arch-arm: Use EL2&0 regime for invalidation only if EL2 enabled 
Change-Id: I467a27e48d077cea5e56afae08f9e0e72f529cfc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51670
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2021-10-18 13:47:18 +00:00
Giacomo Travaglini
f49a15e00f arch-arm: Define a Lookup structure to simplify TLB code 
The lookup/matching function signatures have been constantly amended to
include new parameters. We are replacing the parameter list with a
single lookup structure. This will make it easier to add new forms of
lookups and to propagate them through the MMU/TLB code

Change-Id: Ic45a64d778460b6d308551333c9dc230a02ecb6e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51669
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2021-10-18 13:47:18 +00:00
Giacomo Travaglini
b29349671c arch-arm: EL2/EL3 TLB invalidations should ignore the ASID 
By using the TLBIMVAA class we invalidate for every ASID

Change-Id: Ie53747067275b01eab42d49b5fa518334a86ac53
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51668
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2021-10-18 13:47:18 +00:00
Giacomo Travaglini
8fe7a740e3 arch-arm: Do not always print 0 stats in ArmTLB 
We shouldn't print all TLB stats regardless of their value

For example there is no need to print the number of
read/write hits/misses/accesses in a instruction only TLB as
it will always inevitably be zero

With this patch we are flagging them as nozero, in order
to suppress their printing in the final stats file.
We are still printing them (regardless of their value) in the
unified TLB type

Change-Id: I54e57d856ceb451f6bacdd175a61768d030862aa
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51667
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-10-18 13:47:18 +00:00
Gabe Black
5c8c981cdd arch-sparc: Fix the build for SPARC. 
The fp_enable_check mechanism was removed recently, but the removal was
only partial for SPARC which broke its build. This change completes the
removal by finishing the necessary code substitutions.

Change-Id: I3a6a6cd679b08556e5e4a2a2c4e98168ee7fe1fd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51673
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-10-15 10:13:42 +00:00
Gabe Black
2887a996e1 fastmodel: Don't try to "staticify" system libraries. 
We want to insist that the fast model libraries are the static versions
so they don't have to be found on non-system paths at run time, but we
don't need or want to do the same for system libraries which are from
standard paths on the host system.

Split the set of libraries fast model adds to the build into ones that
come from fast model itself, and ones it needs which should be
provided by the system. The ones from fast model itself should still
go through staticify, but the system libraries should be passed to the
compiler generically so it can pick which version it wants.

Change-Id: I222c94f8117143b86377150e686a4af669a994fe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51627
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-10-14 11:39:52 +00:00
Giacomo Travaglini
133997d515 arch-arm: Add chdir implementation to the Syscall Table 
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I584d9269b0445347dd65071f7fc5569c8ac24b89
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51549
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-10-14 08:52:39 +00:00
Gabe Black
1ee4c4ce43 arch-power: Replace the Loader namespace with loader. 
The Loader namespace is deprecated, and is replaced with loader.

Change-Id: Ic973eefd55c6f8a43d3d41346b8b6e4795e19e55
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51527
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-10-13 20:29:08 +00:00
Gabe Black
8304ed1967 base,arch-arm: Replace Stats namespace with statistics. 
The Stats namespace is deprecated.

Change-Id: I17b1aa7fbced5db7b325e5339395281f3b3eda0b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51528
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-10-13 20:28:52 +00:00
Gabe Black
ad944025ab scons,arch: Make the gem5 lib tag imply the current arch tag. 
That way you can use the tag to specify when a source file should be
built, instead of conditionally declaring the file to SCons.

Change-Id: Ia3a23860d2ee39ec6b32ee2195648b4d88564c83
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50330
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-10-13 20:22:37 +00:00
Gabe Black
79953cf973 scons: Add tag support to ISADesc. 
Change-Id: Icac027cc4df48d0a3c06911bd6fa0a8b5b72c60a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50329
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-10-13 20:22:37 +00:00
Gabe Black
bc1438414a sparc: Stop using fp_enable_check. 
SPARC and MIPS are the only ISAs using this mechanism. This is a step
towards making them self sufficient and simplifying the ISA parser, it's
interface to the rest of gem5, and it's assumptions about how ISAs are
structured.

Change-Id: Ied85d5012a806321fd717f654d940171da3450af
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48717
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
 2021-10-13 07:59:52 +00:00
Gabe Black
645c6b3ceb sparc: Stop special casing FP enable checks for full system. 
Set the actual state which gets checked in full system, and then do that
all the time.

Change-Id: I27ea0939ad71f7399b676e22ec2e73e3e0dd6476
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48716
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
 2021-10-13 07:59:52 +00:00
Gabe Black
7d92144e1b arch,sparc: Get rid of the unused checkVecEnableFault mechanism. 
The method was only defined in SPARC, and SPARC does not use the vector
register file.

Change-Id: I4112eadaecb1f1c6c6db12975bec0cd1fa245d6c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48715
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
 2021-10-13 07:59:52 +00:00
Giacomo Travaglini
851e543b2f misc: Using OS::off_t in syscall signature 
Change-Id: Iefa1e207a3e825959b0fe8df30e6be182d73a0f8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51490
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-10-13 07:44:00 +00:00
Giacomo Travaglini
37495f8823 misc: Using OS::size_t in syscall signature 
Using the host size_t is confusing the guest ABI engine every time
the host and the guest adopt a different data model (ILP32 vs LP64)

For example when a LP64 machine is running an ILP32 application in SE
mode, "size_t" will wrongly inform the guest ABI engine to retrieve the
argument by loading a 64 bit (instead of 32) value from the stack

JIRA: https://gem5.atlassian.net/browse/GEM5-1074

Change-Id: Id7d7740ac429f534a4089331bedf21dc3951bbad
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51489
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-10-13 07:44:00 +00:00
Giacomo Travaglini
43910b5312 arch-arm: Add ftruncate implementation to the Syscall Table 
Change-Id: I27c526c5c8107f888aee7c99b952f086d4fa0e35
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51488
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-10-13 07:44:00 +00:00
Giacomo Travaglini
2644cc3cac arch-arm: Add sendto and recvfrom implementations to the Syscall Table 
Change-Id: Id3fd65778ad3b5af8ec54381a0b8824115c309f6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51487
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-10-13 07:44:00 +00:00
Giacomo Travaglini
ac63b7e294 arch-arm: Add fchownat implementation to the Syscall Table 
Change-Id: If2e05b84064886bd924348930a151c7c00877c38
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51052
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-10-12 15:19:32 +00:00
Giacomo Travaglini
f9a7196396 arch-arm: Add fchown implementation to the Syscall Table 
Change-Id: I4696e305383492e3bf3cf079ffb68eac24f6a19d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51051
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-10-12 15:19:32 +00:00
Giacomo Travaglini
b1a2d5f293 arch-arm: Add existing at impl to ArmLinux32 Syscall Table 
Change-Id: Ia1e7cb02ce9513e6ef5d7037dafc84fbd52b8504
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51049
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
 2021-10-12 15:19:32 +00:00
Eduardo José Gómez Hernández
2b46872ee9 arch-x86: Fixed M5InternalError when decoding certain bytes 
0F 38 is the two bytes prefixes to decode a three-byte opcode.
To prevent errors, the two_bytes_opcode decoder will complain
if it tries to decode 38 as the opcode, because it is a prefix.
The decoder, will treat 38 as a prefix, preventing it to
end in the two_byte_opcode decoder.

However, using the VEX prefix is possible to reach this
forbidden state.

The set of bytes C4 01 01 38 00 will trigger the mentioned
M5InternalError.

The previous instruction is not valid, but it could be
decoded from an speculative path. In its place, a UD2
instructtion should be emitted if the VEX prefix is
present.

Change-Id: I6b7c4b3593dd8e6e8ac99aaf306b8feeb7784b56
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49990
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-10-07 07:06:37 +00:00
Matthew Poremba
3112a7f0d0 arch-gcn3,gpu-compute: Move GCN3 specific TLB to arch 
Move GpuTLB and TLBCoalescer to GCN3 as the TLB format is specific to
GCN3 and SE mode / APU simulation. Vega will have its own TLB,
coalescer, and walker suitable for a dGPU. This also adds a using alias
for the TLB translation state to reduce the number of references to
TheISA and X86ISA. X86 specific includes are also removed.

Change-Id: I34448bb4e5ddb9980b34a55bc717bbcea0e03db5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49847
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-10-04 23:47:03 +00:00
Matthew Poremba
c15e472199 arch-vega: Rework flat instructions to support global 
Global instructions are new in Vega and are essentially FLAT
instructions from GCN3 but guaranteed to go to global memory where as
flat can go to global or local memory.

This reworks the flat instruction classes so that the initiateAcc /
execute / completeAcc logic can be reused for flat, global, and later
scratch subtypes of flat instructions. The decoder creates a flat
instruction class which sets instruction flags based on the flat
instruction's SEG field. There are new initOperandInfo and
generateDissasmbly methods for flat and global. The number of operands
and operand index getters are modified to check the flags and return the
correct value for the subtype.

Change-Id: I1db4a3742aeec62424189e54c38c59d6b1a8d3c1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47106
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Kyle Roarty <kyleroarty1716@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-10-04 22:51:37 +00:00
Giacomo Travaglini
496dc2457c arch-arm: With FEAT_SEL2 isStage2 -> NS doesn't hold anymore 
Change-Id: If71be69808ae97a12770b477d4f08005d35bff2d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51148
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-10-01 08:21:51 +00:00
Gabe Black
f1735afad3 misc: Include static_inst_fwd.hh in sim/faults.hh. 
We only need a StaticInstPtr type, so we don't need to include all of
static_inst.hh. Also fix up some other files which were including some
other things transitively through sim/faults.hh.

Change-Id: I912a84963f33d99617f57d59517c402326f7a494
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50756
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2021-10-01 04:57:56 +00:00
Kyle Roarty
008659bee1 arch-gcn3: Fix MUBUF out-of-bounds case 1 
This patch upates the out-of-bounds check to properly check
against the correct buffer_offset, which is different depending
on if the const_swizzle_enable is true or false.

Change-Id: I5c687c09ee7f8e446618084b8545b74a84211d4d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51127
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Alex Dutu <alexandru.dutu@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-09-30 20:22:35 +00:00
Giacomo Travaglini
a1de03150f arch-arm: Remove duplicate sys param from ArmMMU 
Change-Id: I3f906a1c1076170e8b751d3cfdbf16627cf8c2ac
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51147
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-09-30 16:27:13 +00:00
Giacomo Travaglini
cab5abd0d9 arch-arm: Add an Armv8.4 ArmRelease object 
Change-Id: I0fc4301be2b4f3fa29c4320ab747bfa88132d434
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51021
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2021-09-30 16:03:41 +00:00
Giacomo Travaglini
d2157a81df arch-arm: Add an Armv8.3 ArmRelease object 
Change-Id: I7bd5fee4a5958f6669e1d0ac29e0c62f8f019204
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51020
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2021-09-30 16:03:41 +00:00
Giacomo Travaglini
8156bc0dc1 arch-arm: Add missing Armv8.3 extensions to the enum 
Change-Id: Id3897c59a12189f4aac6a3923f656e1f6b8f6723
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51019
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
 2021-09-30 16:03:41 +00:00
Giacomo Travaglini
a174513320 arch-arm: Add an Armv8.2 ArmRelease object 
Change-Id: I731dde9687b36dc769b18cadcffe07a70868e965
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51018
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2021-09-30 16:03:41 +00:00
Giacomo Travaglini
10cbcb14e8 arch-arm: Add missing Armv8.2 extensions to the enum 
Change-Id: Ie98d06909fada7ca1370f2283ef0fce61b6dc953
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51017
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2021-09-30 16:03:41 +00:00
Giacomo Travaglini
d8c61b2e24 arch-arm: Add an Armv8.1 ArmRelease object 
Change-Id: I5638deb77a165bec1ee47d8f1b2bac31647f173a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51016
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2021-09-30 16:03:41 +00:00
Giacomo Travaglini
03f79f47d8 arch-arm: FEAT_SEL2 is not part of ID_AA64ISAR0_EL1 
Change-Id: I81cb3e8f400eaf8abc1dea61f592239e52501ab1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51015
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2021-09-30 16:03:41 +00:00
Giacomo Travaglini
e77ebef6b6 arch-arm: Add missing Armv8.1 extensions to the enum 
Change-Id: I90c7eb2b22d317f5a60b020c731948681e9f91a1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51014
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2021-09-30 16:03:41 +00:00
Giacomo Travaglini
24dfe8a41c arch-arm: Do not use FEAT_SEL2 in SE mode 
SecureEL2 doesn't make sense for a userspace only simulation

Change-Id: Ieda56cc6684f7c011b31ca754e971fb9a9fb6899
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51013
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2021-09-30 16:03:41 +00:00
Giacomo Travaglini
abbd0fbad9 arch-arm: Use ArmRelease in the ISA class 
This is removing the cached boolean variables from the ISA class.
The ISA is now using a release object.

It is importing it from the ArmSystem in case of a FS simulation,
and it is using its own ArmRelease object in SE mode

This allows us to add/remove SE extensions from python, rather than
hardcoding them in the ISA constructor (in case of SE)

Change-Id: I2b0b2f113e7bb9e28ac86bf2139413e2a71eeb01
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51012
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2021-09-30 16:03:41 +00:00
Gabe Black
1a1ba692c3 sim: Move the MemPools object out of System and into SEWorkload. 
This removes the need for all the FullSystem checks in the System class,
and simplifies that class in general.

Change-Id: Ie8a3bc67db9195027d2111009b15ca59221bdeb2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50348
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-09-30 00:30:49 +00:00
Giacomo Travaglini
152760ee51 arch-arm: Define an ArmRelease class to handle ISA extensions 
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I3240853bd2123a6f24b2bb64c90ad457696f0d93
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51010
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-09-29 22:16:03 +00:00
Giacomo Travaglini
d1ddbdead8 arch-arm: Prefer haveEL over haveSecurity and haveVirtualization 
The Arm architecture reference manual pseudocode checks for the presence
of an exception level (EL) over "security" and "virtualization"

Change-Id: Ia91a9d1848eddc40776627208386a13afdaafda3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51009
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-09-29 07:27:59 +00:00
Gabe Black
ede1ad4b8c arch,cpu,mem,sim: Fold arch/locked_mem.hh into the BaseISA class. 
Turn the functions within it into virtual methods on the ISA classes.
Eliminate the implementation in MIPS, which was just copy pasted from
Alpha long ago. Fix some minor style issues in ARM. Remove templating.
Switch from using an "XC" type parameter to using the ThreadContext *
installed in all ISA classes.

The ARM version of these functions actually depend on the ExecContext
delaying writes to MiscRegs to work correctly. More insiduously than
that, they also depend on the conicidental ThreadContext like
availability of certain functions like contextId and getCpuPtr which
come from the class which happened to implement the type passed into XC.

To accomodate that, those functions need both a real ThreadContext, and
another object which is either an ExecContext or a ThreadContext
depending on how the method is called.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1053

Change-Id: I68f95f7283f831776ba76bc5481bfffd18211bc4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50087
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-09-28 19:56:01 +00:00