Giacomo Travaglini 24dfe8a41c arch-arm: Do not use FEAT_SEL2 in SE mode ...

SecureEL2 doesn't make sense for a userspace only simulation

Change-Id: Ieda56cc6684f7c011b31ca754e971fb9a9fb6899
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51013
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

2021-09-30 16:03:41 +00:00

..

amdgpu

arch-vega: Fix VEGA_X86 build issues

2021-09-27 22:30:30 +00:00

arm

arch-arm: Do not use FEAT_SEL2 in SE mode

2021-09-30 16:03:41 +00:00

gcn3

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

generic

arch,cpu,mem,sim: Fold arch/locked_mem.hh into the BaseISA class.

2021-09-28 19:56:01 +00:00

isa_parser

python,scons: Move grammar.py and code_formatter.py into build_tools.

2021-09-24 21:23:27 +00:00

mips

sim: Move the MemPools object out of System and into SEWorkload.

2021-09-30 00:30:49 +00:00

null

arch,cpu,mem,sim: Fold arch/locked_mem.hh into the BaseISA class.

2021-09-28 19:56:01 +00:00

power

sim: Move the MemPools object out of System and into SEWorkload.

2021-09-30 00:30:49 +00:00

riscv

sim: Move the MemPools object out of System and into SEWorkload.

2021-09-30 00:30:49 +00:00

sparc

sim: Move the MemPools object out of System and into SEWorkload.

2021-09-30 00:30:49 +00:00

x86

sim: Move the MemPools object out of System and into SEWorkload.

2021-09-30 00:30:49 +00:00

micro_asm_test.py

arch, mem, cpu, systemc: Remove Python 2.7 glue code

2021-01-27 10:18:43 +00:00

micro_asm.py

arch, mem, cpu, systemc: Remove Python 2.7 glue code

2021-01-27 10:18:43 +00:00

SConscript

arch,cpu,mem,sim: Fold arch/locked_mem.hh into the BaseISA class.

2021-09-28 19:56:01 +00:00

SConsopts

scons: Turn the ISA and GPU ISA lists into construction variables.

2021-08-07 03:12:56 +00:00