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arch-arm: Add missing Armv8.1 extensions to the enum

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Change-Id: I90c7eb2b22d317f5a60b020c731948681e9f91a1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51014
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2021-09-22 17:56:28 +01:00
parent 24dfe8a41c
commit e77ebef6b6
3 changed files with 30 additions and 2 deletions
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2
src/arch/arm/ArmISA.py
View File

@@ -47,7 +47,7 @@ class DecoderFlavor(Enum): vals = ['Generic']
class ArmDefaultSERelease(ArmRelease):
extensions = [
'CRYPTO', 'FEAT_SVE', 'FEAT_LSE', 'TME'
'CRYPTO', 'FEAT_SVE', 'FEAT_LSE', 'FEAT_RDM', 'TME'
]
class ArmISA(BaseISA):

6
src/arch/arm/ArmSystem.py
View File

@@ -49,6 +49,9 @@ class ArmExtension(ScopedEnum):
'FEAT_VHE',
'FEAT_PAN',
'FEAT_LSE',
'FEAT_HPDS',
'FEAT_VMID16',
'FEAT_RDM',
# Armv8.2
'FEAT_SVE',
@@ -97,7 +100,8 @@ class Armv8(ArmRelease):
class ArmDefaultRelease(Armv8):
extensions = Armv8.extensions + [
'FEAT_SVE', 'FEAT_LSE', 'FEAT_PAN', 'FEAT_SEL2'
'FEAT_SVE', 'FEAT_LSE', 'FEAT_PAN',
'FEAT_HPDS', 'FEAT_VMID16', 'FEAT_RDM', 'FEAT_SEL2'
]
class ArmSystem(System):

24
src/arch/arm/isa.cc
View File

@@ -355,9 +355,15 @@ ISA::initID32(const ArmISAParams &p)
miscRegs[MISCREG_ID_MMFR3] = p.id_mmfr3;
miscRegs[MISCREG_ID_MMFR4] = p.id_mmfr4;
/** MISCREG_ID_ISAR5 */
// Crypto
miscRegs[MISCREG_ID_ISAR5] = insertBits(
miscRegs[MISCREG_ID_ISAR5], 19, 4,
release->has(ArmExtension::CRYPTO) ? 0x1112 : 0x0);
// RDM
miscRegs[MISCREG_ID_ISAR5] = insertBits(
miscRegs[MISCREG_ID_ISAR5], 27, 24,
release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0);
}
void
@@ -421,6 +427,8 @@ ISA::initID64(const ArmISAParams &p)
miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
encodePhysAddrRange64(physAddrRange));
/** MISCREG_ID_AA64ISAR0_EL1 */
// Crypto
miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4,
@@ -429,14 +437,30 @@ ISA::initID64(const ArmISAParams &p)
miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20,
release->has(ArmExtension::FEAT_LSE) ? 0x2 : 0x0);
// RDM
miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64ISAR0_EL1], 31, 28,
release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0);
/** MISCREG_ID_AA64MMFR1_EL1 */
// VMID16
miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64MMFR1_EL1], 7, 4,
release->has(ArmExtension::FEAT_VMID16) ? 0x2 : 0x0);
// VHE
miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64MMFR1_EL1], 11, 8,
release->has(ArmExtension::FEAT_VHE) ? 0x1 : 0x0);
// HPDS
miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64MMFR1_EL1], 15, 12,
release->has(ArmExtension::FEAT_HPDS) ? 0x1 : 0x0);
// PAN
miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,
release->has(ArmExtension::FEAT_PAN) ? 0x1 : 0x0);
// TME
miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64ISAR0_EL1], 27, 24,