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arch-arm: Add missing Armv8.3 extensions to the enum

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Change-Id: Id3897c59a12189f4aac6a3923f656e1f6b8f6723
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51019
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2021-09-23 10:37:33 +01:00
parent a174513320
commit 8156bc0dc1
3 changed files with 43 additions and 1 deletions
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10
src/arch/arm/ArmISA.py
View File

@@ -47,7 +47,15 @@ class DecoderFlavor(Enum): vals = ['Generic']
class ArmDefaultSERelease(ArmRelease):
extensions = [
'CRYPTO', 'FEAT_SVE', 'FEAT_LSE', 'FEAT_RDM', 'TME'
'CRYPTO',
# Armv8.1
'FEAT_LSE', 'FEAT_RDM',
# Armv8.2
'FEAT_SVE',
# Armv8.3
'FEAT_FCMA', 'FEAT_JSCVT', 'FEAT_PAuth',
# Other
'TME'
]
class ArmISA(BaseISA):

7
src/arch/arm/ArmSystem.py
View File

@@ -59,6 +59,11 @@ class ArmExtension(ScopedEnum):
'FEAT_LVA', # Optional in Armv8.2
'FEAT_LPA', # Optional in Armv8.2
# Armv8.3
'FEAT_FCMA',
'FEAT_JSCVT',
'FEAT_PAuth',
# Armv8.4
'FEAT_SEL2',
@@ -107,6 +112,8 @@ class ArmDefaultRelease(Armv8):
'FEAT_LSE', 'FEAT_PAN', 'FEAT_HPDS', 'FEAT_VMID16', 'FEAT_RDM',
# Armv8.2
'FEAT_UAO', 'FEAT_LVA', 'FEAT_LPA', 'FEAT_SVE',
# Armv8.3
'FEAT_FCMA', 'FEAT_JSCVT', 'FEAT_PAuth',
# Armv8.4
'FEAT_SEL2'
]

27
src/arch/arm/isa.cc
View File

@@ -364,6 +364,15 @@ ISA::initID32(const ArmISAParams &p)
miscRegs[MISCREG_ID_ISAR5] = insertBits(
miscRegs[MISCREG_ID_ISAR5], 27, 24,
release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0);
// FCMA
miscRegs[MISCREG_ID_ISAR5] = insertBits(
miscRegs[MISCREG_ID_ISAR5], 31, 28,
release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0);
/** ID_ISAR6 */
miscRegs[MISCREG_ID_ISAR6] = insertBits(
miscRegs[MISCREG_ID_ISAR6], 3, 0,
release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0);
}
void
@@ -440,6 +449,24 @@ ISA::initID64(const ArmISAParams &p)
miscRegs[MISCREG_ID_AA64ISAR0_EL1], 31, 28,
release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0);
/** MISCREG_ID_AA64ISAR1_EL1 */
// PAuth, APA
miscRegs[MISCREG_ID_AA64ISAR1_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64ISAR1_EL1], 7, 4,
release->has(ArmExtension::FEAT_PAuth) ? 0x1 : 0x0);
// JSCVT
miscRegs[MISCREG_ID_AA64ISAR1_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64ISAR1_EL1], 15, 12,
release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0);
// FCMA
miscRegs[MISCREG_ID_AA64ISAR1_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64ISAR1_EL1], 19, 16,
release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0);
// PAuth, GPA
miscRegs[MISCREG_ID_AA64ISAR1_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64ISAR1_EL1], 27, 24,
release->has(ArmExtension::FEAT_PAuth) ? 0x1 : 0x0);
/** MISCREG_ID_AA64MMFR1_EL1 */
// VMID16
miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(