diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index e98041cc12..66133bfde7 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -47,7 +47,15 @@ class DecoderFlavor(Enum): vals = ['Generic']
 
 class ArmDefaultSERelease(ArmRelease):
     extensions = [
-        'CRYPTO', 'FEAT_SVE', 'FEAT_LSE', 'FEAT_RDM', 'TME'
+        'CRYPTO',
+        # Armv8.1
+        'FEAT_LSE', 'FEAT_RDM',
+        # Armv8.2
+        'FEAT_SVE',
+        # Armv8.3
+        'FEAT_FCMA', 'FEAT_JSCVT', 'FEAT_PAuth',
+        # Other
+        'TME'
     ]
 
 class ArmISA(BaseISA):
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 4dd42f37bc..c7be8c4168 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -59,6 +59,11 @@ class ArmExtension(ScopedEnum):
         'FEAT_LVA', # Optional in Armv8.2
         'FEAT_LPA', # Optional in Armv8.2
 
+        # Armv8.3
+        'FEAT_FCMA',
+        'FEAT_JSCVT',
+        'FEAT_PAuth',
+
         # Armv8.4
         'FEAT_SEL2',
 
@@ -107,6 +112,8 @@ class ArmDefaultRelease(Armv8):
         'FEAT_LSE', 'FEAT_PAN', 'FEAT_HPDS', 'FEAT_VMID16', 'FEAT_RDM',
         # Armv8.2
         'FEAT_UAO', 'FEAT_LVA', 'FEAT_LPA', 'FEAT_SVE',
+        # Armv8.3
+        'FEAT_FCMA', 'FEAT_JSCVT', 'FEAT_PAuth',
         # Armv8.4
         'FEAT_SEL2'
     ]
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 224b90a587..834dcca7ba 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -364,6 +364,15 @@ ISA::initID32(const ArmISAParams &p)
     miscRegs[MISCREG_ID_ISAR5] = insertBits(
         miscRegs[MISCREG_ID_ISAR5], 27, 24,
         release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0);
+    // FCMA
+    miscRegs[MISCREG_ID_ISAR5] = insertBits(
+        miscRegs[MISCREG_ID_ISAR5], 31, 28,
+        release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0);
+
+    /** ID_ISAR6 */
+    miscRegs[MISCREG_ID_ISAR6] = insertBits(
+        miscRegs[MISCREG_ID_ISAR6], 3, 0,
+        release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0);
 }
 
 void
@@ -440,6 +449,24 @@ ISA::initID64(const ArmISAParams &p)
         miscRegs[MISCREG_ID_AA64ISAR0_EL1], 31, 28,
         release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0);
 
+    /** MISCREG_ID_AA64ISAR1_EL1 */
+    // PAuth, APA
+    miscRegs[MISCREG_ID_AA64ISAR1_EL1] = insertBits(
+        miscRegs[MISCREG_ID_AA64ISAR1_EL1], 7, 4,
+        release->has(ArmExtension::FEAT_PAuth) ? 0x1 : 0x0);
+    // JSCVT
+    miscRegs[MISCREG_ID_AA64ISAR1_EL1] = insertBits(
+        miscRegs[MISCREG_ID_AA64ISAR1_EL1], 15, 12,
+        release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0);
+    // FCMA
+    miscRegs[MISCREG_ID_AA64ISAR1_EL1] = insertBits(
+        miscRegs[MISCREG_ID_AA64ISAR1_EL1], 19, 16,
+        release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0);
+    // PAuth, GPA
+    miscRegs[MISCREG_ID_AA64ISAR1_EL1] = insertBits(
+        miscRegs[MISCREG_ID_AA64ISAR1_EL1], 27, 24,
+        release->has(ArmExtension::FEAT_PAuth) ? 0x1 : 0x0);
+
     /** MISCREG_ID_AA64MMFR1_EL1 */
     // VMID16
     miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(