With this change, when using a DPRINTF statment on a class inheriting
from the Queue or QueueEntry class, the name at the start of the log
line will be meaningful.
Currently affected classes:
MSHRqueue
MSHR
MSHR::TargetList
WriteQueue
WriteQueueEntry
Change-Id: I4e5ac080fec572961f9f1d9f88429ed6e72d8994
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47040
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
Add serialization of the fd array when checkpointing in SE mode.
With this patch, host backed files are restored.
Further work needs to be done for restoring other types of
file descriptor.
As the file path saved is relative, on restoration of the checkpoint,
it may fail to open the file if the path is no longer valid.
If it cannot open the file, it will exit the simulation
with a meaningful error message.
Change-Id: I4d0c7cd614a8abaffcae9aba1a28c9fdbc023c5a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46619
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The current implementation of the less-than operator
for AddrRange compares intlvMatch values without first
checking that both ranges are interleaved.
This commit modifies the less-than operator to compare
intlvMatch values only if both regions are interleaved.
Otherwise, the operator returns whether the left
address range is interleaved.
This commit also adds AddrRangeMap unit tests
for interleaved address ranges.
JIRA: https://gem5.atlassian.net/browse/GEM5-1010
Change-Id: Id9f14d75d465d472c046995754bdccd441b9470c
Signed-off-by: Carlos Falquez <c.falquez@fz-juelich.de>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47279
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
The latest Power ISA introduces two new bits that record
carry and overflow out of bit 31 of the result, namely
CA32 and OV32 respectively, thereby changing the behaviour
of the add and subtract instructions that set them. Also,
now that 64-bit registers are being used, the nature of
the result, i.e. less than, greater than or equal to zero,
must be set by a 64-bit signed comparison of the result
to zero. This fixes the following instructions.
* Add Immediate (addi)
* Add Immediate Shifted (addis)
* Add (add[o][.])
* Subtract From (subf[o][.])
* Add Immediate Carrying (addic)
* Add Immediate Carrying and Record (addic.)
* Subtract From Immediate Carrying (subfic)
* Add Carrying (addc[o][.])
* Subtract From Carrying (subfc[o][.])
* Add Extended (adde[o][.])
* Subtract From Extended (subfe[o][.])
* Add to Zero Extended (addze[o][.])
* Subtract From Zero Extended (subfze[o][.])
* Negate (neg[o][.])
* Multiply Low Immediate (mulli)
* Multiply Low Word (mullw[o][.])
* Multiply High Word (mulhw[.])
* Multiply High Word Unsigned (mulhwu[.])
* Divide Word (divw[o][.])
* Divide Word Unsigned (divwu[o][.])
Change-Id: I8c79f1dca8b19010ed7b734d7ec9bb598df428c3
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40899
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This changes the base classes for integer arithmetic
instructions and introduces two new classes that are used
to distinguish between instructions using register and
immediate operands.
Decoding has also been consolidated using formats that can
generate code after determining if an instruction records
carry and overflow and also if it records the nature of the
result, i.e. lesser than, greater than or equal to zero.
However, for multiply and divide instructions, the code to
determine if an overflow has occurred has been moved to the
instruction definition itself. The formats have also been
updated to make use of the new base classes.
Change-Id: I23d70ac4bad4d25d876308db0b3564c092bf574c
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40898
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This introduces new formats for DS form instructions and
adds the following instructions.
* Load Doubleword (ld)
* Load Doubleword Indexed (ldx)
* Load Doubleword with Update (ldu)
* Load Doubleword with Update Indexed (ldux)
* Store Doubleword (std)
* Store Doubleword Indexed (stdx)
* Store Doubleword with Update (stdu)
* Store Doubleword with Update Indexed (stdux)
Change-Id: I2a88364e82a11685e081f57be5fd5afd44335668
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40895
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Reviewed-by: lkcl <luke.leighton@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Now that 64-bit registers and operands are being used, the
instructions for words must read or write just one word at
a time. This fixes the following instructions.
* Load Word and Zero (lwz)
* Load Word and Zero Indexed (lwzx)
* Load Word and Zero with Update (lwzu)
* Load Word and Zero with Update Indexed (lwzux)
* Load Word And Reserve Indexed (lwarx)
* Store Word (stw)
* Store Word Indexed (stwx)
* Store Word with Update (stwu)
* Store Word with Update Indexed (stwux)
* Store Word Conditional Indexed (stwcx.)
This also fixes decoding of load-store update instructions
for some special scenarios when RA is zero or RA and RT
are the same. In such cases, the instruction is considered
invalid.
Change-Id: I6787d3614ba8f1b1cbf30a49f85ef422324d7c21
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40893
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This reimplements the previously reverted change: Always generate default
create() methods.
The pybind code should only be generated when python is enabled. This
change passes whether python is enabled into the SimObject code creation
method. Then, the params code is optionally included.
Note: Due to some problems in GCC's linker (or something else...) we
need to have a single file with all of the generated code for the
SimObject.
Change-Id: I0f93b3d787d47f26db2de6c4447730f7df87a0dc
Issue-on: https://gem5.atlassian.net/browse/GEM5-1003
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46820
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Update in a pmp addr register can have effect on other
pmp rules, for example if TOR mode is used.
According to specs, update in a pmp entry is made using
an update to a pmpaddr reg, followed by an update to pmpcfg
reg which should be followed by sfence.vma. Currently,
in gem5 update in cfg register (combination of 8 pmpcfg
regs.), which should happen after a pmpaddr reg. update,
leads to an update in all pmp rules. However, there seems to
be a case where we receive an interrupt right before execution
of an instruction to update cfg register, which leads to unindented
side-effects of S mode addresses falsely falling into a wrong
pmp region. Updating pmp rules right after pmpaddr update, might
be redundant, but should not break anything otherwise.
Change-Id: I3776ee6ba40e1249c98d11076a2d176de40a957e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47059
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The first non-critical piece of this CL removes the unused self
from the Python function signature.
Then also includes "stl.h" from pybind11 to allow the
implicit conversion from std::map<std::string, std::string>
to a Python dict (otherwise there will be a runtime (not compile time)
error when calling the function.
As the current implementation always throws an error because of the
missing stl.h I don't believe anyone is using this function, and as such
it should be safe to just change the signature of
scx_get_parameter_list.
Change-Id: Ib3202b2d4d1b8418a4adf54739fe389d4ee07743
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45622
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45827
1. The logger behavior change breaks verify.py.
commit 8deb205ea1
Author: Daniel Carvalho <odanrc@yahoo.com.br>
Date: Wed Mar 3 16:49:05 2021 -0300
base: Add LOC to Loggers
Printing the line and the file that triggered a log
is useful for debugging.
Change-Id: I74e0637b2943049134bd3e9a4bc6cab3766591a9
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42141
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2. Use bytes diff in LogChecker.
In Python3, string is required to be in a certain encoding, while in Python2,
it is not. In the testcase, misc/cae_test/general/bitwise/or/datatypes,
it contains some invalid codepoint of utf-8, we need diff the log with
bytes in Pyhton3.
3. Python3 compatible.
* dict.iteritems -> dict.items
* remove object base class
* use `except as` when catching exceptions
* handle map and filter behavior change
Test with
src/systemc/tests/verify.py --update-json build/ARM -j `nproc` \
--filter-file src/systemc/tests/working.filt
src/systemc/tests/verify.py --update-json build/ARM -j `nproc` \
--filter-file src/systemc/tests/working.filt --phase verify --result-file
Change-Id: Ibf5b99d08a948387cf6162c476c294c49a7dac0f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44465
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45822
