tests: Re-enable the realview-o3-checker test

We are using the VExpress_GEM5_V1 platform for this test.
This is currently needed as the checker is GICv3 incompatible:

When validating MiscReg cpu interface register (MISCREG_ICC_*) updates
the underlying ISA storage is checked. However the content of some of
those registers is hardcoded in the GICv3 logic

JIRA: https://gem5.atlassian.net/browse/GEM5-364

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I8cfbba6d9869232fdb8475d17d15d15b61dfab87
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46626
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Giacomo Travaglini
2021-06-07 09:14:12 +01:00
parent 23366a2899
commit e7a941ee08
2 changed files with 4 additions and 6 deletions

View File

@@ -38,6 +38,7 @@ from arm_generic import *
from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
machine_type='VExpress_GEM5_V1',
mem_class=DDR3_1600_8x8,
cpu_class=O3_ARM_v7a_3,
checker=True).create_root()

View File

@@ -70,6 +70,7 @@ arm_fs_long_tests = [
'realview-switcheroo-o3',
'realview-switcheroo-full',
'realview64-o3',
'realview64-o3-checker',
'realview64-o3-dual',
'realview64-minor',
'realview64-minor-dual',
@@ -80,8 +81,8 @@ arm_fs_long_tests = [
'realview64-simple-timing-dual-ruby',
# The following tests fail. These are recorded in the GEM5-640 and GEM5-364
# Jira issues.
# The following tests fail. These are recorded in the GEM5-640
# Jira issue.
#
# https://gem5.atlassian.net/browse/GEM5-640
#'realview-simple-atomic-dual',
@@ -89,10 +90,6 @@ arm_fs_long_tests = [
#'realview-o3-dual',
#'realview-minor-dual',
#'realview-simple-timing-dual-ruby',
#
# https://gem5.atlassian.net/browse/GEM5-364
#'realview-o3-checker',
#'realview64-o3-checker',
]
tarball = 'aarch-system-20210904.tar.bz2'