Commit Graph

15240 Commits

Author SHA1 Message Date
Nils Asmussen
3bb461072c arch-riscv: make uret,sret,mret SerializeAfter,NonSpeculative.
These instructions potentially change the privilege level, upon which
the execution of other instructions depends. For that reason, we need to
make *ret SerializeAfter and we also don't want to execute them
speculatively.

Change-Id: If3b5ba6ec3b4102d53c51cf723eba5d5da3eaa2f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25656
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
d3f3a84cfb arch-riscv: make accesses to CSRs SerializeAfter.
According to page 57 in the RISC-V manual, CSR accesses "need to be
performed in program order with respect to those instructions whose
execution behavior is affected by the state of the accessed CSR".

Thus, we need to make them SerializeAfter to ensure that the following
instructions are executed with the potential changes to the CSR. In
theory, we could be smarter here by only considering write accesses to
CSRs and considering the following instructions, but for now we simply
serialize for every CSR access.

Change-Id: I69391fccaec31c34d944c55bac2f04d37947ebfe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25655
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
33d651b254 arch-riscv: fault according to status.{TVM,TSK,TW}.
Change-Id: I38dddadb3373d2156b8fc57eabff861a062021cf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25654
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
c11aed1931 arch-riscv: added dummy implementation of wfi instruction.
Change-Id: I7ca86f57c7d794bf544e34e747875049a3f29d6a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25653
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
55e7d3e5b6 arch-riscv: fault on mstatus accesses from lower privilege modes.
Change-Id: If2e35445770eaa52f5af6f9ef02fb5e11bef8da4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25652
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
aaf294af5c arch-riscv: ignore writes to SXL/UXL fields in status register.
We currently only support SXL=UXL=2 (64 bit). These fields are WARL,
so that we have to make sure that no other value can be set.

Change-Id: I62ddc7d68b8c31ca655ba1ccee7a294912f46b09
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25651
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
54d769308d arch-riscv: added (un)serialization of miscRegFile.
Change-Id: I127dbf4a6bb4a144eaee05a87495830dce82eb58
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25650
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
6d3bf34a2a arch-riscv: show names of MiscRegs on accesses.
Printing the number of the MiscRegs makes it hard to debug problems.
Therefore, this commit adds a name table and prints the name of the
register.

Change-Id: Icd53d5524a5d5daf3e50f253cdda56341663f26e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25649
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
b295e0f3a8 arch-riscv: fixed read of {M,S,U}TVEC.
As stated in 4.1.4 of the privileged ISA manual, the BASE field in the
STVEC register contains the bits [SXLEN-1:2] of the base address, not
the base address shifted left by 2.

Change-Id: I799ec0dc1cbd7b271b91b53adb033a5d1ca3306f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25648
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
4056876301 configs: added bare metal FS support for RISC-V.
Change-Id: Id412186d868680b9af97503a5337fc394fd84f68
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26989
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
2403018690 cpu,configs: let RISC-V use the PT walker cache.
Change-Id: I19b1dd9e3c55c433c897988d36e6715017273c66
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26988
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
a4bd492158 arch-riscv: fixed formatting.
Change-Id: I134993a4aced07e75bf62fec56081b0f9d8fc18c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26986
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
7d0c6eae62 arch-riscv: implement RemoteGDB::acc for FS mode.
Change-Id: I78b37db43fbb16d4dafa74294117e8beba62f903
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26985
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
fa6de5d5fd arch-riscv: implement sfence.vma to flush TLBs.
Change-Id: I424123d3c94c9673269f922cd6755f0bbf5b6cc0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26984
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
476d96cb53 arch-riscv: make sure only supported modes can be set in SATP.
Change-Id: I37c67e491d64bf03d1125e23db28611fa0b16038
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26983
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-04-29 11:41:55 +00:00
Nils Asmussen
2527c6c9da arch-riscv: added TLB and page table walker.
That is, RISC-V has now a TLB and page table walker for Sv39 paging
according to the privileged ISA 1.11.

Both the TLB and PT walker are based on x86 (the code duplication of the
page table walkers will be reduced by a separate commit).

Change-Id: I5e29683bdd40c0d32c06e4d75a8382bf313f2086
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25647
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-29 11:41:55 +00:00
Gabe Black
f8926cd56f arm: Add a unit test for some aspects of the aapcs64 ABI.
This test covers the templates which attempt to classify types, but not the
actual gathering of arguments of distribution of return values. As before, we
can't really use standard C++ to accurately test for HFAs and HVAs, so we stick
with approximating them by detecting arrays of the right types.

For example, I think technically we should also accept a struct with only 4
float members, but c++ templates aren't able to match against types in that way
as far as I know.

Change-Id: I1d7756a964a86c0c5ea13e068a5fc74603e14e30
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28268
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-29 11:30:58 +00:00
Gabe Black
0c7f131ed2 arm: Fix some bugs in the aapcs64 implementation.
The templates which checked for short vectors, and our approximation of
HFA, HVA and HXA types were not correct. This change actually simplifies
them along with getting them to produce correct results. In the case of
HXA, there was a logic bug where an && was used where an || was
intended.

There may still be bugs in the actual collection of arguments and
setting of return values since those aspects are harder to test.

Change-Id: Ice3177205a98c678ecb43ba600813b3909c44e6b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28267
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-28 21:54:04 +00:00
Matthew Poremba
fa5bf60c78 configs: Add missing requestToMemory MessageBuffers
In commit 53b6e21 two protocol config files were missed when the new
requestToMemory MessageBuffers were added. This fixes the issue such
that all Ruby protocols are working again.

Change-Id: Iaa04c792eaf6d659ba13c19f003e7e31b71ffdb4
JIRA: https://gem5.atlassian.net/browse/GEM5-468
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28187
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-28 14:41:28 +00:00
Jordi Vaquero
3afcfe3b53 arch-arm: Fix clasta/b and lasta/b simd&fp instructions
The simd&fp version of this instructions required zeroing the result
vector except for the first element, that contains the result.

Change-Id: I231ad3c44d89f34acae26d299ab676e2ed09acdc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28247
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-28 12:56:29 +00:00
Giacomo Travaglini
eabd4f3a9b configs: Do not require args.kernel to be set in baremetal.py
This is allowing to us run baremetal.py with the --dtb-gen option
without needing to specify a --kernel argument

Change-Id: I98f1bc865d2f4e2230b1a85453efe83d95ec8a55
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28148
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-28 09:51:36 +00:00
Giacomo Travaglini
a0038f7aec sim, arch-arm: Restore capability of running without a kernel
The following patch:

https://gem5-review.googlesource.com/c/public/gem5/+/24283

Removed the capability of starting a gem5 simulation without
a kernel object. This patch is restoring it

Change-Id: I6d751bac386cbb250b3593bb12463140dc964ab3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28147
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-28 09:51:36 +00:00
Gabe Black
26454e8072 util: Add an abstraction layer for call types in the m5 utility.
These make the calling code in m5.c a little bit more generic. Each call
type will have a function to check the arguments and see if that type is
being requested and/or has any additional options set in the arguments.
If so, those are processed, and argc and argv are adjusted.

Then another function returns the appropriate dispatch table to use for
that invocation scheme. This is behind a function instead of, for
instance, a global variable because it gives the call type a little bit
more control over what's happening, for instance if it would use
different implementations in slightly different circumstances.

Change-Id: I661cf202ec657466496767cbdf331fe27995ab26
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27241
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-04-28 01:07:43 +00:00
Gabe Black
1708a71e5b util: Add a helpful macro for merging two tokens to m5ops.h.
I've needed this type of macro often when writing code which uses the
M5OP_FOREACH macro, and so rather than re-write it each time, lets just
put a version here. This is such a common type of macro to need that
you'd think it would be part of a standard header somewhere, but to my
knowledge it isn't.

Change-Id: I0df0d9d2fd7ce1b9e6c355d6e4db197ccfff7c35
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27239
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-04-28 01:07:43 +00:00
Gabe Black
6072c1ad28 util: Use a dispatch table to call ops in the m5 utility.
This way different implementations can be substituted in depending on
how the low level ops should actually be triggered (inst, addr,
semihosting, (etc?)).

Change-Id: I7c6eab7d87cc973d0bc9c1889037a0f89ce057e8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27238
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-04-28 01:07:43 +00:00
Gabe Black
3e88a4aa01 misc,util: Remove explicit ';'s from M5OP_FOREACH.
It may be the case that each item M5OP_FOREACH iterates over should end
in a ',' and not a ';', for instance when putting each item into an
array or initializing a structure. If the caller still wants a ';', they
can add it into the definition of the M5OP macro.

Change-Id: Idd6538b0aad27df39658c3f749c6ff5e4fe55e6d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27237
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-28 01:07:43 +00:00
Gabe Black
3b6f2fc14f misc: Add the SE mode m5 ops to m5ops.h.
These shouldn't be called in fs mode through the m5 utility and
probably shouldn't be called directly either, but this makes them
consistent with the other functions which are mentioned in
asm/generic/m5ops.h.

Change-Id: I80df8b4d507350bc6d2763e770e38e0370931632
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27236
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-28 01:07:43 +00:00
Gabe Black
ac858434c6 sim,misc: Rename M5OP_ANNOTATE to M5OP_RESERVED1.
The M5OP_ANNOTATE constant is unused and treated as a reserved op in
gem5. Rename it to make it official and consistent.

Change-Id: Id5fe6a3aa402a2e0cd187503abff9b09e81b3724
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27235
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-04-28 01:07:43 +00:00
Gabe Black
e81e48c16b misc: Tidy up M5OP_FOREACH and the constants in m5ops.h.
Make sure all the operations that have constants (and aren't deprecated
or reserved) and present in M5OP_FOREACH in order of their constants.
Also move M5OP_ANNOTATE up so that all the constants are also in order.

Change-Id: I8d9f69b020aeb39311a24606a286a76de10a51cc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27234
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-28 01:07:43 +00:00
Gabe Black
4af8df1ecd util: Delete the execfile m5 utility command.
This command was just a thin wrapper around the readfile command, and
can be easily duplicated by piping the output of that command to
/tmp/execfile and then running it.

Change-Id: Ib77166ee9f07571d57e4d21e9615def55e5391a8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27233
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-04-28 01:07:43 +00:00
Gabe Black
5e888d44fe util: Eliminate the sw99param m5 utility command.
This is a small additional layer on top of the initparam command and
just breaks the returned value into 12 bit chunks. It presumes that
there is some particular meaning to the default initparam value which
may or may not be true. It's not entirely clear what the 12 bit chunks
that this command returns are actually good for, and it's been around
long enough that there isn't really any good documentation about what
it's intended purpose was.

Change-Id: I21af0e0cf7501f47026a6dd31920d46cfccff167
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27232
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-04-28 01:07:43 +00:00
Gabe Black
21eba2a6fa util: Improve the usage text of the m5 utility.
Make sure there *is* help text for every command, alphabetize the
commands, explain all the arguments and what the command as a whole
does.

Change-Id: Icf74f8c638545c8658c99169dce728f7b1127806
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27231
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-04-28 01:07:43 +00:00
Gabe Black
10ae66c590 util: Further simplify the initParam implementation.
Take advantage of string comparisons when looking up what to do with a
given key.

Convert the key_str[12] registers from little endian to host endian.
This matches a corresponding change in the m5 utility to pack the
registers in little endian order, regardless of what the actual guest
endianness is.

Absorb the initparam_keys.hh header into sim/pseudo_inst.cc, and convert
its constants to c++ strings. The constants defined in it might be
useful to guest code calling into the m5 ops, but not for gem5 itself.
By merging them into the .cc file, we also don't have to do any tricks to
try to avoid them having multiple definitions.

Change-Id: I3a450ad7f9c4dca25f79c7835d7f9c167c02ae98
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27230
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-04-28 01:07:43 +00:00
Gabe Black
fe63b9c303 misc: Replace a deprecated method in protoio.cc.
A warning says that ByteSize is now deprecated, and should be replaced
with ByteSizeLong. This change does that.

Change-Id: I0b1aef733c509a73a0af9c39b359d39579d1fd37
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28185
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-27 21:46:28 +00:00
Gabe Black
90879d4920 util: Refactor the string->register packing function in the m5 utility.
This change removes the responsibility for checking the number of
arguments and handing the default of no string back into init_param and
out of the function which packs strings into registers. It also renames
the function to more closely match its purpose, and rewrites it to be a
bit simpler and (IMHO) easier to follow.

Importantly, rather than doing a hand implemented strcpy which would
follow the endianness of the target/simulated platform, this change
makes this function pack the registers explicitly in little endian byte
order. This way on the consuming end in gem5, the initParam function
doesn't have to care what the guest endianness is, it can just translate
them from little endian to whatever the host endianness is (very likely
also little endian).

Change-Id: Ie9f79ecb8d4584c6e47a2793a31ccaa8c7c15986
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27229
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-27 21:03:28 +00:00
Gabe Black
fc7ada3e7c sim: Simplify collecting the key value in initParam.
If the first register is all zeroes, it doesn't really matter what the
other register is. If the first register has the entire string, we still
don't care what the other register has in it. There's no reason to
complicate the code with these extra checks.

Change-Id: I22ad521b9ace915ccb75f15934fc6b3d650d5293
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27228
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
2020-04-27 21:03:28 +00:00
Gabe Black
c12a72e073 util: Correct some help text for the initparam m5 utility command.
The "key" value passed to the initparam command can be at most 16
characters long, but the text said it had to be shorter than 16
characters.

Change-Id: Ic98dc87feb868b44c4210ae16cb5b0dad2a67d88
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27227
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-27 21:03:28 +00:00
Gabe Black
f64c8ce5bb util: Remove the "pin" command from the m5 utility.
This command did not use any m5 ops, does the same thing as the
"taskset" command under Linux:

https://linux.die.net/man/1/taskset

and might even have introduced a build error if compiled for any other
OS since that would have left a trailing comma in the mainfuncs array.

While the last problem would be easy to correct, this is not related to
the purpose of this utility (giving access to m5 ops), and is redundant
with an existing standard utility provided with Linux.

Change-Id: Ie72b9310f5e6264f6035013f47ebe74a27464abb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27226
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-27 21:03:28 +00:00
Gabe Black
8fd4d147b6 util: Add missing functions to the java wrapper for m5 ops.
Change-Id: I9bdef3cb78cc01b0743ea38eec6f6d28cd2f6765
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27225
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-27 21:03:28 +00:00
Gabe Black
ae3dc85cc3 misc: Use a const char * in the m5op m5_add_symbol.
The symbol name is not modified by the m5 op, so a const char * is more
accurate and gives the caller more flexibility as far as what they can
pass in.

Change-Id: Iee567bceef501643175dd5c65551a4c8554a6e3b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27224
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
2020-04-27 21:03:28 +00:00
Gabe Black
55c75d799f util: Update the java wrapper names for m5 ops.
These were regularized a while ago, but not updated in the java wrapper.
There are also missing ops, but these will be added in another change.

Change-Id: Iaef281249c26d446709ba2b214ee37d574f6b72c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27223
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
2020-04-27 21:03:28 +00:00
Gabe Black
8b2e1f00c7 misc: Get rid of constants used for critical path annotation.
The constant for the critical path annotation function itself is still
used in gem5 along with the M5OP_RESERVED opcodes to signal
unimplemented functions.

Change-Id: I71c7a56d0346f8aafe23e733a1eea703dda1af92
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27222
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-27 21:03:28 +00:00
Gabe Black
744eecd9e0 misc: Get rid of the m5op_flags.h header.
This held flags for use with the critical path annotation instructions
which are no longer accessible through the m5 utility and so not used.

Change-Id: Ifee85ce78bb33c4a3e8c0db845974f17d8867199
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27221
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-27 21:03:28 +00:00
Gabe Black
9de7264e12 misc: Remove m5a_ (critical path annotation) prototypes from m5ops.h.
This mechanism is still available within gem5 as far as I can tell, but
it's not accessible through the pseudo instruction interface.

Change-Id: I69bd3c92239721a6d1049cee66eb7a0c1bdbc272
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27220
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-27 21:03:28 +00:00
Gabe Black
d0d29805f6 util: Convert the other architecture's m5 utility builds to scons.
Because I don't have a canonical toolchain to set SPARC's defaults to,
it will by default build for Linux instead of Solaris like it used to.
This will make it hard to test, but without a compiler there's not much
I can do.

This also coincidentally brings the SPARC version more in line with the
other variants which all target Linux.

Change-Id: Ie19217e988782da124306160920f40ef168840e4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27219
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2020-04-27 21:03:28 +00:00
Jordi Vaquero
9bcfb78ec4 arch-arm: Fix Sve Fcmla indexed instruction
Sve implementation of FCMLA indexed instruction was
incorrectly typed. This instruction is design to be used for
half-precision and single precision.

Change-Id: Ie529e21140ce5b26a8e72ac869a5422d32eba864
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28227
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-27 13:36:15 +00:00
Giacomo Travaglini
5b23b6ea01 arch-arm: SVE instructions do not use AHP format
SVE half-precision floating-point instructions support only IEEE
754-2008 half-precision format and ignore the value of the FPCR.AHP bit,
behaving as if it has an Effective value of 0.

This patch is addressing this by masking the FPSCR.AHB bit before
passing it to fplib.

Change-Id: I1432fc3f7fefb81445fe042ae7d681f5cec40e64
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28108
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-27 13:10:45 +00:00
Giacomo Travaglini
b089163b72 arch-arm: Do not increment exponent if FPSCR.FZ in fplib
If flushing to zero, the exponent shouldn't be incremented since
we are supposed to produce a 0 value and not a denormal number

Change-Id: Ib6dd594a6555b2fd9a20a52b59cbf1f5f94c2eb5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28107
Reviewed-by: Jordi Vaquero <jordi.vaquero@metempsy.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-27 13:10:45 +00:00
Gabe Black
da21567d2c util: Add some additional flags for files in the m5 util.
When compiling static objects, disable pie with the -no-pie linker flag.
This is necessary for x86, and doesn't seem to hurt anything for the
other variants.

When compiling shared objects, particularly the assembly files which
can't rely on the compiler to generate position independent code, define
M5OP_PIC so that the assembly code can configure itself correctly.

Change-Id: I80d1ea7a7704666027e74228036af5e0e4b9eac2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27218
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-26 11:15:16 +00:00
Bobby R. Bruce
93933b4465 misc,tests: Updated and generalized the resource url for tests
As we are now going to maintain different bundles of resources for each
gem5 release, the resources have been archived to
http://dist.gem5.org/dist/current for gem5 19. The development branch
will use http://dist.gem5.org/dist/develop going forward. New releases
will follow the format http://dist.gem5.org/dist/{VERSION}.

This patch makes the resources url a command-line parameter, set to the
"correct" url by default. This will be updated to the correct, archived,
version subdirectory upon release of a new gem5 version. E.g.:
http://dist.gem5.org/dist/v20 for the gem5 20 release.

Some Make files have been cleaned up to no longer fetch and push to
remote locations. As gem5-resources is implemented, sources will be
moved to the gem5-resources resository and compiled binaries, etc.
pulled from our Google Cloud bucket from the tests themselves.

Change-Id: Ia16c496be3a60283ecc431ffaa5b059e1932b526
Issue-on: https://gem5.atlassian.net/browse/GEM5-431
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27987
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-25 20:41:58 +00:00