derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch-riscv: fault on mstatus accesses from lower privilege modes.

Browse Source 
Change-Id: If2e35445770eaa52f5af6f9ef02fb5e11bef8da4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25652
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Nils Asmussen
2020-02-14 11:45:29 +01:00
parent aaf294af5c
commit 55e7d3e5b6
1 changed files with 13 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
src/arch/riscv/isa/formats/standard.isa
View File

@@ -2,6 +2,7 @@
// Copyright (c) 2015 RISC-V Foundation
// Copyright (c) 2016-2017 The University of Virginia
// Copyright (c) 2020 Barkhausen Institut
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@@ -306,6 +307,18 @@ def template CSRExecute {{
olddata = xc->readMiscReg(MISCREG_FFLAGS) |
(xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
break;
case CSR_MSTATUS: {
auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
if (pm != PrivilegeMode::PRV_M) {
std::string error = csprintf(
"MSTATUS is only accessibly in machine mode\n");
fault = make_shared<IllegalInstFault>(error, machInst);
olddata = 0;
} else {
olddata = xc->readMiscReg(CSRData.at(csr).physIndex);
}
break;
}
default:
if (CSRData.find(csr) != CSRData.end()) {
olddata = xc->readMiscReg(CSRData.at(csr).physIndex);