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arch-riscv: ignore writes to SXL/UXL fields in status register.

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We currently only support SXL=UXL=2 (64 bit). These fields are WARL,
so that we have to make sure that no other value can be set.

Change-Id: I62ddc7d68b8c31ca655ba1ccee7a294912f46b09
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25651
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Nils Asmussen
2020-02-24 13:47:43 +01:00
parent 54d769308d
commit aaf294af5c
1 changed files with 9 additions and 0 deletions
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9
src/arch/riscv/isa.cc
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@@ -347,6 +347,15 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
setMiscRegNoEffect(misc_reg, new_val);
}
break;
case MISCREG_STATUS:
{
// SXL and UXL are hard-wired to 64 bit
auto cur = readMiscRegNoEffect(misc_reg);
val &= ~(STATUS_SXL_MASK | STATUS_UXL_MASK);
val |= cur & (STATUS_SXL_MASK | STATUS_UXL_MASK);
setMiscRegNoEffect(misc_reg, val);
}
break;
default:
setMiscRegNoEffect(misc_reg, val);
}