diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 754ff85b75..a2fbd80437 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -347,6 +347,15 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
                 setMiscRegNoEffect(misc_reg, new_val);
             }
             break;
+          case MISCREG_STATUS:
+            {
+                // SXL and UXL are hard-wired to 64 bit
+                auto cur = readMiscRegNoEffect(misc_reg);
+                val &= ~(STATUS_SXL_MASK | STATUS_UXL_MASK);
+                val |= cur & (STATUS_SXL_MASK | STATUS_UXL_MASK);
+                setMiscRegNoEffect(misc_reg, val);
+            }
+            break;
           default:
             setMiscRegNoEffect(misc_reg, val);
         }