arch-arm: Fix Sve Fcmla indexed instruction
Sve implementation of FCMLA indexed instruction was incorrectly typed. This instruction is design to be used for half-precision and single precision. Change-Id: Ie529e21140ce5b26a8e72ac869a5422d32eba864 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28227 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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@@ -2799,12 +2799,12 @@ namespace Aarch64
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case 2:
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zm = (IntRegIndex) (uint8_t) bits(machInst, 18, 16);
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imm = bits(machInst, 20, 19);
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return new SveFcmlai<uint32_t>(machInst,
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return new SveFcmlai<uint16_t>(machInst,
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zda, zn, zm, rot, imm);
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case 3:
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zm = (IntRegIndex) (uint8_t) bits(machInst, 19, 16);
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imm = bits(machInst, 20);
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return new SveFcmlai<uint64_t>(machInst,
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return new SveFcmlai<uint32_t>(machInst,
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zda, zn, zm, rot, imm);
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}
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return new Unknown64(machInst);
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@@ -3558,7 +3558,7 @@ let {{
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sveCmpInst('fcmuo', 'Fcmuo', 'SimdFloatCmpOp', fpTypes, fcmuoCode)
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# FCMLA (indexed)
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sveComplexMulAddInst('fcmla', 'Fcmlai', 'SimdFloatMultAccOp',
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fpTypes[1:], predType = PredType.NONE)
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fpTypes[:2], predType = PredType.NONE)
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# FCMLA (vectors)
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sveComplexMulAddInst('fcmla', 'Fcmlav', 'SimdFloatMultAccOp',
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fpTypes, predType = PredType.MERGE)
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