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arch-arm: SVE instructions do not use AHP format

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SVE half-precision floating-point instructions support only IEEE
754-2008 half-precision format and ignore the value of the FPCR.AHP bit,
behaving as if it has an Effective value of 0.

This patch is addressing this by masking the FPSCR.AHB bit before
passing it to fplib.

Change-Id: I1432fc3f7fefb81445fe042ae7d681f5cec40e64
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28108
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2020-04-22 17:24:26 +01:00
parent b089163b72
commit 5b23b6ea01
2 changed files with 11 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
src/arch/arm/isa/insts/sve.isa
View File

@@ -2949,7 +2949,7 @@ let {{
if (sub_i) {
elt2_i = fplibNeg<Element>(elt2_i);
}
fpscr = (FPSCR) FpscrExc;
fpscr = FpscrExc & ~FpscrAhpMask;
acc_r = fplibAdd<Element>(acc_r, elt2_i, fpscr);
FpscrExc = fpscr;
}
@@ -2957,7 +2957,7 @@ let {{
if (sub_r) {
elt2_r = fplibNeg<Element>(elt2_r);
}
fpscr = (FPSCR) FpscrExc;
fpscr = FpscrExc & ~FpscrAhpMask;
acc_i = fplibAdd<Element>(acc_i, elt2_r, fpscr);
FpscrExc = fpscr;
}
@@ -3015,7 +3015,7 @@ let {{
if (neg_r) {
elt2_a = fplibNeg<Element>(elt2_a);
}
fpscr = (FPSCR) FpscrExc;
fpscr = FpscrExc & ~FpscrAhpMask;
addend_r = fplibMulAdd<Element>(addend_r, elt1_a, elt2_a, fpscr);
FpscrExc = fpscr;'''
if predType != PredType.NONE:
@@ -3028,7 +3028,7 @@ let {{
if (neg_i) {
elt2_b = fplibNeg<Element>(elt2_b);
}
fpscr = (FPSCR) FpscrExc;
fpscr = FpscrExc & ~FpscrAhpMask;
addend_i = fplibMulAdd<Element>(addend_i, elt1_a, elt2_b, fpscr);
FpscrExc = fpscr;'''
if predType != PredType.NONE:
@@ -3466,7 +3466,7 @@ let {{
sveExtInst('ext', 'Ext', 'SimdAluOp')
# FABD
fpOp = '''
FPSCR fpscr = (FPSCR) FpscrExc;
FPSCR fpscr = FpscrExc & ~FpscrAhpMask;
destElem = %s;
FpscrExc = fpscr;
'''
@@ -3497,7 +3497,7 @@ let {{
sveBinInst('fadd', 'FaddUnpred', 'SimdFloatAddOp', floatTypes, faddCode)
# FADDA
fpAddaOp = '''
FPSCR fpscr = (FPSCR) FpscrExc;
FPSCR fpscr = FpscrExc & ~FpscrAhpMask;
destElem = fplibAdd<Element>(destElem, srcElem1, fpscr);
FpscrExc = FpscrExc | fpscr;
'''
@@ -3505,7 +3505,7 @@ let {{
fpAddaOp)
# FADDV
fpReduceOp = '''
FPSCR fpscr = (FPSCR) FpscrExc;
FPSCR fpscr = FpscrExc & ~FpscrAhpMask;
destElem = fplib%s<Element>(srcElem1, srcElem2, fpscr);
FpscrExc = FpscrExc | fpscr;
'''

6
src/arch/arm/miscregs.hh
View File

@@ -1936,10 +1936,12 @@ namespace ArmISA
// This mask selects bits of the FPSCR that actually go in the FpCondCodes
// integer register to allow renaming.
static const uint32_t FpCondCodesMask = 0xF0000000;
// This mask selects the cumulative FP exception flags of the FPSCR.
static const uint32_t FpscrExcMask = 0x0000009F;
// This mask selects the cumulative saturation flag of the FPSCR.
static const uint32_t FpscrQcMask = 0x08000000;
// This mask selects the AHP bit of the FPSCR.
static const uint32_t FpscrAhpMask = 0x04000000;
// This mask selects the cumulative FP exception flags of the FPSCR.
static const uint32_t FpscrExcMask = 0x0000009F;
/**
* Check for permission to read coprocessor registers.