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cpu,configs: let RISC-V use the PT walker cache.

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Change-Id: I19b1dd9e3c55c433c897988d36e6715017273c66
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26988
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Nils Asmussen
2020-03-21 11:01:31 +01:00
parent a4bd492158
commit 2403018690
3 changed files with 8 additions and 5 deletions
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5
configs/common/CacheConfig.py
View File

@@ -1,4 +1,5 @@
# Copyright (c) 2012-2013, 2015-2016 ARM Limited
# Copyright (c) 2020 Barkhausen Institut
# All rights reserved
#
# The license below extends only to copyright in the software and shall
@@ -79,7 +80,7 @@ def config_cache(options, system):
dcache_class, icache_class, l2_cache_class, walk_cache_class = \
L1_DCache, L1_ICache, L2Cache, None
if buildEnv['TARGET_ISA'] == 'x86':
if buildEnv['TARGET_ISA'] in ['x86', 'riscv']:
walk_cache_class = PageTableWalkerCache
# Set the cache line size of the system
@@ -181,7 +182,7 @@ def config_cache(options, system):
# on these names. For simplicity, we would advise configuring
# it to use this naming scheme; if this isn't possible, change
# the names below.
if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']:
system.cpu[i].addPrivateSplitL1Caches(
ExternalCache("cpu%d.icache" % i),
ExternalCache("cpu%d.dcache" % i),

3
configs/common/Caches.py
View File

@@ -1,4 +1,5 @@
# Copyright (c) 2012 ARM Limited
# Copyright (c) 2020 Barkhausen Institut
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -92,7 +93,7 @@ class PageTableWalkerCache(Cache):
tgts_per_mshr = 12
# the x86 table walker actually writes to the table-walker cache
if buildEnv['TARGET_ISA'] == 'x86':
if buildEnv['TARGET_ISA'] in ['x86', 'riscv']:
is_read_only = False
else:
is_read_only = True

5
src/cpu/BaseCPU.py
View File

@@ -1,4 +1,5 @@
# Copyright (c) 2012-2013, 2015-2017 ARM Limited
# Copyright (c) 2020 Barkhausen Institut
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -181,7 +182,7 @@ class BaseCPU(ClockedObject):
dcache_port = MasterPort("Data Port")
_cached_ports = ['icache_port', 'dcache_port']
if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']:
_cached_ports += ["itb.walker.port", "dtb.walker.port"]
_uncached_slave_ports = []
@@ -216,7 +217,7 @@ class BaseCPU(ClockedObject):
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']:
if iwc and dwc:
self.itb_walker_cache = iwc
self.dtb_walker_cache = dwc