The PCI host has an interrupt-map property which only works for a fixed
setup of parent/child interrupt/address cells, which currently overlaps
with GICv2.
We want to make this flexible, so that the interrupt-map doesn't break
if we change the interrupt/address-cells value, and the patch is aiming
in that direction. This is also needed for GICv3 DTB autogeneration,
since it is using different values than GICv2.
Change-Id: If1c661ddcbc0c277c9d6b0e44a0fd3fe2427618c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20052
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The X86 local APIC doesn't actually use the pio_addr set in the config
and instead computes what address it will respond to based on the
initial ID of the CPU it's attached to. gem5's BasicPioDevice, which
the X86LocalApic class inherits from, does not provide a default value
for that parameter and will complain if *something* isn't set. The
value used, 0x2000000000000000, is a dummy value which is the base of
the region of the physical address space set aside for messages to
local APICs from the CPU and from other local APICs.
Also, the clock for the local APIC's timer is defined to be the bus
clock. The assumption seems to be that this has a 16:1 ratio with the
CPU clock, and I vaguely remember finding that that was more or less
unofficially true, even if it isn't necessary stringently defined to
be that.
Since we were already just assuming that that ratio was correct and
always setting up the local APICs clock that way, we can do that in
the X86LocalApic class definition and remove some special x86 specific
setup that we'd otherwise need for the x86 version of the Interrupt
class. If that's not correct, it can still be overridden somewhere else
in the config.
Change-Id: I50e84f899f44b1191c2ad79d05803b44f07001f9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19968
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gem5Fixture is used to define a fixture for building the gem5
binary. Most tests are expected to define their own Gem5Fixture,
however, as some might depend on the same binary (e.g.,
./build/ARM/gem5.opt), they will try to re-define a fixture for the
same target. This patchset changes Gem5Fixture to derive from
UniqueFixture.
In addition, this patchset changes the way global fixtures are
discovered to work with the new Gem5Fixture class. Instead of
enumerating them when test definitions are loaded, we do so after the
tests have been filtered according to specified tags (e.g., include
opt variant, exclude fast, debug variants).
Change-Id: Ie868a7e18ef6c3271f3c8a658229657cd43997cb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19251
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
This changeset adds a test to check the redirection features
added in faux-filesystem changeset. The test contains a
"chdir" system call to "/proc" which should be redirected to
"$(gem5-dir)/m5out/fs/proc" (as specified by the config files).
After "chdir", the test subsequently outputs the "/proc/cpuinfo"
file which should output a configuration of a fake cpu with
values set by a Python configuration file.
Note, the test will call "clone" once. To avoid a runtime error,
make sure that you run this test with "-n2" supplied to the
"config/example/se.py" script.
Change-Id: I505b046b7a4feddfa93a6ef0f0773ac43078cc94
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17112
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Fix problem with O3 and AMO instructions. At initial stages amo
instruction is considered a type of non-speculative store. After
the instruction has been commited and during the squash step,
acquire_release version of the AMO operation is considered speculative,
that differents results in an assert fault. This fix ensures that AMO
instructions are always considered non-speculative, during early stages
and during squas/removal of the instruction.
Change-Id: Ia0c5fbb9dc44a9991337b57eb759b1ed08e4149e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19815
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
In the current SMMUv3 model, multiple micro/mainTLB are present at the
device interface (SMMUv3SlaveInterface), caching translations specific
to a device.
Those distributed TLBs are checked for a translation before checking for
centralized TLBs (shared by devices), like the configuration cache, walk
cache etc. This means that if a hit in these TLBs occurs, there won't
be a need to enter configuration stage (which is where the STE and CD
are retrieved). So if we invalidate a cached configuration (in
ConfigCache), we need to invalidate those interface TLB entries as well,
otherwise in theory we will keep the same translation even after a
change in configuration tables.
Change-Id: I4aa36ba8392a530267517bef7562318b282bee25
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Michiel van Tol <michiel.vantol@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19813
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
ARMv8.1-PAN adds a new bit to PSTATE. When the value of this PAN state
bit is 1, any privileged data access from EL1 or EL2 to a virtual memory
address that is accessible at EL0 generates a Permission fault.
This feature is mandatory in ARMv8.1 implementations.
This feature is supported in AArch64 and AArch32 states.
The ID_AA64MMFR1_EL1.PAN, ID_MMFR3_EL1.PAN, and ID_MMFR3.PAN fields
identify the support for ARMv8.1-PAN.
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I94a76311711739dd2394c72944d88ba9321fd159
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19729
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
MSR <pstatefield>, #imm is used for setting a PSTATE field using an
immediate. Current implementation has the following flaws:
* There is no base MSR immediate definition: all the existing
PSTATE fields have a different class definition
* Those implementation make use of a generic data64 base class
which results in a wrong disassembly (pstate register is printed as an
integer register).
This patch is fixing this by defining a new base class (MiscRegImmOp64)
and new related templates. In this way, we aim to ease addition of new
PSTATE fields (in ARMv8.x)
Change-Id: I71b630ff32abe1b105bbb3ab5781c6589b67d419
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19728
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The fstat64 system call does an upcast on entries in the file
descriptor array to check if the file descriptor has a backing
host-filesystem file opened. It does so because it needs to pass
the host fd into the fstat call (since we rely on the host
filesystem to service filesystem system calls).
The upcast was overly specific. This changeset alters the system
call to use the most general base class of the file descriptor
entries that can satisfy the code.
Change-Id: I10daf820257cea4d678ee6917e01e9cc9cd1cf5e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17110
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
This addresses the issue described in
64687ee mem-cache: Mark block as dirty after a SWPrefetchEXResp.
Previous patch misses cases when the prefetch response is ReadExResp or
UpgradeResp. Also, marking the block as dirty in serviceMSHRTargets
instead of in handleFill covers cases when the prefetch is coalesced with
other requests.
Change-Id: I2b377fdd240eb0f09e720b6bb284dee6545925ce
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19688
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This patch is rewriting the SMMUv3::processCommand method for the
following reasons:
* Command names were not matching spec
* Command encoding/opcode was wrong
The patch is not adding any new command: there is still a subset of
unimplemented commands; those are:
* CMD_TLBI_EL3_ALL
* CMD_TLBI_EL3_VA
* CMD_TLBI_EL2_ALL
* CMD_TLBI_EL2_VA
* CMD_TLBI_EL2_VAA
* CMD_TLBI_EL2_ASID
which require StreamWorld support, and
* CMD_ATC_INV
* CMD_PRI_RESP
* CMD_RESUME
* CMD_STALL_TERM
which require in sequence: ATS, PRI, Stall Model support
Change-Id: Ia2dd47b5588738402d9584a00cfc88c94c253ad0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Michiel van Tol <michiel.vantol@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19668
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Add this check because Gicv3 does not have the cpu_addr attribute.
Test: Change VExpress_GEM5_V1() to VExpress_GEM5_V2() and run the
following command to boot Debian.
M5_PATH=$PWD/fs_files ./build/ARM/gem5.opt ./configs/example/arm/fs_bigLITTLE.py \
--dtb $PWD/fs_files/binaries/armv8_gem5_v2_1cpu.dtb \
--kernel $PWD/fs_files/binaries/vmlinux \
--disk $PWD/fs_files/disks/disk.img \
--cpu-type atomic --big-cpus 1 --little-cpus 0
Change-Id: I23595ae5238dc7cc915ab09300f91aa5e8c24fdc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19648
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The assert() in the LSQ writeback() only allowed ReExec faults.
However, a SplitRequest which completed the translation in
PartialFault state (i.e. any but the very first cacheline
translation failed) may end up here. The assert() condition is
extended accordingly.
The patch also removes the superfluous/unused Complete/Squashed
states from the LSQ request. (The completion of the request is
recorded in the flags still.)
Change-Id: Ie575f4d3b4d5295585828ad8c7d3f4c7c1fe15d0
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19174
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
SMMU circular queues have a wrap bit which is used in order to
distinguish between an empty queue and a full queue.
According to SMMUv3 spec:
Each index has a wrap flag, represented by the next higher bit adjacent
to the index value contained in PROD and CONS. This bit must toggle each
time the index wraps off the high end and back onto the low end of the
buffer. It is the responsibility of the owner of each index, producer or
consumer, to toggle this bit when the owner updates the index after
wrapping. It is intended that software reads the register, increments or
wraps the index (toggling wrap when required) and writes back both wrap
and index fields at the same time.
Change-Id: Idfeb397141f3627c2878caaeaa2625fadf671d2a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com>
Reviewed-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19311
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
