This changes the base classes for load-store instructions
and introduces two new classes for DS form instructions
which use a shifted signed immediate field as the offset
from the base address and for X form instructions which
use registers for both the offset and the base address.
The formats have also been updated to make use of the new
base classes.
Change-Id: Ib5d1bb5d7747813e0e5b1e3075489f1a3aa72660
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40892
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
ACPI's MADT describes the interrupt system of a processor/system and
partially replaces the Intel MP tables. The config now simply adds the
ACPI variant, so an OS can use either Intel MP or ACPI for interrupt
configuration.
Change-Id: Ie3d293aac0925666f7661a03eab10218f04c8d0c
Signed-off-by: Maximilian Stein <m@steiny.biz>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42825
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
This extends the ACPI implementation to support the MADT. This table
contains information about the interrupt system (Local APIC, IO-APIC)
and partially replaces the Intel MP tables.
The change is particularly needed to support other OSes than Linux that
do not support Intel MP.
Change-Id: I132226f46f4d54e2e0b964e2986004e3e5f5f347
Signed-off-by: Maximilian Stein <m@steiny.biz>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41953
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The RSDP points to the RSDT (32 bit) and/or the XSDT (64 bit), which are
both instances of the abstract System Description Table.
This commit implements the mechanism to write the three data structures
to memory based on the full system's configuration. The SysDescTable
class acts as base class for the RSDT and XSDT as well as any future
implementation of other System Description Tables.
Change-Id: I710279a72376c04f2a636ff2e96fa80228d03eaf
Signed-off-by: Maximilian Stein <m@steiny.biz>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42824
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
When RS and RA are both used as operands by an instruction,
RS takes precedence over RA. In such cases, either both the
register operands are used as sources or RS is a source and
RA is a destination.
This changes the order by giving RS the highest precedence
and will be useful for proper disassembly generation.
Change-Id: If351a03a814653f2f371afa936ec7a5cd4377b3a
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40890
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The initial device contains enough code for the gpufs configuration
scripts to register an amdgpu device that identifies as a Vega 10
(Frontier Edition) device when PCI devices are listed by Linux. It also
contains stubs necessary for adding the MMIO interface to handle driver
initialization.
Using the configuration Linux boots and the device is successfully seen
in lspci. The driver can also begin loading an successfully sends
initial MMIOs and attempts to read the ROM.
Change-Id: I7ad87026876f31f44668e700d5adb639c2c053c1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44909
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This macro is directly expecting a Debug::Flag instance as a first
argument instead of simply the name of the debug flag, and it is
forwarding it with no preprocessing to the underlying logic
(dprintf_flag).
This is different from the common DPRINTF, which is converting the
first argument into a flag and into a string literal.
This is useful if we want to pass the DebugFlag from the subclass to
the superclass. This makes it possible to set tracepoints in the
Base class logic, and let the Derived classes define the flag which
will enable the tracepoint
class Base
{
Base(const Debug::SimpleFlag &_flag)
: flag(_flag) {}
void baseLogic()
{
DPRINTFV(flag, "...");
}
const Debug::SimpleFlag flag;
}
class Derived1 : public Base
{
Derived1() : Base(Debug::Derived1) {}
}
class Derived2 : public Base
{
Derived2() : Base(Debug::Derived2) {}
}
A more concrete example is Arm Table Walker, which is using a DmaPort.
If we want to log the table walker port activity, we are using the
--debug-flags=DMA, which is unconvenient as it will contain the
logs from every DMA device in the simulation
Change-Id: I793cf1521303fd0a3bbea2059a9447386f83661e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44967
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
This adds the definition of the Target Address Register (TAR)
and the following instructions that are associated with it.
* Move To Target Address Register (mttar)
* Move From Target Address Register (mftar)
* Branch Conditional to Branch Target Address Register (bctar[l])
Change-Id: I30f54ebd38b503fb6c9ba9dd74d00ccbbc0f8318
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40889
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Among the register-based conditional branch instructions,
the ones using CTR should not decrement CTR when the bit
corresponding to this action is set in the BO field of
the instruction. In this case, the instruction should be
considered invalid. This fixes the following instructions.
* Branch Conditional to Count Register (bcctr[l])
Change-Id: Ib2dbf2bc36fced580b4b7f7b76783f68361f6bbf
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40887
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
checkpoint-tester script tests gem5's checkpoints by
using gem5 to produce a series of checkpoints, each with
a specified interval. After that, for all K > 1,
each of K-th produced checkpoint is used by gem5 to produce
the {K+1}-th checkpoint. The newly produced checkpoint will
be compared against the {K+1}-th checkpoint that was
previously produced.
Previously, in the tester script, the inputs to
`--take-checkpoints X,Y` was `(interval, interval)`.
The intention was to restore the N-th checkpoint and to run
the simulation for `interval` ticks.
According to the current configs/common/Options.py file,
`--take-checkpoints X,Y` means `X` is the starting tick of
the simulation, while `Y` is the number of ticks to be simulated
after tick `X`.
Therefore, `X` should be the starting tick of the N-th checkpont,
and this change addresses this problem.
Change-Id: I1fd7c91c9454f42a4fb98aa878fb5e4ac7d238f3
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44449
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This changes the base classes for branch instructions and
switches to two high-level classes for unconditional and
conditional branches. The conditional branches are further
classified based on whether they use an immediate field or
a register for determining the target address.
Decoding has also been consolidated using formats that can
generate code after determining if an instruction branches
to an absolute address or a PC-relative address, or if it
implicitly sets the return address by looking at the AA and
LK bits.
Change-Id: I5fa7db7b6693586b4ea3c71e5cad8a60753de29c
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40886
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
When multiple instructions share the same primary opcode,
the decoder can distinguish between them by looking at the
extended opcode field. However, the length and position of
the extended opcode field can slightly vary depending on
the instruction form.
This ensures that the correct extended opcode fields are
used for decoding such instructions.
Change-Id: I8207568ac975587377abba8a9b221ca3097b8488
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40885
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This adds 64-bit statically linked big and little endian
binaries for the hello test program.
It should be noted that all possible combinations of ABI
version and endianness are possible for 64-bit binaries.
However, standard toolchains always use ELF ABI v1 for
big endian and ELF ABI v2 for little endian binaries.
Change-Id: I2dca7eaa2b04a7b68b117ada799d4c3bb69368be
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40951
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Commit a440108cc ("tests: Add Makefiles for hello")
introduced Makefiles for building the hello test binary
for ARM and x86 using dockcross. Since dockcross also
provides an image with a 64-bit little endian toolchain
for Power, this adds a Makefile for building the hello
binary.
As of this moment, 64-bit little endian (ppc64le) is the
prevalent variant supported by most distributions. Hence,
we are currently limited to only building the binary for
this variant.
Change-Id: Ic20322ca33c69634d9f17d30b29e522cc35742fb
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40949
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Rather than decode and call each PsuedoInst function one by one, we can
use a GuestABI which knows how to marshal arguments and return values
and call the pseudoInst dispatch function which will do the work for us,
and make SPARC able to call any pseudo inst, not just the ones it was
hard coded to recognize.
Change-Id: I28192c4feeaf86a77c0f23c5b131929e45ec6d74
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42388
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Only one is set up corrent, the one passed in from the constructor.
Others can be added with addThreadContext.
The inconsistency of adding one ThreadContext through the constructor
and others through addThreadContext isn't great, but this way we can
ensure that there is always at least one ThreadContext. I'm not sure
what the GDB stub should do if there aren't any threads. I don't think
that the protocol can actually handle that, judging from the
documentation I can find.
Change-Id: I9160c3701ce78dcbbe99de1a6fe2a13e7e69404e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44611
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Distinguish between the 'g' and 'c' subcommands. 'c' sets what thread(s)
should be continued or single stepped when those commands are used, and
'g' sets what thread(s) should be used for anything else. Also, insist
that all threads are used for continuing or single stepping.
Still complain if we're asked to switch threads, since we only have one
and we can't change to anything else.
Change-Id: Ia15c055baba48f75fc29ef369567535b0aa2c76b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44609
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Just because the current methods of the base class only call
Event::trace from within DTRACE(Event), that's no guarantee that future
methods will, that the call sites won't be changed so that they don't,
or any number of subclasses that may not even exist today will.
Instead, we should incur the very slight overhead of checking the
Debug::Event variable again to ensure expected behavior, and to avoid
unnecessary complexity for a very small optimization when we're already
enabled a high overhead behavior like tracing for all events in a
virtual function.
Change-Id: I1c360b2ba73ad73c0658e85e9122f1fef07f93ce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44986
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This is aligning with RISCV and X86. Prior to this patch the Arm
TableWalker was using the TLBVerbose flag. We now use the generic
PageTableWalker flag, in most of the table walker code.
We still rely on the TLBVerbose for some methods.
Those are not conceptually related to the table walker:
For example the memAttrs methods are populating the TLB entry fields
before inserting it in the TLB. Describing the entry fields is
not strictly related to the walking mechanism
Change-Id: Ia75fef052cd44905cc41247f8e590e3ce3912252
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44966
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This is an initial configuration capable of booting Linux and
registering a PCI device which registers as an AMD Vega 10 (Frontier
Edition) GPU. It it loosely based on the the example/fs.py and gem5 book
full system example scripts. The top-level file is meant to be modular
such that convenience scripts can be created to set arguments
automatically and then call the main run function.
This will evolve over time as more full-system GPU components are added
and the network topology needed for disjoint address spaces is created
for the VIPER protocol.
Change-Id: I7002213ca8de5eb73919e49fb11840a688744012
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44907
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
There is a design which has been put forward which eliminates the idea
of a zero register entirely, but in the mean time, to get rid of one
more ISA specific constant, this change moves the ZeroReg constant into
the RegClassInfo class, specifically the IntRegClass instance which is
published by each ISA.
When the idea of zero registers has been eliminated entirely from
non ISA specific code, this and the existing machinery can be
eliminated.
Change-Id: I4302a53220dd5ff6b9b47ecc765bddc6698310ca
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42685
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gem5 defines several types of memory access including normal read,
normal write, atomic operations. For now we only support normal read
and normal write converting from SystemC via TLM2. To support atomic
operations from SystemC, we add an atomic extension. A SystemC model can
fire a atomic request with the extension.
The extension mainly has two attributes. One is a AtomicOpFunctor which
is the implementation of the atomic operation. The other one is bool
which indicates the gem5 request flag should be ATOMIC_RETURN_OP or
ATOMIC_NO_RETURN_OP.
Change-Id: I817727dd4b2d357667f928063210c58a44c81afb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44525
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
The prior example config for FS fails SMP boot on the KVMX86CPU.
These updates incorporate logic x86-boot-tests/system/
[system.py|run_exit.py] as well as configs/example/arm/
fs_bigLITTLE.py to enable both single processor and SMP boot.
Each KVM VM now uses its own eventq and a non-zero sim_quantum.
Change-Id: I9c73a2f6f2ca604aecd31f45570423c58f85020f
Signed-off-by: Kevin Loughlin <kevlough@umich.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41602
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The GPU VIPER TCC protocol accidentally used "TiggerMsg" instead
of "TriggerMsg" for the triggerQueue_in port. This was a benign
bug beacuse the msg type is not used in the in_port implementation
but still makes the SLICC harder to understand, so fixing it is
worthwhile.
Change-Id: I88cbc72bac93bcc58a66f057a32f7bddf821cac9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44905
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Previously the pyunit tests needed run in the gem5 root, this change
allows them to run as part of the quick TestLib tests (thereby having
them run as part of the presubmit checks). This runs all the TestLib
tests as a single test using the NULL gem5 binary.
`tests/run_pyunit.py` has been updated to only parse files with the
`pyunit` prefix in their filname. As such `pyunit/util/test_convert.py`
has been renamed `pyunit/util/pyunit_convert_check.py`. The word `test`
has been removed entirely as to not clash with the testlib tests as run
by `tests/main.py`.
Example usage:
```
./main.py run --uid SuiteUID:tests/pyunit/test_run.py:pyunit-tests-NULL-x86_64-opt
```
Discussed briefly in email thread:
https://www.mail-archive.com/gem5-dev@gem5.org/msg38563.html
Change-Id: Id566d44fcb5d8c599eb1a90bca56793158a201e6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44625
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
