arch-power: Fix disassembly for branch instructions

This fixes disassembly generated for branch instructions
based on the AA and LK bits which determine how the target
address is calculated and whether a return address needs
to be set implicitly or not.

Change-Id: I1acba72c360a1fcb4691de17fbae1a012a752dbe
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40888
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Sandipan Das
2021-02-06 17:16:46 +05:30
committed by Boris Shingarov
parent 1517cdf8a7
commit cdd5c5671f

View File

@@ -67,7 +67,16 @@ BranchOp::generateDisassembly(
std::stringstream ss;
Addr target;
ccprintf(ss, "%-10s ", mnemonic);
// Generate correct mnemonic
std::string myMnemonic(mnemonic);
std::string suffix;
// Additional characters depending on isa bits being set
if (lk)
suffix += "l";
if (aa)
suffix += "a";
ccprintf(ss, "%-10s ", myMnemonic + suffix);
if (aa)
target = li;
@@ -102,10 +111,19 @@ BranchDispCondOp::generateDisassembly(
std::stringstream ss;
Addr target;
ccprintf(ss, "%-10s ", mnemonic);
// Generate the correct mnemonic
std::string myMnemonic(mnemonic);
std::string suffix;
// Additional characters depending on isa bits being set
if (lk)
suffix += "l";
if (aa)
suffix += "a";
ccprintf(ss, "%-10s ", myMnemonic + suffix);
// Print BI and BO fields
ss << bi << ", " << bo << ", ";
ss << (int) bi << ", " << (int) bo << ", ";
if (aa)
target = bd;
@@ -136,10 +154,17 @@ BranchRegCondOp::generateDisassembly(
{
std::stringstream ss;
ccprintf(ss, "%-10s ", mnemonic);
// Generate the correct mnemonic
std::string myMnemonic(mnemonic);
std::string suffix;
// Additional characters depending on isa bits being set
if (lk)
suffix += "l";
ccprintf(ss, "%-10s ", myMnemonic + suffix);
// Print the BI and BO fields
ss << bi << ", " << bo;
ss << (int) bi << ", " << (int) bo;
return ss.str();
}