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arch-power: Fix precedence of register operands

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When RS and RA are both used as operands by an instruction,
RS takes precedence over RA. In such cases, either both the
register operands are used as sources or RS is a source and
RA is a destination.

This changes the order by giving RS the highest precedence
and will be useful for proper disassembly generation.

Change-Id: If351a03a814653f2f371afa936ec7a5cd4377b3a
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40890
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Sandipan Das
2021-02-06 17:16:54 +05:30
committed by Boris Shingarov
parent 808056ce4e
commit 73eb5a84cb
1 changed files with 3 additions and 3 deletions
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6
src/arch/power/isa/operands.isa
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@@ -41,9 +41,9 @@ def operand_types {{
def operands {{
# General Purpose Integer Reg Operands
'Ra': ('IntReg', 'ud', 'RA', 'IsInteger', 1),
'Rb': ('IntReg', 'ud', 'RB', 'IsInteger', 2),
'Rs': ('IntReg', 'ud', 'RS', 'IsInteger', 3),
'Rs': ('IntReg', 'ud', 'RS', 'IsInteger', 1),
'Ra': ('IntReg', 'ud', 'RA', 'IsInteger', 2),
'Rb': ('IntReg', 'ud', 'RB', 'IsInteger', 3),
'Rt': ('IntReg', 'ud', 'RT', 'IsInteger', 4),
# General Purpose Floating Point Reg Operands