derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch-power: Add and rename some opcode fields

Browse Source 
This introduces separate extended opcode (XO) fields for DS,
X, XFL, XFX, XL and XO form instructions and renames the
primary opcode field to PO based on the convention used in
the Power ISA manual.

Change-Id: I82598efe74c02960f38fe4ed5e22599340f7e15c
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40884
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
This commit is contained in:
Sandipan Das
2021-02-06 17:16:30 +05:30
committed by Boris Shingarov
parent 9457415729
commit 89a95c1f7a
4 changed files with 11 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/arch/power/isa/bitfields.isa
View File

@@ -34,10 +34,14 @@
// are reversed sometimes. Not sure of a fix to this though...
// Opcode fields
def bitfield OPCODE <31:26>;
def bitfield X_XO <10:0>;
def bitfield XO_XO <10:1>;
def bitfield PO <31:26>;
def bitfield A_XO <5:1>;
def bitfield DS_XO <1:0>;
def bitfield X_XO <10:1>;
def bitfield XFL_XO <10:1>;
def bitfield XFX_XO <10:1>;
def bitfield XL_XO <10:1>;
def bitfield XO_XO <9:1>;
// Register fields
def bitfield RA <20:16>;

2
src/arch/power/isa/decoder.isa
View File

@@ -34,7 +34,7 @@
// Power ISA v3.0B has been used for instruction formats, opcode numbers,
// opcode field names, register names, etc.
//
decode OPCODE default Unknown::unknown() {
decode PO default Unknown::unknown() {
format IntImmArithOp {
7: mulli({{

2
src/arch/power/isa/formats/unimp.isa
View File

@@ -112,7 +112,7 @@ output exec {{
Trace::InstRecord *traceData) const
{
panic("attempt to execute unimplemented instruction '%s' "
"(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst, OPCODE,
"(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst, PO,
inst2string(machInst));
return std::make_shared<UnimplementedOpcodeFault>();
}

4
src/arch/power/isa/formats/unknown.isa
View File

@@ -63,7 +63,7 @@ output decoder {{
Addr pc, const Loader::SymbolTable *symtab) const
{
return csprintf("%-10s (inst 0x%x, opcode 0x%x, binary:%s)",
"unknown", machInst, OPCODE, inst2string(machInst));
"unknown", machInst, PO, inst2string(machInst));
}
}};
@@ -73,7 +73,7 @@ output exec {{
{
panic("attempt to execute unknown instruction at %#x"
"(inst 0x%08x, opcode 0x%x, binary: %s)",
xc->pcState().pc(), machInst, OPCODE, inst2string(machInst));
xc->pcState().pc(), machInst, PO, inst2string(machInst));
return std::make_shared<UnimplementedOpcodeFault>();
}
}};