Commit Graph

20549 Commits

Author SHA1 Message Date
Bobby R. Bruce
26a1ee4e61 configs: 'memoy' -> 'memory' spelling mistake fix (#314)
Fixes https://github.com/gem5/gem5/issues/309
2023-09-13 22:59:48 -07:00
Bobby R. Bruce
7a17c780bd misc: Use 'workdir' for docker-build.yaml (#320) 2023-09-13 22:54:01 -07:00
Bobby R. Bruce
772a316dab misc: Use 'workdir' for docker-build.yaml
Change-Id: If8b30a31e1a8c3fdba84d69da4bb28e09179cb96
2023-09-13 22:52:26 -07:00
Bobby R. Bruce
61339b6471 misc: Fix docker build workflow (#319) 2023-09-13 22:48:20 -07:00
Bobby R. Bruce
dc02862c56 misc: Fix docker build workflow
Change-Id: Ib66cc124a4c3ce1354faee092f14543e699dca40
2023-09-13 22:47:08 -07:00
Bobby R. Bruce
1d160e6ab0 scons: Revert "Add an option specifying the path to mold linker binary" (#313)
Reverts https://github.com/gem5/gem5/pull/244

Fixes https://github.com/gem5/gem5/issues/312
2023-09-13 22:02:30 -07:00
Bobby R. Bruce
b53a311363 misc,util-docker: Fix docker-build.yaml (#285)
https://github.com/gem5/gem5/actions/runs/6114221855 failure was due to
to running the actions inside our 22.04-all-dependencies container. This
container does not contain docker. We must therefore run this action
outside of the container. However, due to our policy of checking out the
code within this container, we must split this into two jobs and use the
artifact upload and download to get the resources we want.
2023-09-13 15:54:15 -07:00
Bobby R. Bruce
d38c029195 mem-ruby: This commit patches an error in AbstractController.cc (#294)
Links to #293 

After calling m5_dump_reset_stats(0,0) in a test program, some
statistics like
l1_controllers.L1Dcache.m_demand_hits,
l1_controllers.L1Dcache.m_demand_misses,
l1_controllers.L1Dcache.m_demand_accesses
were not getting reset in the newer stat dumps.
This one line patch fixes that. Changes were tested with calling two
m5_dump_reset_stats(0,0) in a row for a system with 1 core, tested on
both SE and FS.
Credits: @MeatBoy106
2023-09-13 15:48:46 -07:00
Bobby R. Bruce
673d4b2ac2 arch-x86: initialize and correct bitwidth for FPU tag word (#304)
The x87 FPU tag word (FTW) was not explicitly initialized in
{X86_64,i386}Process::initState(), resulting in holding an initial value
of zero, resulting in an invalid x87 FPU state. This commit initializes
FTW to 0xFFFF, indicating the FPU is empty at program start during
syscall emulation.

The 16-bit FTW register was also incorrectly masked down to 8-bits in
X86ISA::ISA::setMiscRegNoEffect(), leading to an invalid X87 FPU state
that later caused crashes in the X86KvmCPU. This commit corrects the
bitwidth of the mask to 16.

GitHub issue: https://github.com/gem5/gem5/issues/303
2023-09-13 15:47:50 -07:00
Bobby R. Bruce
23c1014677 util: Fix TLM configs making use of TraceCPU replayer (#310)
A recent PR [1] moved the TraceCPU away from the BaseCPU hierarchy.
While the common etrace_replayer.py has been amended, I missed these
hybrid TLM + TraceCPU example scripts.

[1]: https://github.com/gem5/gem5/pull/302
2023-09-13 15:47:05 -07:00
Bobby R. Bruce
e42d71e802 configs: 'memoy' -> 'memory' spelling mistake fix
Fixes https://github.com/gem5/gem5/issues/309

Change-Id: I41ac7c5559d49353d01b3676b5bdf7b91e4efbda
2023-09-13 14:30:22 -07:00
Bobby R. Bruce
d463f73a43 scons: Revert "Add an option specifying the..."
Change-Id: I2bd952d3cfd6c3c671b5ab3458e44c53f93bf649
2023-09-13 14:28:05 -07:00
Gautham Pathak
87db6df8f6 mem-ruby: This commit patches an error in AbstractController.cc
After calling m5_dump_reset_stats(0,0) in a test program,
some statistics like
l1_controllers.L1Dcache.m_demand_hits,
l1_controllers.L1Dcache.m_demand_misses,
l1_controllers.L1Dcache.m_demand_accesses
were not getting reset in the newer stat dumps.
This one line patch fixes that. Changes were tested with
calling two m5_dump_reset_stats(0,0) in a row for a system
with 1 core, tested on both SE and FS.
Credits to Gabriel Busnot for finding the fix.

Change-Id: I19d75996fa53d31ef20f7b206024fd38dbeac643
2023-09-13 14:07:16 -04:00
Giacomo Travaglini
f95e1505b8 util: Fix TLM configs making use of TraceCPU replayer
A recent PR [1] moved the TraceCPU away from the BaseCPU hierarchy.
While the common etrace_replayer.py has been amended, I missed these
hybrid TLM + TraceCPU example scripts.

[1]: https://github.com/gem5/gem5/pull/302

Change-Id: I7e9bc9a612d2721d72f5881ddb2fb4d9ee011587
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2023-09-13 13:36:33 +01:00
Bobby R. Bruce
5fd901ffbb cpu, configs: Fix TraceCPU after multi-ISA addition (#302)
This PR fixes #301
2023-09-12 17:26:27 -07:00
Nicholas Mosier
2178e26bf2 arch-x86: initialize and correct bitwidth for FPU tag word
The x87 FPU tag word (FTW) was not explicitly initialized in
{X86_64,i386}Process::initState(), resulting in holding an initial
value of zero, resulting in an invalid x87 FPU state. This commit
initializes FTW to 0xFFFF, indicating the FPU is empty at program
start during syscall emulation.

The 16-bit FTW register was also incorrectly masked down to 8-bits
in X86ISA::ISA::setMiscRegNoEffect(), leading to an invalid X87 FPU
state that later caused crashes in the X86KvmCPU. This commit
corrects the bitwidth of the mask to 16.

GitHub issue: https://github.com/gem5/gem5/issues/303

Change-Id: I97892d707998a87c1ff8546e08c15fede7eed66f
2023-09-12 15:39:29 +00:00
Bobby R. Bruce
1bebf6a3cc sim-se: Use tgt_stat64 instead of tgt_stat in newfstatatFunc (#283)
The syscall emulation of newfstatat incorrectly treated the output stat
buffer to be of type `OS::tgt_stat`, not `OS::tgt_stat64`, causing the
invalid output stat buffer in the application to hold invalid data.

This patch fixes the bug by simply substituting the type `OS::tgt_stat`
with `OS::tgt_stat64` in `newstatatFunc()`.

GitHub issue: https://github.com/gem5/gem5/issues/281
2023-09-12 08:33:42 -07:00
Bobby R. Bruce
94e5a0cccf sim-se: Fix tgkill logic bug in handling signal argument (#286)
The syscall emulation of tgkill contained a simple logic bug (a `||`
instead of a `&&`), causing the signal argument to always be considered
invalid. This patch fixes the bug by simply changing the `||` to a `&&`.

GitHub issue: https://github.com/gem5/gem5/issues/284
2023-09-12 08:32:56 -07:00
Bobby R. Bruce
d67a6603c1 cpu-kvm: properly set x86 xsave header on gem5->KVM transition (#298)
If the XSAVE KVM capability is available (KVM_CAP_XSAVE), the X86KvmCPU
will try to set the x87 FPU + SSE state using KVM_SET_XSAVE, which
expects a buffer (struct kvm_xsave) in XSAVE area format (Vol. 1, Sec.
13.4 of Intel x86 SDM). The original implementation of
`X86KvmCPU::updateKvmStateFPUXSave()`, however, improperly sets the
xsave header, which contains a bitmap of state components present in the
xsave area.

This patch defines `XSaveHeader` structure to model the xsave header,
which is expected directly following the legacy FPU region (defined in
the `FXSave` structure) in the xsave area. It then sets two bist in the
xsave header to indicate the presence of x86 FPU and SSE state
components.

GitHub issue: https://github.com/gem5/gem5/issues/296
2023-09-12 08:32:20 -07:00
Bobby R. Bruce
5fefbe2933 arch-riscv: Enable RVV run in Minor and O3 CPU (#228)
Changes in the PR:

1. Change the vset\*vl\* instructions to jump/branch family, and
implement the branchTarget.
2. Move the Vl and Vtype from decoder to PCState
3. get VL, VTYPE and VLENB value from PCState
4. Remove vtype checking in construction so that the minor and o3 cpu
and decode the instructions after the vset\*vl\*
2023-09-12 08:31:36 -07:00
Giacomo Travaglini
a0a799f474 cpu: Disable CPU switching functionality with TraceCPU
Now that the TraceCPU is no longer a BaseCPU we disable CPU switching
functionality. AFAICS from the code, it seems like using m5.switchCpus
was never really working.
The takeOverFrom was described as being used when checkpointing
(which is not really the case). Moreover the icache/dcache
event loops were not checking if the CPU was switched out
so the trace was always been consumed regardless of the BaseCPU
state.

Note: IMHO the only case where you might want to switch between
an execution-driven CPU to the TraceCPU is when you want to
warm your caches before the ROI.
All other cases don't really make sense as with the TraceCPU
there is no architectural state being maintained/updated.

Change-Id: I0611359d2b833e1bc0762be72642df24a7c92b1e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2023-09-12 15:50:05 +01:00
Giacomo Travaglini
785eba6ce1 configs: Reflect TraceCPU changes in the etrace_replay script
As we no longer inherit from the BaseCPU, we can't really use
CPU generation methods (like Simulation.setCPUClass) and
cache generation ones (like CacheConfig.config_cache).

This is good news as it allows us to simplify the etrace
script and to remove a dependency with the deprecated-to-be
common library.

Change-Id: Ic89ce2b9d713ee6f6e11bf20c5065426298b3da2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2023-09-12 15:49:39 +01:00
Giacomo Travaglini
9a5d900770 cpu: Stop treating TraceCPU as a BaseCPU
This is fixing a recently reported issue [1] where it is
not possible to use the TraceCPU to replay elastic traces

It requires some architectural data structures (like ArchMMU,
ArchDecoder...) which are no longer defined in the BaseCPU class at
compilation time.  Which Arch version should be used for a class
(TraceCPU) that is supposed to be ISA agnostic ? Does it really make
sense to define them for the TraceCPU? Those classes are not used anyway
during trace replay and their sole purpose would just be to comply to
the BaseCPU interface.

As there is no elegant way to make things work, this patch stops
treating the TraceCPU as a BaseCPU.

While it philosophically makes sense to treat the TraceCPU as a common
CPU (it sort of replays pre-executed instructions), a case can be made
for considering it more like a traffic generator.

[1]: https://github.com/gem5/gem5/issues/301

Change-Id: I7438169e8cc7fb6272731efb336ed2cf271c0844
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2023-09-12 15:49:29 +01:00
Roger Chang
e41184fafc util: Update the RISC-V PCState checkpoint
Change-Id: I64b6a3e1706173a001f5f8fb06756bd50d65f5bd
2023-09-12 17:54:35 +08:00
Roger Chang
def89745bc arch-riscv: Allow Minor and O3 CPU execute RVV
Change-Id: I4780b42c25d349806254b5053fb0da3b6993ca2f
2023-09-12 13:56:22 +08:00
Roger Chang
0f54cb0593 arch-riscv: Remove check vconf done implementation
Change-Id: If633cef209390d0500c4c2c5741d56158ef26c00
2023-09-12 13:56:22 +08:00
Roger Chang
31b95987da arch-riscv: Change the instruction family to jump like
The method that get the vl, vtype from PCState in the next changes

Change-Id: I022b47b7a96572f6434eed30dd9f7caa79854c31
2023-09-12 13:56:22 +08:00
Roger Chang
282765234b arch-riscv: Implement the branchTarget for vset*vl*
Change-Id: I10bf6be736ce2b99323ace410bff1d8e1e2a4123
2023-09-12 13:56:22 +08:00
Roger Chang
a3aaad2ecd arch-riscv: Refactor the execution part of vset*vl*
Change-Id: Ie0d9671242481a85bb0fe5728748b16c3ef62592
2023-09-12 13:56:21 +08:00
Roger Chang
1bde42760f arch-riscv: Get vl, vtype and vlenb from PCState
Change-Id: I0ded57a3dc2db6fcc7121f147bcaf6d8a8873f6a
2023-09-12 13:56:21 +08:00
Roger Chang
8918302239 arch-riscv: Change the implementation of vset*vl*
The changes includes:

1. Add VL, Vtype and VlenbBits operands
2. Change R/W methods of VL, Vtype and VlenbBits from PCState

Change-Id: I0531ddc14344f2cca94d0e750a3b4291e0227d54
2023-09-12 13:56:21 +08:00
Roger Chang
7b5d8b4e5b arch-riscv: Add vlenb, vtype and vl in PCState
Change-Id: I7c2aed7dda34a1a449253671d7b86aa615c28464
2023-09-12 13:56:21 +08:00
Roger Chang
f94658098d arch-riscv: Remove checked_type in StaticInst Constructor
We should not try to check vtype when decoding the instruction.
It should be checked in vset{i}vl{i} since the register can be
modified via vset{i}vl{i}

Change-Id: I403e5c4579bc5b8e6af10f93eac20c14662e4d2d
2023-09-12 13:56:21 +08:00
Roger Chang
3f0475321a arch-riscv: Change VTYPE to BitUnion64
Change-Id: I7620ad1ef3ee0cc045bcd02b3c9a2d83f93bf3fe
2023-09-12 13:56:21 +08:00
Roger Chang
dfc725838e arch-riscv: Refactor PCState class
Change-Id: I1d25350ba2a3c7c366f42340c20b4488c33cde6f
2023-09-12 13:56:21 +08:00
Bobby R. Bruce
a217c218e0 util: Update gcn-gpu Dockerfile (#290)
This adds the setting up of environment variables to the gcn-gpu
Dockerfile from the halofinder Dockerfile in gem5-resources so that we
don't need to use a separate Docker image in the gpu tests.
2023-09-11 11:19:49 -07:00
Jason Lowe-Power
a89aeb3906 util: Revert "Add docker prune cron to GitHub..." (#299)
This reverts commit 0249d47acc,
https://github.com/gem5/gem5/pull/271.

This solution doesn't work. GitHub runners pull the images they need at
the start of job (i.e., all the images they may need for each step).
They then create the containers later, at the step they are needed. This
solution therefore breaks in the case a cleanup happens during the
running of a job. I.e., a `docker system prune` happens after setup,
therefore deleting all the images, then the job tries to use one of the
images during a step.

This crontab solution may work if we can only do it when the runner is
in an idle state. Whether this is possible is unknown.
2023-09-11 09:33:28 -07:00
Bobby R. Bruce
7091a8b7a0 util: Revert "Add docker prune cron to GitHub..."
This reverts commit 0249d47acc,
https://github.com/gem5/gem5/pull/271.

This solution doesn't work. GitHub runners pull the images they need at
the start of job (i.e., all the images they may need for each step).
They then create the containers later, at the step they are needed.
This solution therefore breaks in the case a cleanup happens during the
running of a job. I.e., a `docker system prune` happens after setup,
therefore deleting all the images, then the job tries to use one of the
images during a step.

This crontab solution may work if we can only do it when the runner is
in an idle state. Whether this is possible is unknown.

Change-Id: I7cb5b2d98d596e9380ae1525c7d66ad97af1b59b
2023-09-10 20:32:49 -07:00
Nicholas Mosier
2b9d558cef cpu-kvm: properly set x86 xsave header on gem5->KVM transition
If the XSAVE KVM capability is available (KVM_CAP_XSAVE), the X86KvmCPU
will try to set the x87 FPU + SSE state using KVM_SET_XSAVE, which
expects a buffer (struct kvm_xsave) in XSAVE area format (Vol. 1,
Sec. 13.4 of Intel x86 SDM). The original implementation of
`X86KvmCPU::updateKvmStateFPUXSave()`, however, improperly sets the
xsave header, which contains a bitmap of state components present
in the xsave area.

This patch defines `XSaveHeader` structure to model the xsave header,
which is expected directly following the legacy FPU region (defined in
the `FXSave` structure) in the xsave area. It then sets two bist in
the xsave header to indicate the presence of x86 FPU and SSE state
components.

GitHub issue: https://github.com/gem5/gem5/issues/296

Change-Id: I5c5c7925fa7f78a7b5e2adc209187deff53ac039
2023-09-10 15:16:50 +00:00
Nicholas Mosier
8740385f9e sim-se: Fix tgkill logic bug in handling signal argument
The syscall emulation of tgkill contained a simple logic bug
(a `||` instead of a `&&`), causing the signal argument to always
be considered invalid. This patch fixes the bug by simply changing
the `||` to a `&&`.

GitHub issue: https://github.com/gem5/gem5/issues/284

Change-Id: I3b02c618c369ef56d32a0b04e0b13eacc9fb4977
2023-09-09 08:51:41 -07:00
Jason Lowe-Power
ebde1133c0 redirect_path patch for restoring cpt (#221)
Modify the FDArray::unserialize function to perform a checkPathRedirect
if a Process pointer is passed in.
Currently when restoring a checkpoint, it doesn't perform
checkPathRedirect for files that were opened during checkpointing. This
patch adds a checkPathRedirect in the FDArray::unserialize to redirect
app path for restoring checkpoints.
2023-09-08 15:30:53 -07:00
Nicholas Mosier
259a5d6272 sim-se: Use tgt_stat64 instead of tgt_stat in newfstatatFunc
The syscall emulation of newfstatat incorrectly treated the output
stat buffer to be of type `OS::tgt_stat`, not `OS::tgt_stat64`, causing
the invalid output stat buffer in the application to hold invalid
data.

This patch fixes the bug by simply substituting the type `OS::tgt_stat`
with `OS::tgt_stat64` in `newstatatFunc()`.

GitHub issue: https://github.com/gem5/gem5/issues/281

Change-Id: Ice97c1fc4cccbfb6824e313ebecde00f134ebf9c
2023-09-08 11:28:54 -07:00
Bobby R. Bruce
d5f5211b91 scons: Add an option specifying the path to mold linker binary (#244)
To use mold linker with gcc of version older than 12.1.0, the user has
to pass the -B option to specify where the linker is. [1]

Currently in gem5, scons only looks for the mold binary at conventional
places, such as /usr/libexec/mold and /usr/local/libexec/mold. There's
no option to manually specify the path to the linker.

gcc-12 and mold are not widely available on older systems. Having an
option to manually input the linker path allows user to build and use
mold without sudo permission.

[1] https://github.com/rui314/mold#how-to-use
2023-09-08 11:21:29 -07:00
Melissa Jost
16e8c95091 util: Update gcn-gpu Dockerfile
This adds the setting up of environment variables to the gcn-gpu
Dockerfile from the halofinder Dockerfile in gem5-resources
so that we don't need to use a seperate Docker image in the
gpu tests.

Change-Id: Ifcc7a4c6bbcd5289ce9561923366e9ed193f170c
2023-09-08 10:25:09 -07:00
Bobby R. Bruce
ce27f5c07a sim-se: Fix crash in chdirFunc() on nonexistent directory (#277)
This commit fixes a crash in the syscall emulation of the chdir(2)
syscall, implemented by chdirFunc() in src/sim/syscall_emul.cc, when
passed a nonexistent directory. The buggy code did not check the return
value of realpath().

This patch adds code to check the return value of realpath(), and if it
is NULL (i.e., there was an error with the requested directory to change
to), propagates the error in `errno` to the application.

GitHub issue: https://github.com/gem5/gem5/issues/276
2023-09-08 10:10:30 -07:00
Nicholas Mosier
e0498cb490 Merge branch 'develop' into bugfix-chdir 2023-09-07 14:13:00 -07:00
Bobby R. Bruce
75a33ec377 misc,util-docker: Fix docker-build.yaml
https://github.com/gem5/gem5/actions/runs/6114221855 failure was due
to to running the actions inside our 22.04-all-dependencies container.
This container does not contain docker. We must therefore run this action
outside of the container. However, due to our policy of checking out the
code within this container, we must split this into two jobs and use the
artifact upload and download to get the resources we want.

Change-Id: I6a5f9c3a4c287a56a3d5abe3b84dd560fa2e9ff1
2023-09-07 14:07:36 -07:00
Bobby R. Bruce
ce54ff061a scons: Fix 'recompiling' -> 'recompile'
Change-Id: Ifb2366a0c2342bf4e7207df8db6196e14184a9d5
2023-09-07 12:52:31 -07:00
Bobby R. Bruce
aca67fe3a3 misc: Add test status badges to README.md (#233)
These allow visitors to the repository to quickly see the status of our
tests run on the develop branch.
2023-09-07 12:47:00 -07:00
Bobby R. Bruce
eb5ae35341 resources,stdlib: Add workload to resource specialization and deprecate workload.py (#212) 2023-09-07 12:45:45 -07:00