Commit Graph

16495 Commits

Author SHA1 Message Date
Daniel R. Carvalho
23f8efc73b base: Remove negation operator in Flag
There is already a bool conversion operator, so there
is no need to provide a negation operator.

Change-Id: If5f99f8a0bb1707c115d139417aedd47bd162963
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38708
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-01-13 11:15:18 +00:00
Daniel R. Carvalho
ba284a13dd base: Fix uninitialized variable in Flag
This was uninitialized, and was breaking expected values
under certain situations.

Change-Id: If51ab6ae038c7c397bc83de1c73af348c1db4ef8
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38707
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-01-13 11:15:18 +00:00
Daniel R. Carvalho
3b03eaab9c mem-cache: Fix update of useful prefetches
The probe notification must be parsed on every hit, even if
the prefetcher is set not to generate prefetches on accesses.
This fixes the calculation of useful prefetches.

Change-Id: Iff298f7bea11013f411f4ba39dba705fd81a0cd4
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38177
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-01-13 11:12:23 +00:00
Gabe Black
c6933a27da misc: Fix missing includes.
Change-Id: I545ff03041e8fe66dc489c6aa95c009e54df0970
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38995
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-01-13 08:55:59 +00:00
Gabe Black
a7f3c5aad2 base: Remove begin() and end() from CircleBuf.
These functions return iterators which are inconsistent with the usage
model for this type. It should be accessed using the peek, push, and pop
methods and not iterators. If you need a class with iterators which is
oriented around accessing individual elements at a time, the
CircularQueue type is likely a better choice.

Change-Id: I9f37eab12e490b63d870d378a91f601dad353f25
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38998
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-01-13 02:33:58 +00:00
Gabe Black
43114ad1dd dev: Use regular atomic accesses for DMA in bypass mode.
These are now accelerated with backdoor accesses and should be at least
as fast as functional accesses. This removes a dependency on port
proxies, and also stops the HDLCD from using functional accesses.

Change-Id: I5e959288eb533d09cffa7b79938aa2f61e4aff7d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38720
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-01-13 01:29:32 +00:00
Gabe Black
c5da197679 dev: Teach the DmaPort to use atomic memory backdoors.
This is implemented similary to the NonCachingSimpleCPU, except that
both the normal atomic and noncaching atomic behaviors are implemented
by the same class. The sendDma function now dispatches to a method which
implements one or the other behavior since that function was getting too
big and complex.

Change-Id: I7972971ef41d1373424e587cf67c8444d50de748
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38719
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-01-13 01:29:10 +00:00
Gabe Black
93c0fdfb12 dev: Generate DMA packets as needed.
Instead of generating all of the DMA packets when a request is
initiated, keep track of the necessary properties and generate them as
needed.

The primary benefit of this approach is that if we don't actually need
packets, for instance if we can satisfy the request using a memory
backdoor, we can just skip them. Otherwise we'll have wasted time
creating them, and then have to clean them up.

Change-Id: I04d399fb7bce1ff9a44979c311be356baf2db555
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38717
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-01-13 01:28:46 +00:00
Gabe Black
65828b2735 base: Re-implement CircleBuf without using CircularQueue.
CircularQueue provides iterators which make it easier for users to
interact with it and helps abstract its internal state, but at the same
time it prevents standard algorithms like std::copy from recognizing
opportunities to use bulk copies to speed up execution. It also hides
the seams when wrapping around the buffer happens which std::copy
wouldn't know how to handle.

CircleBuf seems to be intended as a simpler type which doesn't hold
complex entries like the CircularQueue does, and instead just acts as a
wrap around buffer, like the name suggests. This change reimplements it
to not use CircularQueue, and to instead use an underlying vector.

The way internal indexing is handled CircularQueue was simplified
recently, and using the same scheme here means that this code is
actually not much more verbose than it was before. It also intrinsically
handles indexing and bulk accesses, and uses std::copy_n in a way that
lets it recognize and take advantage of contiguous storage and bulk
copies.

Change-Id: I78e7cfe174c52f60c95c81e5cd3d71c6052d4d41
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38896
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-01-13 01:28:09 +00:00
Gabe Black
28f8a39726 base: Add a setNext method to the ChunkGenerator.
This method lets you stretch the current chunk, if you want to skip over
some of the upcoming chunks since you've already handled their bytes.

For instance, if you were iterating over pages in a range of virtual
addresses, you might be able to handle multiple page sized chunks at
once if they were represented by a single large sized page table entry.
This mechanism would let you move past all the pages you had just
handled without having to walk through them all one by one.

Change-Id: I7d962f548947b77f0aa1b725036dbcc9e1b28659
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38718
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-01-09 13:18:48 +00:00
Kyle Roarty
f6ec145fc0 gpu-compute: Fix FLAT insts decrementing lgkm count early
FLAT instructions used to decrement lgkm count on execute, while the
GCN3 ISA specifies that lgkm count should be decremented on data being
returned or data being written.

This patch changes it so that lgkm is decremented after initiateAcc (for
stores) and after completeAcc (for loads) to better reflect the ISA
definition.

This fixes a bug where waitcnts would be satisfied even though the
memory access wasn't completed, which lead to instructions using the
wrong data.

Change-Id: I596cb031af9cda8d47a1b5e146e4a4ffd793d36c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38696
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-01-07 17:12:31 +00:00
Giacomo Travaglini
3c0769bd25 configs: Remove default bootscript option for fs_bigLITTLE.py
Since the beginning fs_bigLITTLE has been pointing to a default

default_rcs = 'bootscript.rcS'

as a System.readfile parameter. That script is not present in
the gem5 repo and all the other fs scripts (starter_fs.py, fs.py
through Options.py) are using an emptry string as default
readfile param value.

We are hence aligning to the other scripts by removing this
default value

Change-Id: I20dc7714deae890d61706459c8d13bd8f5aac7a0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38815
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-01-07 09:37:40 +00:00
Adrian Herrera
00dd0d7b3d dev-arm: SMMUv3, enable interrupt interface
Users can set "irq_interface_enable" to allow software to program
SMMU_IRQ_CTRL and SMMU_IRQ_CTRLACK. This is required to boot Linux v5.4+
in a reasonable time. Notice the model does not implement architectural
interrupt sources, so no assertions will happen.

Change-Id: Ie138befdf5a204fe8fce961081c575c2166e22b9
Signed-off-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38555
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2021-01-07 09:07:09 +00:00
Gabe Black
131ae4a2eb dev: Remove the return type from DmaPort::dmaAction.
This function had a comment claiming that returning an arbitrary request
from the call was necessary for page table walker statistics, but
looking at the actual code, the return type was never used. Also
returning whatever the last request happens to be seems arbitrary, and a
bad boundary for modularization. The page table walker should not depend
on the internal implementation of the DMA port.

Change-Id: I00281fbaf6aeb85b15baf54f3d4a23ca1ac72b8b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38716
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-01-06 06:33:50 +00:00
Gabe Black
e5c8f03b21 dev: Fix style in the pixel pump base class.
Change-Id: I8aa25911b367d36d6862780b39781f13724e79dc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38715
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-01-06 04:26:33 +00:00
Gabe Black
2bf116e859 dev: Style fixes in the ARM HDLCD device.
Change-Id: I230e0e0db879a56bc23c3ed439b9722e76cdd8e4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38484
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-01-06 04:26:10 +00:00
Cui Jin
8c3658939d arch-riscv: fix the wrong cause register setting
The most significant bit should be set based on interrupt or
exception. I assume in current RV64 implementation the bit should
be 63rd, rather than 31st. This causes interrupt handler to get
invalid cause code.

Minor bug is for the mpie is suppossed to be set to the value of
old mie.

The fix is verified in FS.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-858

Change-Id: I1cc166c254b35f5c1acb3f5774c43149c61cc37a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38755
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-01-06 01:18:15 +00:00
Gabe Black
3059c6df5c arch: Add a mechanism to pad the src or dest reg index arrays.
ARM reaches in and pads out the source register index list behind the
parser's back to force dest regs to also be sources in case an
instruction fails predication and needs to forward the original register
values. It shouldn't be hacking up these values in that way, but since
it is, this will let it continue to do so while still fitting in the new
system where each instruction allocates its src/dest reg index arrays to
size.

Change-Id: Ia296be9f63123f18f6cdc0d3bb1314d33e759b3a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38380
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-01-05 07:33:01 +00:00
Gabe Black
27a41d6ef6 dev: Cache the cacheLineSize in the DMA read FIFO.
This is a minor simplification which decouples the FIFO from the system
object at run time, although it does need to read the cache line size
out at construction time.

Change-Id: I57d96a676b9604663b6c9ed7c662640f507c5305
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38482
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-01-05 02:09:25 +00:00
Gabe Black
9e97dbe8c8 dev: Make DMA devices use their own ports for functional accesses.
DMA devices already have ports they use for non-functional accesses. We
can just attach a port proxy to that instead of getting one from the
system object.

Change-Id: I5e9adee43c7fe07b4c90978dbb7ec71468caadbb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38481
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
2020-12-31 10:19:12 +00:00
Gabe Black
f16bfed9ea dev: Style fixes in src/dev/dma_device.(cc|hh).
Change-Id: Ie72f30d95e7f889f9a440d0fed57a5940747b40d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38480
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-12-31 10:18:55 +00:00
Gabe Black
b3dd0d4f99 base: Style fixes in the CircleBuf and Fifo classes.
Change-Id: Ia08548027973e2b18e09bc3f05a6498855bdd7f7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38479
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2020-12-31 10:18:46 +00:00
Gabe Black
fa36e7d560 base,cpu: Simplify the CircularQueue class significantly.
This class had been trying to keep all indices within the modulus of the
queue size, and to use all elements in the underlying storage by making
the empty and full conditions alias, differentiated by a bool. To keep
track of the difference between a storage location on one trip around
the queue vs other times around, ie an alias once the indices had
wrapped, it also keep track of a "round" value in both the queue itself,
and any iterators it created.

All this bookkeeping significantly complicated the data structure.
Instead, this change modifies it to keep track of a monotonically
increasing index which is wrapped at the time it's used. Only the head
index and current size need to be tracked in the queue itself, and only
a pointer to the queue and an index need to be tracked in the iterators.

Theoretically, it's possible that this value could overflow eventually
since it increases forever, unlike before where the index wrapped and
was never larger than the queue's capacity. In practice, the type of the
index was changed from a uint32_t to a size_t, probably a 64 bit value
in modern systems, which will hold much larger values. Also, the round
counter and the index values together acted like a smaller than 64 bit
value anyway, since the round counter would overflow after 2^32 times
around a less than 2^32 entry queue.

One minor interface difference is that the head() and tail() values
returned by the queue are no longer pre-wrapped to be modulo the queue's
capacity. As long as consumers don't try to be overly clever and feed in
fixed values, do their own bounds checking, etc., something that would
be cumbersome considering the wrapping nature of the structure, this
shouldn't be an issue.

Also, since external consumers no longer need to worry about wrapping,
since only one of them was used in only one place, and because they
weren't even marked as part of the interface, the modulo helper
functions have been eliminated from the queue. If other code wants to
perform modulo arithmetic for some reason (which the queue no longer
requires) they can accomplish basically the same thing in basically the
same amount of code using normal math.

Also, rather than inherit from std::vector, this change makes the vector
internal to the queue. That prevents methods of the vector that aren't
aware of the circular nature of the structure from leaking out if
they're not overridden or otherwise proactively blocked.

On top of simplifying the implementation, this also makes it perform
*slightly* better. To measure that, I ran the following command:

$ time build/ARM/base/circular_queue.test.opt --gtest_repeat=100000 > /dev/null

and found a few percent improvement in total run time. While this
difference was small and not measured against realistic usage of the
data structure, it was still measurable, and at minimum doesn't seem to
have hurt performance.

Change-Id: Ic2baa28de135be7086fa94579bbec451d69b3b15
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38478
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-12-31 10:18:36 +00:00
Gabe Black
be7043f079 base: Fix style issues in the circular queue.
Change-Id: I61da587d760019a338522f098745f375a5ce429e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38477
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-12-31 10:18:18 +00:00
Cui Jin
acfb233685 arch-riscv: fix MIE csr register setting bugs
Any changes on xIE bits changes should trigger the updating
of CSR register. The old condition is wrongly reversed.

The fix is verified in FS.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-855

Change-Id: Ia2c6d3fbfd24d7f9d23f7cfa6f25f893544f4157
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38578
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-12-31 03:17:09 +00:00
Yu-hsin Wang
400152d5cb ext: googletest: upgrade to googletest 1.10
Upgrade googletest to 1.10
upstream commit: 703bd9caab50b139428cea1aaff9974ebee5742e
tag: release-1.10.0

sha1sum c4bb446ee3f8a730168097f44c31c90b62c63287 generated by command:
find . -type f ! -name SConscript ! -path "./.git/*" ! -name ".*" -print0 \
| sort -z | xargs -0 sha1sum | sha1sum

Change-Id: I6500e13e9c094efd99ebc72b3ae564861e67c159
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38577
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-12-30 02:10:10 +00:00
Hoa Nguyen
8da27ca382 scons: Fix the scons script failing to install git hooks
A recent change,
https://gem5-review.googlesource.com/c/public/gem5/+/38616,
removed the 'root' environment variable, while the git hooks
installation script relies on the variable. This commit
addresses this problem.

Change-Id: I2d27861794021a6a60ef8668461e4127cb1db261
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38655
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-12-23 02:37:27 +00:00
Daniel R. Carvalho
4dc09a9543 mem-cache: Generate error on compression misconfiguration
Compressed caches must use the compressed tags, otherwise a
seg fault will be generated. Besides, if no compressor is
assigned; yet compressed tags are used, data is not compressed.

Generate an error for the first case, and a warning for the
second.

Change-Id: Iac5474ed919163ce38a8c4e8efd9727e5b3d8417
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38635
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-12-22 16:03:34 +00:00
Hoa Nguyen
0badfdb207 mem-ruby: Update stats style for SimpleNetwork
Change-Id: I7d54ed02d01a3811b41dce794e308b8b77576c92
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38055
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-12-22 09:52:36 +00:00
Hoa Nguyen
fa81ca4988 sim: Update stats style of System and Process
Change-Id: I3af072a61a18f4fbba3f7d4b632c58501e7b7ae8
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37995
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2020-12-22 09:52:36 +00:00
Hoa Nguyen
6a80d9f0aa mem-ruby: Update stats of AbstractController and derived classes
This commit moves stats of AbstractController and its derived
classes to a Stats::Group struct.

Also, one of the controllers needs access to the ruby system profiler
stats, and Profiler's stats is now made public as a result.

Change-Id: Ibe04e33a6cf09b453564592d29293b354d0d33c9
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38075
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-12-22 09:52:36 +00:00
Hoa Nguyen
4c42811ff3 mem-ruby: Move CacheMemory stats used in SLICC to a Stats group
This change moves some stats that are used in SLICC to a
separate Stats::Group.

In order to use stats in SLICC, new functions are added in
CacheMemory:
        - profileDemandHit()
        - profileDemandMiss()

The functions increase the corresponding stat by 1.

Change-Id: I52b6fefdf6579a49f626f2fca400641f90800017
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37815
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-12-22 09:52:36 +00:00
Hoa Nguyen
78270ede7b mem-ruby: Update stats style
This commit makes move stats from several classes in mem/ruby
to corresponding Stats::Group's.

For ruby's Profiler, additional changes are made: there are stats that
are profiled for each of RequestType, for each of MachineType, and for
each of combinations of RequestType and MachineType. The current naming
scheme is ...<stat_name>.<request_type_name>.<machine_type_name>. To make
it easier for stats parser to know whether the stat is of RequestType, or
is of MachineType, or is of (RequestType, MachineType), a prefix is added
as follows,
	...<meta>.<stat_name>.<request_type_name>.<machine_type_name>
where <meta> is one of {RequestType, MachineType, RequestTypeMachineType}.

Another point of using this naming scheme is that the parser doesn't
need to know all of RequestType and MachineType.

Change-Id: I8b8bdd771c7798954f984d416f521e8eb42d01ed
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36478
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-12-22 09:52:36 +00:00
Hoa Nguyen
6da3e5748f util: Add reviewers using account ID's when possible
Currently, there are some accounts that cannot be added as a
reviewer due to unknown conflicts associated with the email address.

This commit adds the ability for the bot to use
ReviewerInfo._account_id when possible, and to use email addresses
otherwise.

To reduce the number of queries to the server, a json file will be
created in .data/ to store known account ID's.

Change-Id: I9887bec12d14279e61119a615687a339e3f9c994
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38236
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-12-22 09:52:30 +00:00
Hoa Nguyen
350278b84d python: Improve SimObject's warning when parent specified twice
SimObject outputs a warning when its parent is specified more than
once. The cause is most likely that there is unexpected param
specified in the constructor called in the Python interface.

This commit adds a note about this probable cause of this potential
error to the warning message.

Change-Id: I9b6bf5d5fb0c77bfdad5fde42e88f814e8a4b72b
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38359
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-12-22 09:52:23 +00:00
Gabe Black
40af27b571 util: Force the m5 utility to be built using c++14.
Otherwise, the version of the standard being used will depend on the
version of the compiler, and may not build consistently on different
machines.

Change-Id: I3a031a2dfe97df3dd83926abb517781069c1c6a5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38216
Reviewed-by: Daniel Gerzhoy <daniel.gerzhoy@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-12-21 23:48:14 +00:00
Gabe Black
99d96b76cb util: Break up some unit tests in the m5 utility.
Some unit tests for the inst and semi call types in the m5 utility were
too big and testing multiple scenarioes. This change breaks them up into
individual tests, like in the addr call type unit test.

Change-Id: I764d9edfbe4f6bdcc5907173247f7511c68aa1d0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36855
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-12-21 23:48:07 +00:00
Gabe Black
c110695a44 util: Use the std namespace for memcpy and memset in the m5 util.
The C++ versions of those functions are technically in the std
namespace, and while they may work without it (the C version leaking
through from somewhere?), they should still use it.

Change-Id: Ib53a7f0c41d7f5776221e7661c616ea51e8ed528
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31834
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2020-12-21 23:47:59 +00:00
Gabe Black
3fa1ce6d72 util: Expose addr config mechanisms in the gem5 op java wrapper.
These allow you to set the target physical address, and map or unmap the
region of physical memory. This is not automatic for two reasons. First,
the address needs to be configured before the mapping is done, and
there's no way to ensure that ordering when everything is handled
automatically. Second, if the user isn't going to use the address based
mechanism, then the mapping and access to /dev/mem isn't necessary and
may prevent using the other call types.

Change-Id: I0f9c32d6bfa402ba59ea1bf5672fb7f11003568d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28184
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-12-21 23:47:51 +00:00
Gabe Black
c3f882f905 util: Embed the JNI library (.so) in the jar file for the gem5 ops.
This makes it easier to manage the java wrapper since there's only one
file. This change also splits up the command builder which builds the
java jar since we need to run one step which produces the .h, then a
second step to build the library, and then finally the step that
produces the jar. The first step is left as a command builder since the
scons Java builder still doesn't know about the -h option, but the
second step now uses the Jar builder.

Change-Id: I76e2e5e86bb3153f2ba69a75ad94cd4e065cd33d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28183
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-12-21 23:47:36 +00:00
Gabe Black
48f7ee9244 util: Enable using different call types in the gem5 ops java wrapper.
Convert the native implementation from C to C++. Also expand the test to
cycle through the different call mechanisms and call "sum" using each
one. This test should primarily be run on a gem5 native CPU which will
support all call types.

To access a particular call type, get an instance of the gem5.Ops class
from the callTypes static map, using the name of the call type you want
as the key. If you just want whatever the default is, use the additional
key "default".

Change-Id: If4ef812c9746fbf974e54cc9fe515e2b581e9939
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28182
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-12-21 23:47:22 +00:00
Gabe Black
40deabcc48 scons,fastmodel: Change how ARM license slots are throttled.
To limit the number of license slots used by SCons when building fast
model components, the fastmodel SConscript set up a group of nodes
which are attached to each simgen run using the SCons SideEffect
method using one of the library files it generates.

To create each unique node, the SCons Value() method was used, passing
it the counter for the loop. In at least version 4 of SCons, what this
ended up doing was setting that library file as a source for each of
the Value() nodes it corresponds to.

That doesn't *seem* like a problem, but then when creating config
include files, files which expose SCons configuration values to C++,
they also create Value() nodes using the value of the config variable.
In cases where that variable is boolean, the value might be 0 or 1.

The result was that the config header depended on Value(0) (for
instance), and then Value(0) depended on a collection of static library
files.

When scons tried to determine whether the config file was up to date,
it tried to check if if its sources had changed. It would check
Value(0), and then Value(0) would try to compute a checksum for its own
source. To do that, it seems to assume that the value can be
interpreted as a string and tries to decode it as utf8. Since the
library is a binary file, that would fail and break the build with a
cryptic message from within the guts of SCons.

To address this, this change replaces the loop index with a call to
object(). Each instance created in that way will be different from
every other, and there will be no way (purposefully or otherwise) to
create a collision with it when creating Value() nodes for some other
purpose.

Change-Id: I56bc842ae66b8cb36d3dcbc25796b708254d6982
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38617
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Reviewed-by: Ahbong Chang <cwahbong@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-12-21 21:53:40 +00:00
Gabe Black
a4e5d2cbb9 scons: Stop auto including the git tool from the default too override.
SCons has a system of "tools", which basically detect versions of build
tools (compilers, linkers, etc) and set up an environment with the
appropriate build variable substitutions for that tool to be used.

For instance, there would be a "tool" for gcc, and it would detect if
gcc is present on the system, and if so would set the "CC" variable to
"gcc". An actually tool as defined by SCons would be a lot more
sophisticated than that and set more variables, but that's the basic
idea.

To help modularize the gem5 SConstruct file, I moved code which would
set up git commit hooks into a "tool" which helped modularize it and
reduce the size of SConstruct.

This isn't quite right since, while the code does detect if git was
used to check out the source (if there is a .git file at the root), it
doesn't really modify the environment at all. It will also be invoked
every time any environment is set up, although right now that will only
be the DefaultEnvironment, what's used when loose functions like
Builder or Command are called with, and the "main" environment which
all the others are Clone-d from.

Normally, when SCons sets up a new environment, either implicitly or
when Environment() is called, it sets up a bunch of built in tools
which are fixed within SCons itself. If you want, you can add a "tools"
argument to Environment (or to the DefaultEnvironment() function) which
will replace that list of tools. That can be used to make an
environment use the new "git" tool, but it isn't automatic.

SCons also lets you override default tools by creating your own with
the same name as the default. To make loading the git tool automatic,
I added an override "default" tool which, in addition to setting some
defaults which should apply to all environments, also pulled in other
tools, at that time "git" and "mercurial" (RIP).

Unfortunately, that meant that today, apparently particularly with
SCons version 4, *any* Environment would pull in "git", and all of
"git"'s dependencies, even if SCons wasn't set up enough for those to
work.

To break that dependency, this change stops the default tool from
automatically loading the git tool, although it does continue to set
other defaults which have very minimal external dependencies. When
creating the "main" Environment in the SConstruct, the "git" tool is
now added in explicitly. Since the list of tools replaces the original
and doesn't extend it, we have to add in "default" explicitly as well.

Really, the "git" tool should be converted from the tool interface into
something more appropriate, like perhaps a small module under
site_scons which site_init.py can import and call. When that happens,
main can be declared like normal again.

While making this change, I also got rid of a few nonstandard additions
to the main environment that were little used and not really necessary.
When reading the SConstruct, it wasn't very obvious where those extra
values were coming from, and they didn't really add any value.

Change-Id: I574db42fc2196bf62fc13d6754357c753ceb9117
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38616
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-12-21 21:53:33 +00:00
Bobby R. Bruce
79ed97f37b util,python: Updated maintainers.py to fix deprecation warning
The following warning was being thrown:

```
util/maint/lib/maintainers.py:120: YAMLLoadWarning: calling yaml.load() without Loader=... is deprecated, as the default Loader is unsafe. Please read https://msg.pyyaml.org/load for full details.
```

This is fixed by adding `Loader=yaml.SafeLoader` when calling
`yaml.load()`.

Change-Id: I3b79115379a45409967a8848175658ab3c13bfc7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38476
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-12-18 22:26:05 +00:00
Bobby R. Bruce
9c556e7935 util,python: Updated git-pre-commit.py to use Python3
Change-Id: I3897a57237637a55e75b3c9c4cb43918b39cf7d0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38475
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-12-18 22:26:05 +00:00
Gabe Black
150fef8453 dev: Use BitUnions and a RegisterBank in the Uart8250.
Change-Id: I139db4f08f9e6addfed4906ea6c49ee67439d30e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36818
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-12-18 00:30:55 +00:00
Gabe Black
3eb63b688f x86: Fix some comments in x86 KVM process initialization.
These comments did not reflect what the code was actually doing.

Change-Id: I2bcd23bd68c870e364bdfd0b9b0eb5dcb560e713
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38537
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-12-17 03:30:20 +00:00
Gabe Black
aad4ee30c4 x86: Change some CR0 settings when setting up kvm x86 processes.
These values were (seemingly) arbitrarily changed from the original,
non-KVM settings, and no longer matched the comments which were also
copied over. These two bits enable alignment checking on memory accesses
(not normally used on x86), and whether kernel code can write to read
only pages.

Change-Id: I48e560e448e4849607f12e9336d1ab0458ad9407
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38536
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-12-17 03:30:01 +00:00
Gabe Black
cc0d4a8fd6 arm: Fix style in the ISA templates.
Change-Id: I3014d26c8649efaf6227f2e3a798cc6c4183a0c5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38379
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-12-16 13:19:21 +00:00
Daniel R. Carvalho
491b9874d2 mem-cache: Implement a frequency-sampling compressor
Implementation of a generic frequency-based sampling
compressor. The compressor goes through a sampling stage,
where no compression is done, and the values are simply
sampled for their frequencies. Then, after enough samples
have been taken, the compressor starts generating
compressed data.

Compression works by comparing chunks to the table of
most frequent values. In theory, a chunk that is present
in the frequency table has its value replaced by the
index of its respective entry in the table. In practice,
the value itself is stored because there is no straight-
forward way to acquire an index from an entry.

Finally, the index can be encoded so that the values
with highest frequency have smaller codeword representation.
Its Huffman coupling can be used similar to the approach
taken in "SC 2 : A Statistical Compression Cache Scheme".

Change-Id: Iae0ebda08e8c08f3b62930fd0fb7e818fd0d141f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37335
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-12-16 12:13:05 +00:00