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mem-ruby: Move CacheMemory stats used in SLICC to a Stats group

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This change moves some stats that are used in SLICC to a
separate Stats::Group.

In order to use stats in SLICC, new functions are added in
CacheMemory:
        - profileDemandHit()
        - profileDemandMiss()

The functions increase the corresponding stat by 1.

Change-Id: I52b6fefdf6579a49f626f2fca400641f90800017
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37815
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Hoa Nguyen
2020-11-19 17:45:07 -08:00
parent 78270ede7b
commit 4c42811ff3
19 changed files with 132 additions and 116 deletions
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4
src/mem/ruby/protocol/GPU_VIPER-TCC.sm
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@@ -439,11 +439,11 @@ machine(MachineType:TCC, "TCC Cache")
}
action(p_profileMiss, "pm", desc="Profile cache miss") {
++L2cache.demand_misses;
L2cache.profileDemandMiss();
}
action(p_profileHit, "ph", desc="Profile cache hit") {
++L2cache.demand_hits;
L2cache.profileDemandHit();
}
action(t_allocateTBE, "t", desc="allocate TBE Entry") {

4
src/mem/ruby/protocol/GPU_VIPER-TCP.sm
View File

@@ -529,11 +529,11 @@ machine(MachineType:TCP, "GPU TCP (L1 Data Cache)")
// added for profiling
action(uu_profileDataMiss, "\udm", desc="Profile the demand miss"){
++L1cache.demand_misses;
L1cache.profileDemandMiss();
}
action(uu_profileDataHit, "\udh", desc="Profile the demand hit"){
++L1cache.demand_hits;
L1cache.profileDemandHit();
}

8
src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
View File

@@ -771,19 +771,19 @@ machine(MachineType:L0Cache, "MESI Directory L0 Cache")
}
action(uu_profileInstMiss, "\ui", desc="Profile the demand miss") {
++Icache.demand_misses;
Icache.profileDemandMiss();
}
action(uu_profileInstHit, "\uih", desc="Profile the demand hit") {
++Icache.demand_hits;
Icache.profileDemandHit();
}
action(uu_profileDataMiss, "\ud", desc="Profile the demand miss") {
++Dcache.demand_misses;
Dcache.profileDemandMiss();
}
action(uu_profileDataHit, "\udh", desc="Profile the demand hit") {
++Dcache.demand_hits;
Dcache.profileDemandHit();
}
// store conditionals

4
src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
View File

@@ -774,11 +774,11 @@ machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP")
}
action(uu_profileMiss, "\um", desc="Profile the demand miss") {
++cache.demand_misses;
cache.profileDemandMiss();
}
action(uu_profileHit, "\uh", desc="Profile the demand hit") {
++cache.demand_hits;
cache.profileDemandHit();
}

8
src/mem/ruby/protocol/MESI_Three_Level_HTM-L0cache.sm
View File

@@ -915,19 +915,19 @@ machine(MachineType:L0Cache, "MESI Directory L0 Cache")
}
action(uu_profileInstMiss, "\ui", desc="Profile the demand miss") {
++Icache.demand_misses;
Icache.profileDemandMiss();
}
action(uu_profileInstHit, "\uih", desc="Profile the demand hit") {
++Icache.demand_hits;
Icache.profileDemandHit();
}
action(uu_profileDataMiss, "\ud", desc="Profile the demand miss") {
++Dcache.demand_misses;
Dcache.profileDemandMiss();
}
action(uu_profileDataHit, "\udh", desc="Profile the demand hit") {
++Dcache.demand_hits;
Dcache.profileDemandHit();
}
// store conditionals

8
src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
View File

@@ -956,19 +956,19 @@ machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP")
}
action(uu_profileInstMiss, "\uim", desc="Profile the demand miss") {
++L1Icache.demand_misses;
L1Icache.profileDemandMiss();
}
action(uu_profileInstHit, "\uih", desc="Profile the demand hit") {
++L1Icache.demand_hits;
L1Icache.profileDemandHit();
}
action(uu_profileDataMiss, "\udm", desc="Profile the demand miss") {
++L1Dcache.demand_misses;
L1Dcache.profileDemandMiss();
}
action(uu_profileDataHit, "\udh", desc="Profile the demand hit") {
++L1Dcache.demand_hits;
L1Dcache.profileDemandHit();
}
action(po_observeHit, "\ph", desc="Inform the prefetcher about the hit") {

4
src/mem/ruby/protocol/MESI_Two_Level-L2cache.sm
View File

@@ -732,11 +732,11 @@ machine(MachineType:L2Cache, "MESI Directory L2 Cache CMP")
}
action(uu_profileMiss, "\um", desc="Profile the demand miss") {
++L2cache.demand_misses;
L2cache.profileDemandMiss();
}
action(uu_profileHit, "\uh", desc="Profile the demand hit") {
++L2cache.demand_hits;
L2cache.profileDemandHit();
}
action(nn_addSharer, "\n", desc="Add L1 sharer to list") {

4
src/mem/ruby/protocol/MI_example-cache.sm
View File

@@ -350,11 +350,11 @@ machine(MachineType:L1Cache, "MI Example L1 Cache")
}
action(p_profileMiss, "pi", desc="Profile cache miss") {
++cacheMemory.demand_misses;
cacheMemory.profileDemandMiss();
}
action(p_profileHit, "ph", desc="Profile cache hit") {
++cacheMemory.demand_hits;
cacheMemory.profileDemandHit();
}
action(r_load_hit, "r", desc="Notify sequencer the load completed.") {

16
src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm
View File

@@ -1267,35 +1267,35 @@ machine(MachineType:CorePair, "CP-like Core Coherence")
}
action(l2m_profileMiss, "l2m", desc="l2m miss profile") {
++L2cache.demand_misses;
L2cache.profileDemandMiss();
}
action(l10m_profileMiss, "l10m", desc="l10m miss profile") {
++L1D0cache.demand_misses;
L1D0cache.profileDemandMiss();
}
action(l11m_profileMiss, "l11m", desc="l11m miss profile") {
++L1D1cache.demand_misses;
L1D1cache.profileDemandMiss();
}
action(l1im_profileMiss, "l1lm", desc="l1im miss profile") {
++L1Icache.demand_misses;
L1Icache.profileDemandMiss();
}
action(l10h_profileHit, "l10h", desc="l10h hit profile") {
++L1D0cache.demand_hits;
L1D0cache.profileDemandHit();
}
action(l11h_profileHit, "l11h", desc="l11h hit profile") {
++L1D1cache.demand_hits;
L1D1cache.profileDemandHit();
}
action(l1ih_profileHit, "l1lh", desc="l1ih hit profile") {
++L1Icache.demand_hits;
L1Icache.profileDemandHit();
}
action(l2h_profileHit, "l2h", desc="l2h hit profile") {
++L2cache.demand_hits;
L2cache.profileDemandHit();
}
action(yy_recycleProbeQueue, "yy", desc="recycle probe queue") {

8
src/mem/ruby/protocol/MOESI_AMD_Base-Region-CorePair.sm
View File

@@ -1421,19 +1421,19 @@ machine(MachineType:CorePair, "CP-like Core Coherence")
}
action(l10m_profileMiss, "l10m", desc="l10m miss profile") {
++L1D0cache.demand_misses;
L1D0cache.profileDemandMiss();
}
action(l11m_profileMiss, "l11m", desc="l11m miss profile") {
++L1D1cache.demand_misses;
L1D1cache.profileDemandMiss();
}
action(l1im_profileMiss, "l1lm", desc="l1im miss profile") {
++L1Icache.demand_misses;
L1Icache.profileDemandMiss();
}
action(l2m_profileMiss, "l2m", desc="l2m miss profile") {
++L2cache.demand_misses;
L2cache.profileDemandMiss();
}
action(yy_recycleProbeQueue, "yy", desc="recycle probe queue") {

4
src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
View File

@@ -639,9 +639,9 @@ machine(MachineType:Directory, "AMD Baseline protocol")
//deallocated in dt_deallocateTBE (only for WB) as it checks the L3Hit flag of the TBE entry.
action(pr_profileL3HitMiss, "pr_l3hm", desc="L3 Hit or Miss Profile") {
if (tbe.L3Hit) {
++L3CacheMemory.demand_hits;
L3CacheMemory.profileDemandHit();
} else {
++L3CacheMemory.demand_misses;
L3CacheMemory.profileDemandMiss();
}
}

8
src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
View File

@@ -905,19 +905,19 @@ machine(MachineType:L1Cache, "L1 cache protocol")
}
action(uu_profileInstMiss, "\uim", desc="Profile the demand miss") {
++L1Icache.demand_misses;
L1Icache.profileDemandMiss();
}
action(uu_profileInstHit, "\uih", desc="Profile the demand hit") {
++L1Icache.demand_hits;
L1Icache.profileDemandHit();
}
action(uu_profileDataMiss, "\udm", desc="Profile the demand miss") {
++L1Dcache.demand_misses;
L1Dcache.profileDemandMiss();
}
action(uu_profileDataHit, "\udh", desc="Profile the demand hit") {
++L1Dcache.demand_hits;
L1Dcache.profileDemandHit();
}
action(z_recycleRequestQueue, "z", desc="Send the head of the mandatory queue to the back of the queue.") {

4
src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
View File

@@ -1560,11 +1560,11 @@ machine(MachineType:L2Cache, "Token protocol")
}
action(uu_profileMiss, "\um", desc="Profile the demand miss") {
++L2cache.demand_misses;
L2cache.profileDemandMiss();
}
action(uu_profileHit, "\uh", desc="Profile the demand hit") {
++L2cache.demand_hits;
L2cache.profileDemandHit();
}
action(y_copyCacheStateToDir, "y", desc="Copy cache state to directory state") {

8
src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
View File

@@ -1549,19 +1549,19 @@ machine(MachineType:L1Cache, "Token protocol")
}
action(uu_profileInstMiss, "\uim", desc="Profile the demand miss") {
++L1Icache.demand_misses;
L1Icache.profileDemandMiss();
}
action(uu_profileInstHit, "\uih", desc="Profile the demand hit") {
++L1Icache.demand_hits;
L1Icache.profileDemandHit();
}
action(uu_profileDataMiss, "\udm", desc="Profile the demand miss") {
++L1Dcache.demand_misses;
L1Dcache.profileDemandMiss();
}
action(uu_profileDataHit, "\udh", desc="Profile the demand hit") {
++L1Dcache.demand_hits;
L1Dcache.profileDemandHit();
}
action(w_assertIncomingDataAndCacheDataMatch, "w", desc="Assert that the incoming data and the data in the cache match") {

4
src/mem/ruby/protocol/MOESI_CMP_token-L2cache.sm
View File

@@ -981,11 +981,11 @@ machine(MachineType:L2Cache, "Token protocol")
}
action(uu_profileMiss, "\um", desc="Profile the demand miss") {
++L2cache.demand_misses;
L2cache.profileDemandMiss();
}
action(uu_profileHit, "\uh", desc="Profile the demand hit") {
++L2cache.demand_hits;
L2cache.profileDemandHit();
}
action(w_assertIncomingDataAndCacheDataMatch, "w", desc="Assert that the incoming data and the data in the cache match") {

12
src/mem/ruby/protocol/MOESI_hammer-cache.sm
View File

@@ -1266,27 +1266,27 @@ machine(MachineType:L1Cache, "AMD Hammer-like protocol")
}
action(uu_profileL1DataMiss, "\udm", desc="Profile the demand miss") {
++L1Dcache.demand_misses;
L1Dcache.profileDemandMiss();
}
action(uu_profileL1DataHit, "\udh", desc="Profile the demand hits") {
++L1Dcache.demand_hits;
L1Dcache.profileDemandHit();
}
action(uu_profileL1InstMiss, "\uim", desc="Profile the demand miss") {
++L1Icache.demand_misses;
L1Icache.profileDemandMiss();
}
action(uu_profileL1InstHit, "\uih", desc="Profile the demand hits") {
++L1Icache.demand_hits;
L1Icache.profileDemandHit();
}
action(uu_profileL2Miss, "\um", desc="Profile the demand miss") {
++L2cache.demand_misses;
L2cache.profileDemandMiss();
}
action(uu_profileL2Hit, "\uh", desc="Profile the demand hits") {
++L2cache.demand_hits;
L2cache.profileDemandHit();
}
action(zz_stallAndWaitMandatoryQueue, "\z", desc="Send the head of the mandatory queue to the back of the queue.") {

4
src/mem/ruby/protocol/RubySlicc_Types.sm
View File

@@ -211,8 +211,8 @@ structure (CacheMemory, external = "yes") {
int getNumBlocks();
Addr getAddressAtIdx(int);
Scalar demand_misses;
Scalar demand_hits;
void profileDemandHit();
void profileDemandMiss();
}
structure (WireBuffer, inport="yes", outport="yes", external = "yes") {

73
src/mem/ruby/structures/CacheMemory.cc
View File

@@ -68,16 +68,7 @@ CacheMemory::CacheMemory(const Params &p)
p.start_index_bit, p.ruby_system),
tagArray(p.tagArrayBanks, p.tagAccessLatency,
p.start_index_bit, p.ruby_system),
cacheMemoryStats(this),
ADD_STAT(m_demand_hits, "Number of cache demand hits"),
ADD_STAT(m_demand_misses, "Number of cache demand misses"),
ADD_STAT(m_demand_accesses, "Number of cache demand accesses",
m_demand_hits + m_demand_misses),
ADD_STAT(m_sw_prefetches, "Number of software prefetches"),
ADD_STAT(m_hw_prefetches, "Number of hardware prefetches"),
ADD_STAT(m_prefetches, "Number of prefetches",
m_sw_prefetches + m_hw_prefetches),
ADD_STAT(m_accessModeType, "")
cacheMemoryStats(this)
{
m_cache_size = p.size;
m_cache_assoc = p.assoc;
@@ -88,26 +79,6 @@ CacheMemory::CacheMemory(const Params &p)
m_block_size = p.block_size; // may be 0 at this point. Updated in init()
m_use_occupancy = dynamic_cast<ReplacementPolicy::WeightedLRU*>(
m_replacementPolicy_ptr) ? true : false;
m_sw_prefetches
.flags(Stats::nozero);
m_hw_prefetches
.flags(Stats::nozero);
m_prefetches
.flags(Stats::nozero);
m_accessModeType
.init(RubyRequestType_NUM)
.flags(Stats::pdf | Stats::total);
for (int i = 0; i < RubyAccessMode_NUM; i++) {
m_accessModeType
.subname(i, RubyAccessMode_to_string(RubyAccessMode(i)))
.flags(Stats::nozero)
;
}
}
void
@@ -559,7 +530,16 @@ CacheMemoryStats::CacheMemoryStats(Stats::Group *parent)
"transaction"),
ADD_STAT(htmTransAbortReadSet, "Read set size of a aborted transaction"),
ADD_STAT(htmTransAbortWriteSet, "Write set size of a aborted "
"transaction")
"transaction"),
ADD_STAT(m_demand_hits, "Number of cache demand hits"),
ADD_STAT(m_demand_misses, "Number of cache demand misses"),
ADD_STAT(m_demand_accesses, "Number of cache demand accesses",
m_demand_hits + m_demand_misses),
ADD_STAT(m_sw_prefetches, "Number of software prefetches"),
ADD_STAT(m_hw_prefetches, "Number of hardware prefetches"),
ADD_STAT(m_prefetches, "Number of prefetches",
m_sw_prefetches + m_hw_prefetches),
ADD_STAT(m_accessModeType, "")
{
numDataArrayReads
.flags(Stats::nozero);
@@ -595,6 +575,25 @@ CacheMemoryStats::CacheMemoryStats(Stats::Group *parent)
.init(8)
.flags(Stats::pdf | Stats::dist | Stats::nozero | Stats::nonan);
m_sw_prefetches
.flags(Stats::nozero);
m_hw_prefetches
.flags(Stats::nozero);
m_prefetches
.flags(Stats::nozero);
m_accessModeType
.init(RubyRequestType_NUM)
.flags(Stats::pdf | Stats::total);
for (int i = 0; i < RubyAccessMode_NUM; i++) {
m_accessModeType
.subname(i, RubyAccessMode_to_string(RubyAccessMode(i)))
.flags(Stats::nozero)
;
}
}
// assumption: SLICC generated files will only call this function
@@ -738,3 +737,15 @@ CacheMemory::htmCommitTransaction()
DPRINTF(HtmMem, "htmCommitTransaction: read set=%u write set=%u\n",
htmReadSetSize, htmWriteSetSize);
}
void
CacheMemory::profileDemandHit()
{
cacheMemoryStats.m_demand_hits++;
}
void
CacheMemory::profileDemandMiss()
{
cacheMemoryStats.m_demand_misses++;
}

63
src/mem/ruby/structures/CacheMemory.hh
View File

@@ -148,25 +148,6 @@ class CacheMemory : public SimObject
void htmCommitTransaction();
public:
struct CacheMemoryStats : public Stats::Group
{
CacheMemoryStats(Stats::Group *parent);
Stats::Scalar numDataArrayReads;
Stats::Scalar numDataArrayWrites;
Stats::Scalar numTagArrayReads;
Stats::Scalar numTagArrayWrites;
Stats::Scalar numTagArrayStalls;
Stats::Scalar numDataArrayStalls;
// hardware transactional memory
Stats::Histogram htmTransCommitReadSet;
Stats::Histogram htmTransCommitWriteSet;
Stats::Histogram htmTransAbortReadSet;
Stats::Histogram htmTransAbortWriteSet;
};
int getCacheSize() const { return m_cache_size; }
int getCacheAssoc() const { return m_cache_assoc; }
int getNumBlocks() const { return m_cache_num_sets * m_cache_assoc; }
@@ -224,17 +205,41 @@ class CacheMemory : public SimObject
*/
bool m_use_occupancy;
private:
struct CacheMemoryStats : public Stats::Group
{
CacheMemoryStats(Stats::Group *parent);
Stats::Scalar numDataArrayReads;
Stats::Scalar numDataArrayWrites;
Stats::Scalar numTagArrayReads;
Stats::Scalar numTagArrayWrites;
Stats::Scalar numTagArrayStalls;
Stats::Scalar numDataArrayStalls;
// hardware transactional memory
Stats::Histogram htmTransCommitReadSet;
Stats::Histogram htmTransCommitWriteSet;
Stats::Histogram htmTransAbortReadSet;
Stats::Histogram htmTransAbortWriteSet;
Stats::Scalar m_demand_hits;
Stats::Scalar m_demand_misses;
Stats::Formula m_demand_accesses;
Stats::Scalar m_sw_prefetches;
Stats::Scalar m_hw_prefetches;
Stats::Formula m_prefetches;
Stats::Vector m_accessModeType;
} cacheMemoryStats;
public:
CacheMemoryStats cacheMemoryStats;
Stats::Scalar m_demand_hits;
Stats::Scalar m_demand_misses;
Stats::Formula m_demand_accesses;
Stats::Scalar m_sw_prefetches;
Stats::Scalar m_hw_prefetches;
Stats::Formula m_prefetches;
Stats::Vector m_accessModeType;
// These function increment the number of demand hits/misses by one
// each time they are called
void profileDemandHit();
void profileDemandMiss();
};
std::ostream& operator<<(std::ostream& out, const CacheMemory& obj);