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arch-riscv: fix MIE csr register setting bugs

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Any changes on xIE bits changes should trigger the updating
of CSR register. The old condition is wrongly reversed.

The fix is verified in FS.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-855

Change-Id: Ia2c6d3fbfd24d7f9d23f7cfa6f25f893544f4157
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38578
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Cui Jin
2020-12-22 16:46:46 +08:00
parent 400152d5cb
commit acfb233685
1 changed files with 3 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/arch/riscv/isa/formats/standard.isa
View File

@@ -383,9 +383,9 @@ def template CSRExecute {{
xc->setMiscReg(MISCREG_FRM, bits(data, 7, 5));
break;
case CSR_MIP: case CSR_MIE:
if (oldinterrupt.mei == newinterrupt.mei &&
oldinterrupt.mti == newinterrupt.mti &&
oldinterrupt.msi == newinterrupt.msi) {
if (oldinterrupt.mei != newinterrupt.mei ||
oldinterrupt.mti != newinterrupt.mti ||
oldinterrupt.msi != newinterrupt.msi) {
xc->setMiscReg(CSRData.at(csr).physIndex,data);
} else {
std::string error = "Interrupt m bits are "