arch: Add a mechanism to pad the src or dest reg index arrays.

ARM reaches in and pads out the source register index list behind the
parser's back to force dest regs to also be sources in case an
instruction fails predication and needs to forward the original register
values. It shouldn't be hacking up these values in that way, but since
it is, this will let it continue to do so while still fitting in the new
system where each instruction allocates its src/dest reg index arrays to
size.

Change-Id: Ia296be9f63123f18f6cdc0d3bb1314d33e759b3a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38380
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/isa_parser/isa_parser.py

@@ -107,7 +107,8 @@ class Template(object):
 
             myDict['reg_idx_arr_decl'] = \
                 'RegId srcRegIdxArr[%d]; RegId destRegIdxArr[%d]' % \
-                (d.operands.numSrcRegs, d.operands.numDestRegs)
+                (d.operands.numSrcRegs + d.srcRegIdxPadding,
+                 d.operands.numDestRegs + d.destRegIdxPadding)
 
             # The reinterpret casts are largely because an array with a known
             # size cannot be passed as an argument which is an array with an
@@ -391,6 +392,9 @@ class InstObjParams(object):
 
         self.operands = OperandList(parser, compositeCode)
 
+        self.srcRegIdxPadding = 0
+        self.destRegIdxPadding = 0
+
         # The header of the constructor declares the variables to be used
         # in the body of the constructor.
         header = ''
@@ -464,6 +468,12 @@ class InstObjParams(object):
         else:
             self.fp_enable_check = ''
 
+    def padSrcRegIdx(self, padding):
+        self.srcRegIdxPadding = padding
+
+    def padDestRegIdx(self, padding):
+        self.destRegIdxPadding = padding
+
 
 #######################
 #