This changes the base classes for branch instructions and
switches to two high-level classes for unconditional and
conditional branches. The conditional branches are further
classified based on whether they use an immediate field or
a register for determining the target address.
Decoding has also been consolidated using formats that can
generate code after determining if an instruction branches
to an absolute address or a PC-relative address, or if it
implicitly sets the return address by looking at the AA and
LK bits.
Change-Id: I5fa7db7b6693586b4ea3c71e5cad8a60753de29c
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40886
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
When multiple instructions share the same primary opcode,
the decoder can distinguish between them by looking at the
extended opcode field. However, the length and position of
the extended opcode field can slightly vary depending on
the instruction form.
This ensures that the correct extended opcode fields are
used for decoding such instructions.
Change-Id: I8207568ac975587377abba8a9b221ca3097b8488
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40885
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This adds 64-bit statically linked big and little endian
binaries for the hello test program.
It should be noted that all possible combinations of ABI
version and endianness are possible for 64-bit binaries.
However, standard toolchains always use ELF ABI v1 for
big endian and ELF ABI v2 for little endian binaries.
Change-Id: I2dca7eaa2b04a7b68b117ada799d4c3bb69368be
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40951
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Commit a440108cc ("tests: Add Makefiles for hello")
introduced Makefiles for building the hello test binary
for ARM and x86 using dockcross. Since dockcross also
provides an image with a 64-bit little endian toolchain
for Power, this adds a Makefile for building the hello
binary.
As of this moment, 64-bit little endian (ppc64le) is the
prevalent variant supported by most distributions. Hence,
we are currently limited to only building the binary for
this variant.
Change-Id: Ic20322ca33c69634d9f17d30b29e522cc35742fb
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40949
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Rather than decode and call each PsuedoInst function one by one, we can
use a GuestABI which knows how to marshal arguments and return values
and call the pseudoInst dispatch function which will do the work for us,
and make SPARC able to call any pseudo inst, not just the ones it was
hard coded to recognize.
Change-Id: I28192c4feeaf86a77c0f23c5b131929e45ec6d74
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42388
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Only one is set up corrent, the one passed in from the constructor.
Others can be added with addThreadContext.
The inconsistency of adding one ThreadContext through the constructor
and others through addThreadContext isn't great, but this way we can
ensure that there is always at least one ThreadContext. I'm not sure
what the GDB stub should do if there aren't any threads. I don't think
that the protocol can actually handle that, judging from the
documentation I can find.
Change-Id: I9160c3701ce78dcbbe99de1a6fe2a13e7e69404e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44611
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Distinguish between the 'g' and 'c' subcommands. 'c' sets what thread(s)
should be continued or single stepped when those commands are used, and
'g' sets what thread(s) should be used for anything else. Also, insist
that all threads are used for continuing or single stepping.
Still complain if we're asked to switch threads, since we only have one
and we can't change to anything else.
Change-Id: Ia15c055baba48f75fc29ef369567535b0aa2c76b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44609
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Just because the current methods of the base class only call
Event::trace from within DTRACE(Event), that's no guarantee that future
methods will, that the call sites won't be changed so that they don't,
or any number of subclasses that may not even exist today will.
Instead, we should incur the very slight overhead of checking the
Debug::Event variable again to ensure expected behavior, and to avoid
unnecessary complexity for a very small optimization when we're already
enabled a high overhead behavior like tracing for all events in a
virtual function.
Change-Id: I1c360b2ba73ad73c0658e85e9122f1fef07f93ce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44986
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This is aligning with RISCV and X86. Prior to this patch the Arm
TableWalker was using the TLBVerbose flag. We now use the generic
PageTableWalker flag, in most of the table walker code.
We still rely on the TLBVerbose for some methods.
Those are not conceptually related to the table walker:
For example the memAttrs methods are populating the TLB entry fields
before inserting it in the TLB. Describing the entry fields is
not strictly related to the walking mechanism
Change-Id: Ia75fef052cd44905cc41247f8e590e3ce3912252
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44966
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This is an initial configuration capable of booting Linux and
registering a PCI device which registers as an AMD Vega 10 (Frontier
Edition) GPU. It it loosely based on the the example/fs.py and gem5 book
full system example scripts. The top-level file is meant to be modular
such that convenience scripts can be created to set arguments
automatically and then call the main run function.
This will evolve over time as more full-system GPU components are added
and the network topology needed for disjoint address spaces is created
for the VIPER protocol.
Change-Id: I7002213ca8de5eb73919e49fb11840a688744012
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44907
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
There is a design which has been put forward which eliminates the idea
of a zero register entirely, but in the mean time, to get rid of one
more ISA specific constant, this change moves the ZeroReg constant into
the RegClassInfo class, specifically the IntRegClass instance which is
published by each ISA.
When the idea of zero registers has been eliminated entirely from
non ISA specific code, this and the existing machinery can be
eliminated.
Change-Id: I4302a53220dd5ff6b9b47ecc765bddc6698310ca
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42685
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gem5 defines several types of memory access including normal read,
normal write, atomic operations. For now we only support normal read
and normal write converting from SystemC via TLM2. To support atomic
operations from SystemC, we add an atomic extension. A SystemC model can
fire a atomic request with the extension.
The extension mainly has two attributes. One is a AtomicOpFunctor which
is the implementation of the atomic operation. The other one is bool
which indicates the gem5 request flag should be ATOMIC_RETURN_OP or
ATOMIC_NO_RETURN_OP.
Change-Id: I817727dd4b2d357667f928063210c58a44c81afb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44525
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
The prior example config for FS fails SMP boot on the KVMX86CPU.
These updates incorporate logic x86-boot-tests/system/
[system.py|run_exit.py] as well as configs/example/arm/
fs_bigLITTLE.py to enable both single processor and SMP boot.
Each KVM VM now uses its own eventq and a non-zero sim_quantum.
Change-Id: I9c73a2f6f2ca604aecd31f45570423c58f85020f
Signed-off-by: Kevin Loughlin <kevlough@umich.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41602
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The GPU VIPER TCC protocol accidentally used "TiggerMsg" instead
of "TriggerMsg" for the triggerQueue_in port. This was a benign
bug beacuse the msg type is not used in the in_port implementation
but still makes the SLICC harder to understand, so fixing it is
worthwhile.
Change-Id: I88cbc72bac93bcc58a66f057a32f7bddf821cac9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44905
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Previously the pyunit tests needed run in the gem5 root, this change
allows them to run as part of the quick TestLib tests (thereby having
them run as part of the presubmit checks). This runs all the TestLib
tests as a single test using the NULL gem5 binary.
`tests/run_pyunit.py` has been updated to only parse files with the
`pyunit` prefix in their filname. As such `pyunit/util/test_convert.py`
has been renamed `pyunit/util/pyunit_convert_check.py`. The word `test`
has been removed entirely as to not clash with the testlib tests as run
by `tests/main.py`.
Example usage:
```
./main.py run --uid SuiteUID:tests/pyunit/test_run.py:pyunit-tests-NULL-x86_64-opt
```
Discussed briefly in email thread:
https://www.mail-archive.com/gem5-dev@gem5.org/msg38563.html
Change-Id: Id566d44fcb5d8c599eb1a90bca56793158a201e6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44625
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Viper is checking for the dma's type before making the port assignment.
In FullSystem mode the IDE device is a PortRef and does not have an
attribute 'type.' This handles the various types a bit better and
ensures that IDE device, the protocol tester, and upcoming DMA devices
related to FullSystem can be added.
Change-Id: I6879b25c6aabbbc22b0ee8dc9cbfec6399f70daa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44806
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The arch/generic/types.hh header includes some more complicated types
which in turn bring in more dependencies, adding baggage when other code
only needs the simple RegIndex or ElemIndex types. Also the RegVal type
alias is already in base/types.hh. It doesn't really make sense to have
RegVal in one header and RegIndex in another.
Change-Id: I1360652598b5fa59e0632b1ee0e0535ace2ba563
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42966
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
GPUCoalescers in FullSystem mode should not be connected to the piobus
since they reside on a completely different RubyPort. There is also no
concept of IO requests from GPU so any request attempting to use the
default port (pio) should fatal. Further, coalescers do not implement
the connectIOPorts function.
This avoids coalescers by checking is_cpu_sequencer, which I believe is
the purpose of that boolean.
Change-Id: I482dd631292ca20e3bcd856489376f9b38457200
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44805
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit id ef44dc9a removed mmap-based doorbell allocation since dGPUs
use ioctl's instead. However, APUs still need this to work correctly.
Add that logic back in as well as some new logic to distinguish doorbells
mmaps from other types. Also add some additional commentary regarding
Event page mmaps.
Change-Id: I8507ac85c8f07886d0fb4f95bde5e18a7790eab8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42218
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
GPU MTYPE is currently set using a global config passed to the
PACoalescer. This patch enables MTYPE to be set by the shader on a
per-request bases. In real hardware, the MTYPE is extracted from a
GPUVM PTE during address translation. However, our current simulator
only models x86 page tables which do not have the appropriate bits for
GPU MTYPES. Rather than hacking non-x86 bits into our x86 page table
models, this patch instead keeps an interval tree of all pages that
request custom MTYPES in the driver itself. This is currently
only used to map host pages to the GPU as uncacheable, but is easily
extensible to other MTYPES.
Change-Id: I7daab0ffae42084b9131a67c85cd0aa4bbbfc8d6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42216
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
dev/ has unit tests, but they are not run when
using the NULL ISA. The currently existing tests
are not ISA-specific, so the tests were set to
be run at an ARM environment.
As of now this is enough, but when ISA-specific
tests from ISAs other than ARM are added one will
need to change to cover them too.
Change-Id: I18df0141d415286325463afa759459b04ac8a92f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44367
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
There was a merge error caused by new options being added to this script
while all scripts were being converted from optparse. This fixes the
error.
This also removes the mostly unused setOption / getOption as you can
directly assign a value to an argument after parsing
Change-Id: Ic8aaa0728a43936cd4c6e1ed590e01ba5f0fbf5b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44785
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
