454cb00ddb
Refactor: remove monolithic configuration class
2024-02-23 11:54:51 +01:00
6645a9ed54
Introduce method to convert memspecs to DRAMPower memspecs and cleanup source files
2023-11-14 14:57:25 +01:00
Lukas Steiner
8224e97abe
Reformat all files.
2023-09-21 16:50:59 +02:00
c07d09f392
Format all files
2023-08-29 09:26:25 +02:00
Lukas Steiner
12f2b73cde
Additional check of byte enable pointer.
2023-08-23 15:21:53 +02:00
Lukas Steiner
76e58b1755
Fix renaming.
2023-08-23 13:50:10 +02:00
Lukas Steiner
0f824e8b92
Do not allow masked write in default case.
2023-08-23 11:41:58 +02:00
4548d20b6e
Rename requiresMaskedWrite to requiresReadModifyWrite
2023-08-21 10:55:41 +02:00
c5f1320399
Implement Partial Write for DDR5
2023-08-16 09:38:57 +02:00
40dbc518b6
Add hack in TimingCheckers to convert MWR to WR in insertion stage
2023-08-16 09:38:54 +02:00
f7066a22b0
First implementation of Partial Writes
2023-08-16 09:38:54 +02:00
Lukas Steiner
12dcbfd917
Use scoped enums for DRAM types.
2023-06-30 15:49:41 +02:00
Lukas Steiner
ba3f367676
Use type safe index vectors in timing checkers (2/2).
2023-06-21 12:59:26 +02:00
Lukas Steiner
20f6aae787
Replace tabs with whitespaces.
2023-05-25 16:09:55 +02:00
Lukas Steiner
b3955d6d02
Update TUK to RPTU.
2023-05-25 15:15:52 +02:00
69cd04c448
Namespace the complete DRAMSys library
2023-05-17 11:42:00 +02:00
85f944fe58
Rename RAACDR to RAADEC
2023-04-21 11:10:09 +02:00
Lukas Steiner
9a1443835d
Merge branch 'develop' into wip/unit_test_preps
...
# Conflicts:
# extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp
2023-04-14 11:35:32 +02:00
Lukas Steiner
9b31fef555
Use local copies of sc_max_time() instead of calling the function.
2023-04-14 10:03:59 +02:00
d27a29ca80
Refactor configuration library
...
The configuration library has been refactored to make use of nlohmann
macros to reduce boilerplate code.
The nlohmann parser callback is used to decide whether to include
configuration json objects directly, or if they need to be loaded
from a sperate file.
2023-04-13 11:18:39 +02:00
Lukas Steiner
5f1c74790b
Remove duplicate checks in DDR5 checker.
2023-04-12 13:45:44 +00:00
507c1d32d6
Update tCCD_L_WR, tCCD_L_WR2 and tCCD_M_WR timings in DDR5 timing checker
2023-04-12 09:40:18 +02:00
60b2bcbffa
Fix DDR5 write-to-write delay in TimingChecker
2023-04-11 14:08:32 +02:00
49954df6ee
Add tCCD_M DDR5 timings, MemSpecs still incomplete
2023-04-06 10:38:48 +02:00
Lukas Steiner
1bd6d61d23
Adapt more paths.
2023-02-22 15:18:17 +01:00
Thomas Psota
f434026ccd
Added extension mechanism and ported DDR5, LPDDR5, HBM3, TraceAnalyzer
2023-02-09 14:22:34 +01:00
