Lukas Steiner
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8f45b7683b
|
Test: coverage only for library and simulator.
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2020-07-03 14:45:51 +02:00 |
|
Lukas Steiner
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f0a5f07345
|
Rename TUK, add missing disclaimers.
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2020-07-03 14:20:48 +02:00 |
|
Lukas Steiner
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03e27090a3
|
Updates gem5 readme.
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2020-07-03 10:28:06 +02:00 |
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Lukas Steiner
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3a03119d78
|
Merge branch 'readme_updates2' into 'development'
Readme updates.
See merge request ems/astdm/dram.sys!257
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2020-07-02 15:22:45 +02:00 |
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Lukas Steiner
|
7b4aeaf663
|
Remove old tests.
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2020-07-02 15:07:29 +02:00 |
|
Lukas Steiner
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88821a2216
|
Merge branch 'ci_tests' into readme_updates2
# Conflicts:
# DRAMSys/tests/HBM2/configs/mcconfigs/fifoStrict.json
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2020-07-02 14:58:58 +02:00 |
|
scorrea
|
c762540d37
|
dummy refresh manager test
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2020-07-02 14:15:42 +02:00 |
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Lukas Steiner
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8dd4f3f702
|
Merge branch 'ci_tests' into 'development'
Include new CI for DRAMSys4.0 on KOA
See merge request ems/astdm/dram.sys!256
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2020-07-02 14:08:38 +02:00 |
|
scorrea
|
aca89f7a07
|
power analysis enabled for ddr3 and ddr4
|
2020-07-02 12:38:47 +02:00 |
|
Lukas Steiner
|
7dad1da564
|
One stage for tests in CI.
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2020-07-02 11:51:47 +02:00 |
|
Lukas Steiner
|
603f9b6bdd
|
Move refresh mode to DDR4 memspec.
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2020-07-02 11:28:44 +02:00 |
|
Lukas Steiner
|
74c219ebdc
|
Update image paths.
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2020-07-01 16:55:47 +02:00 |
|
Lukas Steiner
|
92c32fdf15
|
Removed old images of readme.
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2020-07-01 16:31:01 +02:00 |
|
Lukas Steiner
|
3d3c9c2799
|
Update resources.
|
2020-07-01 16:11:52 +02:00 |
|
Lukas Steiner
|
b52cabf21a
|
Readme updates, separate gem5 readme.
|
2020-07-01 15:41:20 +02:00 |
|
scorrea
|
56fa53b784
|
export COVERAGE=true
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2020-06-30 19:34:47 +02:00 |
|
scorrea
|
072ae5960c
|
html files removed
|
2020-06-30 17:44:57 +02:00 |
|
scorrea
|
e98e1c49aa
|
html removed
|
2020-06-30 17:42:08 +02:00 |
|
scorrea
|
f0d3a081c8
|
.gitlab-ci.yml back to older version
|
2020-06-30 17:07:51 +02:00 |
|
scorrea
|
6e8ea831c6
|
removed base.out before coverage eval
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2020-06-30 16:12:48 +02:00 |
|
scorrea
|
153d68dee8
|
base file removed
|
2020-06-30 15:58:23 +02:00 |
|
scorrea
|
5db27a8b17
|
undone changes to cov test
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2020-06-30 12:59:24 +02:00 |
|
scorrea
|
cdb1693687
|
Merge branch 'ci_tests' of https://git.eit.uni-kl.de/ems/astdm/dram.sys into ci_tests
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2020-06-30 12:34:46 +02:00 |
|
scorrea
|
9241689b99
|
cov test updated
|
2020-06-30 12:33:12 +02:00 |
|
Lukas Steiner
|
117937f4aa
|
Includes flag for coverage build.
|
2020-06-30 11:15:46 +02:00 |
|
scorrea
|
066f22c798
|
cov path modified
|
2020-06-26 15:56:22 +02:00 |
|
scorrea
|
bc8f2aaeca
|
ci build and path updated4
|
2020-06-26 11:44:10 +02:00 |
|
scorrea
|
c97c3b87f6
|
ci build and path updated3
|
2020-06-26 11:34:35 +02:00 |
|
scorrea
|
79574c83ec
|
ci build and path updated2
|
2020-06-26 11:31:55 +02:00 |
|
scorrea
|
3c00374d39
|
ci build and path updated
|
2020-06-26 11:29:22 +02:00 |
|
scorrea
|
1751e0c6cd
|
ci build and path updated
|
2020-06-26 11:22:53 +02:00 |
|
scorrea
|
416b1bbcc7
|
coverage added to CMakelists
|
2020-06-26 09:43:13 +02:00 |
|
scorrea
|
5a75a62760
|
coverage flags changed
|
2020-06-24 18:35:50 +02:00 |
|
scorrea
|
8ed64a85cf
|
--coverage option
|
2020-06-24 18:05:01 +02:00 |
|
scorrea
|
542a7d9f32
|
gcov option passed to GCC
|
2020-06-24 17:53:56 +02:00 |
|
scorrea
|
2e5483e122
|
ddr3 ci.yml file corrected
|
2020-06-24 16:15:43 +02:00 |
|
scorrea
|
4cf1f2c0b4
|
.tdb in expected folders excluded from gitignore
|
2020-06-23 12:07:02 +02:00 |
|
scorrea
|
26c2c7f66f
|
HBM2 ci.yml correction
|
2020-06-23 11:45:54 +02:00 |
|
scorrea
|
c016959d50
|
traceAnalyzer tests excluded from ci tests
|
2020-06-23 11:09:17 +02:00 |
|
scorrea
|
54f3285b17
|
HBM2 test to dual-channel/ DDR2 memspecs updated
|
2020-06-20 16:12:35 +02:00 |
|
scorrea
|
81c67fb1d3
|
NumberOfMemChannels to nbrOfChannels
|
2020-06-18 15:45:27 +02:00 |
|
scorrea
|
5cbfa36339
|
PAGE POLICIES AND TRACES MODIFIED
|
2020-06-18 12:39:50 +02:00 |
|
scorrea
|
295810ac1b
|
ci tests traces and memspec modified
|
2020-06-18 10:40:37 +02:00 |
|
Lukas Steiner
|
b5eaf936ac
|
Merge branch 'refb_multicycle_fix' into ci_tests
# Conflicts:
# DRAMSys/tests/DDR4/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json
# DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json
# DRAMSys/tests/ddr4_bankgroups/configs/simulator/ddr4.json
# DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json
|
2020-06-16 13:43:14 +02:00 |
|
Lukas Steiner
|
5f57c29224
|
Per-bank refresh fix.
|
2020-06-16 13:24:20 +02:00 |
|
scorrea
|
ab206aa688
|
ci.yml edited
|
2020-06-16 11:50:11 +02:00 |
|
scorrea
|
b2b70d3771
|
ci and test files modified/some old tests deleted
|
2020-06-16 11:25:49 +02:00 |
|
Lukas Steiner
|
4265ecc3c7
|
Adapted memspecs to nbrOfChannels and nbrOfDevicesOnDIMM.
|
2020-06-16 10:53:43 +02:00 |
|
scorrea
|
a3592e15ba
|
Nr of channel and devices per DIMM at memspec file
|
2020-06-15 18:24:16 +02:00 |
|
scorrea
|
3f8f12358b
|
new test files
|
2020-06-10 12:32:20 +02:00 |
|