Adapted memspecs to nbrOfChannels and nbrOfDevicesOnDIMM.

2020-06-16 10:53:43 +02:00
parent a3592e15ba
commit 4265ecc3c7
24 changed files with 70 additions and 42 deletions
--- a/DRAMSys/library/CMakeLists.txt
+++ b/DRAMSys/library/CMakeLists.txt
@@ -172,6 +172,7 @@ add_library(DRAMSysLibrary
    resources/simulations/lpddr4-example.json
    resources/simulations/ranktest.json
    resources/simulations/wideio-example.json
+    resources/simulations/wideio-thermal.json

    # Address Mapping Config Files
    resources/configs/amconfigs/am_ddr3_1Gbx8_p1KB_brc.json
@@ -266,9 +267,11 @@ add_library(DRAMSysLibrary
    resources/configs/simulator/hbm2.json
    resources/configs/simulator/lpddr4.json
    resources/configs/simulator/wideio.json
+    resources/configs/simulator/wideio_thermal.json

    # Thermal Simulation Config Files
    resources/configs/thermalsim/config.json
+    resources/configs/thermalsim/powerInfo.json

    # Trace Files
    resources/traces/test_ecc.stl
--- a/DRAMSys/library/src/common/AddressDecoder.cpp
+++ b/DRAMSys/library/src/common/AddressDecoder.cpp
@@ -143,7 +143,7 @@ AddressDecoder::AddressDecoder(std::string pathToAddressMapping)
    Configuration &config = Configuration::getInstance();
    MemSpec *memSpec = config.memSpec;

-    if (memSpec->numberOfMemChannels != channels || memSpec->numberOfRanks != ranks
+    if (memSpec->numberOfChannels != channels || memSpec->numberOfRanks != ranks
            || memSpec->numberOfBankGroups != bankgroups || memSpec->numberOfBanks != banks
            || memSpec->numberOfRows != rows || memSpec->numberOfColumns != columns
            || memSpec->numberOfDevicesOnDIMM * memSpec->bitWidth != bytes * 8)
--- a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp
@@ -43,29 +43,29 @@
 using namespace tlm;
 using json = nlohmann::json;

-MemSpec::MemSpec(json &memspec, unsigned numberOfRanks, unsigned banksPerRank,
+MemSpec::MemSpec(json &memspec, unsigned numberOfChannels,
+                 unsigned numberOfRanks, unsigned banksPerRank,
                 unsigned groupsPerRank, unsigned banksPerGroup,
-                 unsigned numberOfBanks, unsigned numberOfBankGroups)
-    : numberOfRanks(numberOfRanks),
+                 unsigned numberOfBanks, unsigned numberOfBankGroups,
+                 unsigned numberOfDevicesOnDIMM)
+    : numberOfChannels(numberOfChannels),
+      numberOfRanks(numberOfRanks),
      banksPerRank(banksPerRank),
      groupsPerRank(groupsPerRank),
      banksPerGroup(banksPerGroup),
      numberOfBanks(numberOfBanks),
      numberOfBankGroups(numberOfBankGroups),
+      numberOfDevicesOnDIMM(numberOfDevicesOnDIMM),
      numberOfRows(parseUint(memspec["memarchitecturespec"]["nbrOfRows"],"nbrOfRows")),
      numberOfColumns(parseUint(memspec["memarchitecturespec"]["nbrOfColumns"],"nbrOfColumns")),
      burstLength(parseUint(memspec["memarchitecturespec"]["burstLength"],"burstLength")),
      dataRate(parseUint(memspec["memarchitecturespec"]["dataRate"],"dataRate")),
      bitWidth(parseUint(memspec["memarchitecturespec"]["width"],"width")),
      fCKMHz(parseUdouble(memspec["memtimingspec"]["clkMhz"], "clkMhz")),
-      numberOfDevicesOnDIMM(parseUint(memspec["memarchitecturespec"]["NumberOfDevicesOnDIMM"],
-                                                                    "numberOfDevicesOnDIMM")),
-      numberOfMemChannels(parseUint(memspec["memarchitecturespec"]["NumberOfMemChannels"],
-                                                                    "NumberOfMemChannels")),
      tCK(sc_time(1.0 / fCKMHz, SC_US)),
-      burstDuration(tCK * (burstLength / dataRate)),
      memoryId(parseString(memspec["memoryId"], "memoryId")),
-      memoryType(parseString(memspec["memoryType"], "memoryType"))
+      memoryType(parseString(memspec["memoryType"], "memoryType")),
+      burstDuration(tCK * (burstLength / dataRate))
 {
    commandLengthInCycles = std::vector<unsigned>(numberOfCommands(), 1);
 }
--- a/DRAMSys/library/src/configuration/memspec/MemSpec.h
+++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h
@@ -48,19 +48,19 @@
 class MemSpec
 {
 public:
+    unsigned numberOfChannels;
    unsigned numberOfRanks;
    unsigned banksPerRank;
    unsigned groupsPerRank;
    unsigned banksPerGroup;
    unsigned numberOfBanks;
    unsigned numberOfBankGroups;
+    unsigned numberOfDevicesOnDIMM;
    unsigned numberOfRows;
    unsigned numberOfColumns;
    unsigned burstLength;
    unsigned dataRate;
    unsigned bitWidth;
-    unsigned int numberOfDevicesOnDIMM;
-    unsigned int numberOfMemChannels;

    // Clock
    double fCKMHz;
@@ -80,9 +80,11 @@ public:
    sc_time getCommandLength(Command) const;

 protected:
-    MemSpec(nlohmann::json &memspec, unsigned numberOfRanks, unsigned banksPerRank,
+    MemSpec(nlohmann::json &memspec, unsigned numberOfChannels,
+            unsigned numberOfRanks, unsigned banksPerRank,
            unsigned groupsPerRank, unsigned banksPerGroup,
-            unsigned numberOfBanks, unsigned numberOfBankGroups);
+            unsigned numberOfBanks, unsigned numberOfBankGroups,
+            unsigned numberOfDevicesOnDIMM);

    // Command lengths in cycles on bus, usually one clock cycle
    std::vector<unsigned> commandLengthInCycles;
--- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp
@@ -40,13 +40,15 @@ using json = nlohmann::json;

 MemSpecDDR3::MemSpecDDR3(json &memspec)
    : MemSpec(memspec,
+      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
      1,
      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
+      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"]["nbrOfDevicesOnDIMM"],"nbrOfDevicesOnDIMM")),
      tCKE     (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
      tPD      (tCKE),
      tCKESR   (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")),
--- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp
@@ -41,6 +41,7 @@ using json = nlohmann::json;

 MemSpecDDR4::MemSpecDDR4(json &memspec)
    : MemSpec(memspec,
+      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
      parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
@@ -49,7 +50,8 @@ MemSpecDDR4::MemSpecDDR4(json &memspec)
      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
      parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups")
-          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
+          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"]["nbrOfDevicesOnDIMM"],"nbrOfDevicesOnDIMM")),
      tCKE     (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
      tPD      (tCKE),
      tCKESR   (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")),
--- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp
@@ -40,6 +40,7 @@ using json = nlohmann::json;

 MemSpecGDDR5::MemSpecGDDR5(json &memspec)
    : MemSpec(memspec,
+      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
      parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
@@ -48,7 +49,8 @@ MemSpecGDDR5::MemSpecGDDR5(json &memspec)
      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
      parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups")
-          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
+          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
+      1),
      tRP        (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
      tRAS       (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
      tRC        (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),
--- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp
@@ -40,6 +40,7 @@ using json = nlohmann::json;

 MemSpecGDDR5X::MemSpecGDDR5X(json &memspec)
    : MemSpec(memspec,
+      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
      parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
@@ -48,7 +49,8 @@ MemSpecGDDR5X::MemSpecGDDR5X(json &memspec)
      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
      parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups")
-          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
+          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
+      1),
      tRP        (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
      tRAS       (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
      tRC        (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),
--- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp
@@ -40,6 +40,7 @@ using json = nlohmann::json;

 MemSpecGDDR6::MemSpecGDDR6(json &memspec)
    : MemSpec(memspec,
+      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
      parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
@@ -48,7 +49,8 @@ MemSpecGDDR6::MemSpecGDDR6(json &memspec)
      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
      parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups")
-          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
+          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
+      1),
      tRP        (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
      tRAS       (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
      tRC        (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),
--- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp
@@ -40,6 +40,7 @@ using json = nlohmann::json;

 MemSpecHBM2::MemSpecHBM2(json &memspec)
    : MemSpec(memspec,
+      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
      parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
@@ -48,7 +49,8 @@ MemSpecHBM2::MemSpecHBM2(json &memspec)
      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
      parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups")
-          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
+          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
+      1),
      tDQSCK  (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")),
      tRC     (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),
      tRAS    (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
--- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp
@@ -40,13 +40,15 @@ using json = nlohmann::json;

 MemSpecLPDDR4::MemSpecLPDDR4(json &memspec)
    : MemSpec(memspec,
+      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
      1,
      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
+      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
+      1),
      tREFI   (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")),
      tREFIpb (tCK * parseUint(memspec["memtimingspec"]["REFIPB"], "REFIPB")),
      tRFCab  (tCK * parseUint(memspec["memtimingspec"]["RFCAB"], "RFCAB")),
--- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp
@@ -40,13 +40,15 @@ using json = nlohmann::json;

 MemSpecWideIO::MemSpecWideIO(json &memspec)
    : MemSpec(memspec,
+      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
      1,
      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
+      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
+      1),
      tCKE    (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
      tCKESR  (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")),
      tDQSCK  (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")),
--- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp
@@ -40,13 +40,15 @@ using json = nlohmann::json;

 MemSpecWideIO2::MemSpecWideIO2(json &memspec)
    : MemSpec(memspec,
+      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
      1,
      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
+      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
+      1),
      tDQSCK  (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")),
      tDQSS   (tCK * parseUint(memspec["memtimingspec"]["DQSS"], "DQSS")),
      tCKE    (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
--- a/DRAMSys/library/src/simulation/Arbiter.cpp
+++ b/DRAMSys/library/src/simulation/Arbiter.cpp
@@ -49,7 +49,7 @@ Arbiter::Arbiter(sc_module_name name, std::string pathToAddressMapping) :
    // Anytime an transaction comes from a memory unity to the arbiter the "bw" callback is called.
    iSocket.register_nb_transport_bw(this, &Arbiter::nb_transport_bw);

-    for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; ++i)
+    for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; ++i)
    {
        channelIsFree.push_back(true);
        pendingRequests.push_back(std::queue<tlm_generic_payload *>());
@@ -130,7 +130,7 @@ void Arbiter::peqCallback(tlm_generic_payload &payload, const tlm_phase &phase)

    // Check the valid range of thread ID and channel Id
    // TODO: thread ID not checked
-    assert(channelId < Configuration::getInstance().memSpec->numberOfMemChannels);
+    assert(channelId < Configuration::getInstance().memSpec->numberOfChannels);

    // Phases initiated by the intiator side from arbiter's point of view (devices performing memory requests to the arbiter)
    if (phase == BEGIN_REQ)
--- a/DRAMSys/library/src/simulation/DRAMSys.cpp
+++ b/DRAMSys/library/src/simulation/DRAMSys.cpp
@@ -192,7 +192,7 @@ void DRAMSys::instantiateModules(const std::string &pathToResources,

    // Create controllers and DRAMs
    std::string memoryType = Configuration::getInstance().memSpec->memoryType;
-    for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++)
+    for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++)
    {
        std::string str = "controller" + std::to_string(i);

@@ -251,7 +251,7 @@ void DRAMSys::bindSockets()

    if (Configuration::getInstance().checkTLM2Protocol)
    {
-        for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++)
+        for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++)
        {
            arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket);
            controllersTlmCheckers[i]->initiator_socket.bind(controllers[i]->tSocket);
@@ -260,7 +260,7 @@ void DRAMSys::bindSockets()
    }
    else
    {
-        for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++)
+        for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++)
        {
            arbiter->iSocket.bind(controllers[i]->tSocket);
            controllers[i]->iSocket.bind(drams[i]->tSocket);
--- a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp
+++ b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp
@@ -91,7 +91,7 @@ void DRAMSysRecordable::setupTlmRecorders(const std::string &traceName,
                                          const std::string &pathToResources)
 {
    // Create TLM Recorders, one per channel.
-    for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++)
+    for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++)
    {
        std::string sqlScriptURI = pathToResources
                                   + std::string("scripts/createTraceDB.sql");
@@ -140,7 +140,7 @@ void DRAMSysRecordable::instantiateModules(const std::string &traceName,

    // Create controllers and DRAMs
    std::string memoryType = Configuration::getInstance().memSpec->memoryType;
-    for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++)
+    for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++)
    {
        std::string str = "controller" + std::to_string(i);

@@ -199,7 +199,7 @@ void DRAMSysRecordable::bindSockets()

    if (Configuration::getInstance().checkTLM2Protocol)
    {
-        for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++)
+        for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++)
        {
            arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket);
            controllersTlmCheckers[i]->initiator_socket.bind(controllers[i]->tSocket);
@@ -208,7 +208,7 @@ void DRAMSysRecordable::bindSockets()
    }
    else
    {
-        for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++)
+        for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++)
        {
            arbiter->iSocket.bind(controllers[i]->tSocket);
            controllers[i]->iSocket.bind(drams[i]->tSocket);
--- a/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json
+++ b/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json
@@ -7,6 +7,7 @@
            "nbrOfBanks": 16,
            "nbrOfColumns": 128,
            "nbrOfRanks": 2,
+            "nbrOfChannels": 1,
            "nbrOfRows": 32768,
            "width": 64
        },
--- a/DRAMSys/tests/HBM2/configs/simulator/hbm2.json
+++ b/DRAMSys/tests/HBM2/configs/simulator/hbm2.json
@@ -8,8 +8,6 @@
        "EnableWindowing": false,
        "ErrorCSVFile": "",
        "ErrorChipSeed": 42,
-        "NumberOfDevicesOnDIMM": 1,
-        "NumberOfMemChannels": 1,
        "PowerAnalysis": false,
        "SimulationName": "hbm2",
        "SimulationProgressBar": true,
--- a/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json
+++ b/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json
@@ -6,8 +6,10 @@
            "nbrOfBanks": 8,
            "nbrOfColumns": 1024,
            "nbrOfRanks": 2,
+            "nbrOfChannels": 1,
            "nbrOfRows": 16384,
-            "width": 8
+            "width": 8,
+            "nbrOfDevicesOnDIMM": 8
        },
        "memoryId": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM",
        "memoryType": "DDR3",
@@ -49,6 +51,10 @@
            "XPDLL": 13,
            "XS": 64,
            "XSDLL": 512,
+            "ACTPDEN": 1,
+            "PRPDEN": 1,
+            "REFPDEN": 1,
+            "RTRS": 1,
            "clkMhz": 533
        }
    }
--- a/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json
+++ b/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json
@@ -8,8 +8,6 @@
        "EnableWindowing": false,
        "ErrorCSVFile": "",
        "ErrorChipSeed": 42,
-        "NumberOfDevicesOnDIMM": 8,
-        "NumberOfMemChannels": 1,
        "PowerAnalysis": false,
        "SimulationName": "ddr3",
        "SimulationProgressBar": true,
--- a/DRAMSys/tests/ddr4_bankgroups/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json
+++ b/DRAMSys/tests/ddr4_bankgroups/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json
@@ -7,8 +7,10 @@
            "nbrOfBanks": 16,
            "nbrOfColumns": 1024,
            "nbrOfRanks": 1,
+            "nbrOfChannels": 1,
            "nbrOfRows": 32768,
-            "width": 8
+            "width": 8,
+            "nbrOfDevicesOnDIMM": 8
        },
        "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A",
        "memoryType": "DDR4",
--- a/DRAMSys/tests/ddr4_bankgroups/configs/simulator/ddr4.json
+++ b/DRAMSys/tests/ddr4_bankgroups/configs/simulator/ddr4.json
@@ -8,8 +8,6 @@
        "EnableWindowing": false,
        "ErrorCSVFile": "",
        "ErrorChipSeed": 42,
-        "NumberOfDevicesOnDIMM": 8,
-        "NumberOfMemChannels": 1,
        "PowerAnalysis": false,
        "SimulationName": "ddr4",
        "SimulationProgressBar": true,
--- a/DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json
+++ b/DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json
@@ -6,6 +6,7 @@
            "nbrOfBanks": 8,
            "nbrOfColumns": 1024,
            "nbrOfRanks": 1,
+            "nbrOfChannels": 1,
            "nbrOfRows": 65536,
            "width": 16
        },
@@ -30,6 +31,8 @@
            "RL": 28,
            "RPAB": 34,
            "RPPB": 29,
+            "RCAB": 102,
+            "RCPB": 97,
            "RPST": 0,
            "RRD": 16,
            "RTP": 12,
@@ -40,6 +43,7 @@
            "WTR": 16,
            "XP": 12,
            "XSR": 460,
+            "RTRS": 1,
            "clkMhz": 1600
        }
    }
--- a/DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json
+++ b/DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json
@@ -8,8 +8,6 @@
        "EnableWindowing": false,
        "ErrorCSVFile": "",
        "ErrorChipSeed": 42,
-        "NumberOfDevicesOnDIMM": 1,
-        "NumberOfMemChannels": 1,
        "PowerAnalysis": false,
        "SimulationName": "lpddr4",
        "SimulationProgressBar": true,