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This commit is contained in:
scorrea
2020-06-10 12:32:20 +02:00
parent 84f492c910
commit 3f8f12358b
44 changed files with 1552 additions and 0 deletions
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46
DRAMSys/tests/HBM2/configs/amconfigs/am_hbm2_8Gb_pc_brc.json Normal file
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{
"CONGEN": {
"RANK_BIT":[
29
],
"BANKGROUP_BIT":[
27,
28
],
"BANK_BIT": [
25,
26
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9
],
"ROW_BIT": [
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24
]
}
}

11
DRAMSys/tests/HBM2/configs/mcconfigs/fifoStrict.json Normal file
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{"mcconfig": {"PagePolicy": "Closed",
"Scheduler": "Fifo",
"RequestBufferSize": 8,
"CmdMux": "Strict",
"RespQueue": "Fifo",
"RefreshPolicy": "Rankwise",
"RefreshMode": 1,
"RefreshMaxPostponed": 0,
"RefreshMaxPulledin": 0,
"PowerDownPolicy": "NoPowerDown",
"PowerDownTimeout": 100}}

46
DRAMSys/tests/HBM2/configs/memspecs/HBM2.json Normal file
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{
"memspec": {
"memarchitecturespec": {
"burstLength": 4,
"dataRate": 2,
"nbrOfBankGroups": 4,
"nbrOfBanks": 16,
"nbrOfColumns": 128,
"nbrOfRanks": 2,
"nbrOfRows": 32768,
"width": 64
},
"memoryId": "https://www.computerbase.de/2019-05/amd-memory-tweak-vram-oc/#bilder",
"memoryType": "HBM2",
"memtimingspec": {
"CCDL": 3,
"CCDS": 2,
"CKE": 8,
"DQSCK": 1,
"FAW": 16,
"PL": 0,
"RAS": 28,
"RC": 42,
"RCDRD": 12,
"RCDWR": 6,
"REFI": 3900,
"REFISB": 244,
"RFC": 220,
"RFCSB": 96,
"RL": 17,
"RP": 14,
"RRDL": 6,
"RRDS": 4,
"RREFD": 8,
"RTP": 5,
"RTW": 18,
"WL": 7,
"WR": 14,
"WTRL": 9,
"WTRS": 4,
"XP": 8,
"XS": 216,
"clkMhz": 1000
}
}
}

21
DRAMSys/tests/HBM2/configs/simulator/hbm2.json Normal file
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{
"simconfig": {
"AddressOffset": 0,
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"Debug": false,
"ECCControllerMode": "Disabled",
"EnableWindowing": false,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": 1,
"NumberOfMemChannels": 1,
"PowerAnalysis": false,
"SimulationName": "hbm2",
"SimulationProgressBar": true,
"StoreMode": "NoStorage",
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

15
DRAMSys/tests/HBM2/configs/thermalsim/config.json Normal file
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{
"thermalsimconfig": {
"TemperatureScale": "Celsius",
"StaticTemperatureDefaultValue": 89,
"ThermalSimPeriod":100,
"ThermalSimUnit":"us",
"PowerInfoFile": "powerInfo.json",
"IceServerIp": "127.0.0.1",
"IceServerPort": 11880,
"SimPeriodAdjustFactor" : 10,
"NPowStableCyclesToIncreasePeriod": 5,
"GenerateTemperatureMap": true,
"GeneratePowerMap": true
}
}

45
DRAMSys/tests/HBM2/configs/thermalsim/core.flp Executable file
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CPUs :
position 0, 0 ;
dimension 2750, 4300 ;
GPU :
position 3350, 0 ;
dimension 2750, 4000 ;
BASEBAND1 :
position 4250, 4000 ;
dimension 1850, 3300 ;
BASEBAND2 :
position 3350, 7300 ;
dimension 2750, 3300 ;
LLCACHE :
position 0, 4300 ;
dimension 1900, 3000 ;
DRAMCTRL1 :
position 1900, 4300 ;
dimension 850, 3000 ;
DRAMCTRL2 :
position 3350, 4000 ;
dimension 900, 3300 ;
TSVS :
position 2750, 2300 ;
dimension 600, 6000 ;
ACELLERATORS :
position 0, 7300 ;
dimension 2750, 3300 ;

16
DRAMSys/tests/HBM2/configs/thermalsim/mem.flp Executable file
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channel0 :
position 150, 100 ;
dimension 2600, 5200 ;
channel1 :
position 3350, 100 ;
dimension 2600, 5200 ;
channel2 :
position 150, 5300 ;
dimension 2600, 5200 ;
channel3 :
position 3350, 5300 ;
dimension 2600, 5200 ;

20
DRAMSys/tests/HBM2/configs/thermalsim/powerInfo.json Normal file
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{
"powerInfo": {
"dram_die_channel0": {
"init_pow": 0,
"threshold": 1.0
},
"dram_die_channel1": {
"init_pow": 0,
"threshold": 1.0
},
"dram_die_channel2": {
"init_pow": 0,
"threshold": 1.0
},
"dram_die_channel3": {
"init_pow": 0,
"threshold": 1.0
}
}
}

49
DRAMSys/tests/HBM2/configs/thermalsim/stack.stk Executable file
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material SILICON :
thermal conductivity 1.30e-4 ;
volumetric heat capacity 1.628e-12 ;
material BEOL :
thermal conductivity 2.25e-6 ;
volumetric heat capacity 2.175e-12 ;
material COPPER :
thermal conductivity 4.01e-04 ;
volumetric heat capacity 3.37e-12 ;
top heat sink :
//sink height 1e03, area 100e06, material COPPER ;
//spreader height 0.5e03, area 70e06, material SILICON ;
heat transfer coefficient 1.3e-09 ;
temperature 318.15 ;
dimensions :
chip length 6100, width 10600 ;
cell length 100, width 100 ;
layer PCB :
height 10 ;
material BEOL ;
die DRAM :
layer 58.5 SILICON ;
source 2 SILICON ;
layer 1.5 BEOL ;
layer 58.5 SILICON ;
stack:
die DRAM_DIE DRAM floorplan "./mem.flp" ;
layer CONN_TO_PCB PCB ;
solver:
transient step 0.01, slot 0.05 ;
initial temperature 300.0 ;
output:
Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot );
Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot );
Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot );
Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot );
Tmap (DRAM_DIE, "output1.txt", slot) ;
Pmap (DRAM_DIE, "output2.txt", slot) ;

94
DRAMSys/tests/HBM2/scripts/createTraceDB.sql Normal file
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DROP TABLE IF EXISTS Phases;
DROP TABLE IF EXISTS GeneralInfo;
DROP TABLE IF EXISTS CommandLengths;
DROP TABLE IF EXISTS Comments;
DROP TABLE IF EXISTS ranges;
DROP TABLE IF EXISTS Transactions;
DROP TABLE IF EXISTS DebugMessages;
DROP TABLE IF EXISTS Power;
CREATE TABLE Phases(
ID INTEGER PRIMARY KEY,
PhaseName TEXT,
PhaseBegin INTEGER,
PhaseEnd INTEGER,
Transact INTEGER
);
CREATE TABLE GeneralInfo(
NumberOfTransactions INTEGER,
TraceEnd INTEGER,
NumberOfRanks INTEGER,
NumberOfBanks INTEGER,
clk INTEGER,
UnitOfTime TEXT,
MCconfig TEXT,
Memspec TEXT,
Traces TEXT,
WindowSize INTEGER,
FlexibleRefresh INTEGER,
MaxRefBurst INTEGER,
ControllerThread INTEGER
);
CREATE TABLE CommandLengths(
ACT INTEGER,
PRE INTEGER,
PREA INTEGER,
RD INTEGER,
RDA INTEGER,
WR INTEGER,
WRA INTEGER,
REFA INTEGER,
REFB INTEGER,
PDEA INTEGER,
PDXA INTEGER,
PDEP INTEGER,
PDXP INTEGER,
SREFEN INTEGER,
SREFEX INTEGER
);
CREATE TABLE Power(
time DOUBLE,
AveragePower DOUBLE
);
CREATE TABLE Comments(
Time INTEGER,
Text TEXT
);
CREATE TABLE DebugMessages(
Time INTEGER,
Message TEXT
);
-- use SQLITE R* TREE Module to make queries on timespans effecient (see http://www.sqlite.org/rtree.html)
CREATE VIRTUAL TABLE ranges USING rtree(
id,
begin, end
);
CREATE TABLE Transactions(
ID INTEGER,
Range INTEGER,
Address INTEGER,
Burstlength INTEGER,
TThread INTEGER,
TChannel INTEGER,
TRank INTEGER,
TBankgroup INTEGER,
TBank INTEGER,
TRow INTEGER,
TColumn INTEGER,
DataStrobeBegin INTEGER,
DataStrobeEnd INTEGER,
TimeOfGeneration INTEGER,
Command TEXT
);
CREATE INDEX ranges_index ON Transactions(Range);
CREATE INDEX "phasesTransactions" ON "Phases" ("Transact" ASC);
CREATE INDEX "messageTimes" ON "DebugMessages" ("Time" ASC);

20
DRAMSys/tests/HBM2/simulations/hbm2-example.json Normal file
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{
"simulation": {
"addressmapping": "am_hbm2_8Gb_pc_brc.json",
"mcconfig": "fifoStrict.json",
"memspec": "HBM2.json",
"simconfig": "hbm2.json",
"simulationid": "hbm2-example",
"thermalconfig": "config.json",
"tracesetup": [
{
"clkMhz": 1000,
"name": "trace1_test4.stl"
},
{
"clkMhz": 1000,
"name": "trace2_test4.stl"
}
]
}
}

51
DRAMSys/tests/ddr3_multirank/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json Normal file
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{
"CONGEN": {
"XOR":[
{
"FIRST":13,
"SECOND":16
}
],
"BANK_BIT": [
13,
14,
15
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
],
"RANK_BIT": [
30
]
}
}

12
DRAMSys/tests/ddr3_multirank/configs/mcconfigs/fr_fcfs_grp.json Normal file
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{"mcconfig":
{"PagePolicy": "Open",
"Scheduler": "FrFcfsGrp",
"RequestBufferSize": 8,
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "Rankwise",
"RefreshMode": 1,
"RefreshMaxPostponed": 0,
"RefreshMaxPulledin": 0,
"PowerDownPolicy": "Staggered",
"PowerDownTimeout": 100}}

55
DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json Normal file
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{
"memspec": {
"memarchitecturespec": {
"burstLength": 8,
"dataRate": 2,
"nbrOfBanks": 8,
"nbrOfColumns": 1024,
"nbrOfRanks": 2,
"nbrOfRows": 16384,
"width": 8
},
"memoryId": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM",
"memoryType": "DDR3",
"mempowerspec": {
"idd0": 720.0,
"idd2n": 400.0,
"idd2p0": 80.0,
"idd2p1": 200.0,
"idd3n": 440.0,
"idd3p0": 240.0,
"idd3p1": 240.0,
"idd4r": 1200.0,
"idd4w": 1200.0,
"idd5": 1760.0,
"idd6": 48.0,
"vdd": 1.5
},
"memtimingspec": {
"AL": 0,
"CCD": 4,
"CKE": 3,
"CKESR": 4,
"CL": 7,
"DQSCK": 0,
"FAW": 20,
"RAS": 20,
"RC": 27,
"RCD": 7,
"REFI": 4160,
"RFC": 59,
"RL": 7,
"RP": 7,
"RRD": 4,
"RTP": 4,
"WL": 6,
"WR": 8,
"WTR": 4,
"XP": 4,
"XPDLL": 13,
"XS": 64,
"XSDLL": 512,
"clkMhz": 533
}
}
}

21
DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json Normal file
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{
"simconfig": {
"AddressOffset": 0,
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"Debug": false,
"ECCControllerMode": "Disabled",
"EnableWindowing": false,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": 8,
"NumberOfMemChannels": 1,
"PowerAnalysis": false,
"SimulationName": "ddr3",
"SimulationProgressBar": true,
"StoreMode": "NoStorage",
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

15
DRAMSys/tests/ddr3_multirank/configs/thermalsim/config.json Normal file
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{
"thermalsimconfig": {
"TemperatureScale": "Celsius",
"StaticTemperatureDefaultValue": 89,
"ThermalSimPeriod":100,
"ThermalSimUnit":"us",
"PowerInfoFile": "powerInfo.json",
"IceServerIp": "127.0.0.1",
"IceServerPort": 11880,
"SimPeriodAdjustFactor" : 10,
"NPowStableCyclesToIncreasePeriod": 5,
"GenerateTemperatureMap": true,
"GeneratePowerMap": true
}
}

45
DRAMSys/tests/ddr3_multirank/configs/thermalsim/core.flp Executable file
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CPUs :
position 0, 0 ;
dimension 2750, 4300 ;
GPU :
position 3350, 0 ;
dimension 2750, 4000 ;
BASEBAND1 :
position 4250, 4000 ;
dimension 1850, 3300 ;
BASEBAND2 :
position 3350, 7300 ;
dimension 2750, 3300 ;
LLCACHE :
position 0, 4300 ;
dimension 1900, 3000 ;
DRAMCTRL1 :
position 1900, 4300 ;
dimension 850, 3000 ;
DRAMCTRL2 :
position 3350, 4000 ;
dimension 900, 3300 ;
TSVS :
position 2750, 2300 ;
dimension 600, 6000 ;
ACELLERATORS :
position 0, 7300 ;
dimension 2750, 3300 ;

16
DRAMSys/tests/ddr3_multirank/configs/thermalsim/mem.flp Executable file
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channel0 :
position 150, 100 ;
dimension 2600, 5200 ;
channel1 :
position 3350, 100 ;
dimension 2600, 5200 ;
channel2 :
position 150, 5300 ;
dimension 2600, 5200 ;
channel3 :
position 3350, 5300 ;
dimension 2600, 5200 ;

20
DRAMSys/tests/ddr3_multirank/configs/thermalsim/powerInfo.json Normal file
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{
"powerInfo": {
"dram_die_channel0": {
"init_pow": 0,
"threshold": 1.0
},
"dram_die_channel1": {
"init_pow": 0,
"threshold": 1.0
},
"dram_die_channel2": {
"init_pow": 0,
"threshold": 1.0
},
"dram_die_channel3": {
"init_pow": 0,
"threshold": 1.0
}
}
}

49
DRAMSys/tests/ddr3_multirank/configs/thermalsim/stack.stk Executable file
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material SILICON :
thermal conductivity 1.30e-4 ;
volumetric heat capacity 1.628e-12 ;
material BEOL :
thermal conductivity 2.25e-6 ;
volumetric heat capacity 2.175e-12 ;
material COPPER :
thermal conductivity 4.01e-04 ;
volumetric heat capacity 3.37e-12 ;
top heat sink :
//sink height 1e03, area 100e06, material COPPER ;
//spreader height 0.5e03, area 70e06, material SILICON ;
heat transfer coefficient 1.3e-09 ;
temperature 318.15 ;
dimensions :
chip length 6100, width 10600 ;
cell length 100, width 100 ;
layer PCB :
height 10 ;
material BEOL ;
die DRAM :
layer 58.5 SILICON ;
source 2 SILICON ;
layer 1.5 BEOL ;
layer 58.5 SILICON ;
stack:
die DRAM_DIE DRAM floorplan "./mem.flp" ;
layer CONN_TO_PCB PCB ;
solver:
transient step 0.01, slot 0.05 ;
initial temperature 300.0 ;
output:
Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot );
Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot );
Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot );
Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot );
Tmap (DRAM_DIE, "output1.txt", slot) ;
Pmap (DRAM_DIE, "output2.txt", slot) ;

94
DRAMSys/tests/ddr3_multirank/scripts/createTraceDB.sql Normal file
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DROP TABLE IF EXISTS Phases;
DROP TABLE IF EXISTS GeneralInfo;
DROP TABLE IF EXISTS CommandLengths;
DROP TABLE IF EXISTS Comments;
DROP TABLE IF EXISTS ranges;
DROP TABLE IF EXISTS Transactions;
DROP TABLE IF EXISTS DebugMessages;
DROP TABLE IF EXISTS Power;
CREATE TABLE Phases(
ID INTEGER PRIMARY KEY,
PhaseName TEXT,
PhaseBegin INTEGER,
PhaseEnd INTEGER,
Transact INTEGER
);
CREATE TABLE GeneralInfo(
NumberOfTransactions INTEGER,
TraceEnd INTEGER,
NumberOfRanks INTEGER,
NumberOfBanks INTEGER,
clk INTEGER,
UnitOfTime TEXT,
MCconfig TEXT,
Memspec TEXT,
Traces TEXT,
WindowSize INTEGER,
FlexibleRefresh INTEGER,
MaxRefBurst INTEGER,
ControllerThread INTEGER
);
CREATE TABLE CommandLengths(
ACT INTEGER,
PRE INTEGER,
PREA INTEGER,
RD INTEGER,
RDA INTEGER,
WR INTEGER,
WRA INTEGER,
REFA INTEGER,
REFB INTEGER,
PDEA INTEGER,
PDXA INTEGER,
PDEP INTEGER,
PDXP INTEGER,
SREFEN INTEGER,
SREFEX INTEGER
);
CREATE TABLE Power(
time DOUBLE,
AveragePower DOUBLE
);
CREATE TABLE Comments(
Time INTEGER,
Text TEXT
);
CREATE TABLE DebugMessages(
Time INTEGER,
Message TEXT
);
-- use SQLITE R* TREE Module to make queries on timespans effecient (see http://www.sqlite.org/rtree.html)
CREATE VIRTUAL TABLE ranges USING rtree(
id,
begin, end
);
CREATE TABLE Transactions(
ID INTEGER,
Range INTEGER,
Address INTEGER,
Burstlength INTEGER,
TThread INTEGER,
TChannel INTEGER,
TRank INTEGER,
TBankgroup INTEGER,
TBank INTEGER,
TRow INTEGER,
TColumn INTEGER,
DataStrobeBegin INTEGER,
DataStrobeEnd INTEGER,
TimeOfGeneration INTEGER,
Command TEXT
);
CREATE INDEX ranges_index ON Transactions(Range);
CREATE INDEX "phasesTransactions" ON "Phases" ("Transact" ASC);
CREATE INDEX "messageTimes" ON "DebugMessages" ("Time" ASC);

16
DRAMSys/tests/ddr3_multirank/simulations/ddr3-example.json Normal file
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{
"simulation": {
"addressmapping": "am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json",
"mcconfig": "fr_fcfs_grp.json",
"memspec": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json",
"simconfig": "ddr3.json",
"simulationid": "ddr3-example-dual-rank-json",
"thermalconfig": "config.json",
"tracesetup": [
{
"clkMhz": 533,
"name": "trace_test2.stl"
}
]
}
}

46
DRAMSys/tests/ddr4_bankgroups/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json Normal file
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@@ -0,0 +1,46 @@
{
"CONGEN": {
"BANKGROUP_BIT":[
30,
31
],
"BANK_BIT": [
28,
29
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27
]
}
}

12
DRAMSys/tests/ddr4_bankgroups/configs/mcconfigs/fr_fcfs.json Normal file
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@@ -0,0 +1,12 @@
{"mcconfig": {
"PagePolicy": "Open",
"Scheduler": "FrFcfs",
"RequestBufferSize": 8,
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "Rankwise",
"RefreshMode": 1,
"RefreshMaxPostponed": 128,
"RefreshMaxPulledin": 128,
"PowerDownPolicy": "NoPowerDown",
"PowerDownTimeout": 100}}

66
DRAMSys/tests/ddr4_bankgroups/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json Normal file
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@@ -0,0 +1,66 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 8,
"dataRate": 2,
"nbrOfBankGroups": 4,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 32768,
"width": 8
},
"memoryId": "MICRON_4Gb_DDR4-1866_8bit_A",
"memoryType": "DDR4",
"mempowerspec": {
"idd0": 56.25,
"idd02": 4.05,
"idd2n": 33.75,
"idd2p0": 17.0,
"idd2p1": 17.0,
"idd3n": 39.5,
"idd3p0": 22.5,
"idd3p1": 22.5,
"idd4r": 157.5,
"idd4w": 135.0,
"idd5": 118.0,
"idd6": 20.25,
"idd62": 2.6,
"vdd": 1.2,
"vdd2": 2.5
},
"memtimingspec": {
"AL": 0,
"CCD_L": 5,
"CCD_S": 4,
"CKE": 6,
"CKESR": 7,
"CL": 13,
"DQSCK": 2,
"FAW": 22,
"RAS": 32,
"RC": 45,
"RCD": 13,
"REFI": 3644,
"RFC": 243,
"RL": 13,
"RP": 13,
"RRD_L": 5,
"RRD_S": 4,
"RTP": 8,
"WL": 12,
"WR": 14,
"WTR_L": 7,
"WTR_S": 3,
"XP": 8,
"XPDLL": 255,
"XS": 252,
"XSDLL": 512,
"ACTPDEN": 1,
"PRPDEN": 1,
"REFPDEN": 1,
"RTRS": 1,
"clkMhz": 933
}
}
}

21
DRAMSys/tests/ddr4_bankgroups/configs/simulator/ddr4.json Normal file
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@@ -0,0 +1,21 @@
{
"simconfig": {
"AddressOffset": 0,
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"Debug": false,
"ECCControllerMode": "Disabled",
"EnableWindowing": false,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": 8,
"NumberOfMemChannels": 1,
"PowerAnalysis": false,
"SimulationName": "ddr4",
"SimulationProgressBar": true,
"StoreMode": "NoStorage",
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

15
DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/config.json Normal file
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@@ -0,0 +1,15 @@
{
"thermalsimconfig": {
"TemperatureScale": "Celsius",
"StaticTemperatureDefaultValue": 89,
"ThermalSimPeriod":100,
"ThermalSimUnit":"us",
"PowerInfoFile": "powerInfo.json",
"IceServerIp": "127.0.0.1",
"IceServerPort": 11880,
"SimPeriodAdjustFactor" : 10,
"NPowStableCyclesToIncreasePeriod": 5,
"GenerateTemperatureMap": true,
"GeneratePowerMap": true
}
}

45
DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/core.flp Executable file
View File

@@ -0,0 +1,45 @@
CPUs :
position 0, 0 ;
dimension 2750, 4300 ;
GPU :
position 3350, 0 ;
dimension 2750, 4000 ;
BASEBAND1 :
position 4250, 4000 ;
dimension 1850, 3300 ;
BASEBAND2 :
position 3350, 7300 ;
dimension 2750, 3300 ;
LLCACHE :
position 0, 4300 ;
dimension 1900, 3000 ;
DRAMCTRL1 :
position 1900, 4300 ;
dimension 850, 3000 ;
DRAMCTRL2 :
position 3350, 4000 ;
dimension 900, 3300 ;
TSVS :
position 2750, 2300 ;
dimension 600, 6000 ;
ACELLERATORS :
position 0, 7300 ;
dimension 2750, 3300 ;

16
DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/mem.flp Executable file
View File

@@ -0,0 +1,16 @@
channel0 :
position 150, 100 ;
dimension 2600, 5200 ;
channel1 :
position 3350, 100 ;
dimension 2600, 5200 ;
channel2 :
position 150, 5300 ;
dimension 2600, 5200 ;
channel3 :
position 3350, 5300 ;
dimension 2600, 5200 ;

20
DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/powerInfo.json Normal file
View File

@@ -0,0 +1,20 @@
{
"powerInfo": {
"dram_die_channel0": {
"init_pow": 0,
"threshold": 1.0
},
"dram_die_channel1": {
"init_pow": 0,
"threshold": 1.0
},
"dram_die_channel2": {
"init_pow": 0,
"threshold": 1.0
},
"dram_die_channel3": {
"init_pow": 0,
"threshold": 1.0
}
}
}

49
DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/stack.stk Executable file
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@@ -0,0 +1,49 @@
material SILICON :
thermal conductivity 1.30e-4 ;
volumetric heat capacity 1.628e-12 ;
material BEOL :
thermal conductivity 2.25e-6 ;
volumetric heat capacity 2.175e-12 ;
material COPPER :
thermal conductivity 4.01e-04 ;
volumetric heat capacity 3.37e-12 ;
top heat sink :
//sink height 1e03, area 100e06, material COPPER ;
//spreader height 0.5e03, area 70e06, material SILICON ;
heat transfer coefficient 1.3e-09 ;
temperature 318.15 ;
dimensions :
chip length 6100, width 10600 ;
cell length 100, width 100 ;
layer PCB :
height 10 ;
material BEOL ;
die DRAM :
layer 58.5 SILICON ;
source 2 SILICON ;
layer 1.5 BEOL ;
layer 58.5 SILICON ;
stack:
die DRAM_DIE DRAM floorplan "./mem.flp" ;
layer CONN_TO_PCB PCB ;
solver:
transient step 0.01, slot 0.05 ;
initial temperature 300.0 ;
output:
Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot );
Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot );
Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot );
Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot );
Tmap (DRAM_DIE, "output1.txt", slot) ;
Pmap (DRAM_DIE, "output2.txt", slot) ;

94
DRAMSys/tests/ddr4_bankgroups/scripts/createTraceDB.sql Normal file
View File

@@ -0,0 +1,94 @@
DROP TABLE IF EXISTS Phases;
DROP TABLE IF EXISTS GeneralInfo;
DROP TABLE IF EXISTS CommandLengths;
DROP TABLE IF EXISTS Comments;
DROP TABLE IF EXISTS ranges;
DROP TABLE IF EXISTS Transactions;
DROP TABLE IF EXISTS DebugMessages;
DROP TABLE IF EXISTS Power;
CREATE TABLE Phases(
ID INTEGER PRIMARY KEY,
PhaseName TEXT,
PhaseBegin INTEGER,
PhaseEnd INTEGER,
Transact INTEGER
);
CREATE TABLE GeneralInfo(
NumberOfTransactions INTEGER,
TraceEnd INTEGER,
NumberOfRanks INTEGER,
NumberOfBanks INTEGER,
clk INTEGER,
UnitOfTime TEXT,
MCconfig TEXT,
Memspec TEXT,
Traces TEXT,
WindowSize INTEGER,
FlexibleRefresh INTEGER,
MaxRefBurst INTEGER,
ControllerThread INTEGER
);
CREATE TABLE CommandLengths(
ACT INTEGER,
PRE INTEGER,
PREA INTEGER,
RD INTEGER,
RDA INTEGER,
WR INTEGER,
WRA INTEGER,
REFA INTEGER,
REFB INTEGER,
PDEA INTEGER,
PDXA INTEGER,
PDEP INTEGER,
PDXP INTEGER,
SREFEN INTEGER,
SREFEX INTEGER
);
CREATE TABLE Power(
time DOUBLE,
AveragePower DOUBLE
);
CREATE TABLE Comments(
Time INTEGER,
Text TEXT
);
CREATE TABLE DebugMessages(
Time INTEGER,
Message TEXT
);
-- use SQLITE R* TREE Module to make queries on timespans effecient (see http://www.sqlite.org/rtree.html)
CREATE VIRTUAL TABLE ranges USING rtree(
id,
begin, end
);
CREATE TABLE Transactions(
ID INTEGER,
Range INTEGER,
Address INTEGER,
Burstlength INTEGER,
TThread INTEGER,
TChannel INTEGER,
TRank INTEGER,
TBankgroup INTEGER,
TBank INTEGER,
TRow INTEGER,
TColumn INTEGER,
DataStrobeBegin INTEGER,
DataStrobeEnd INTEGER,
TimeOfGeneration INTEGER,
Command TEXT
);
CREATE INDEX ranges_index ON Transactions(Range);
CREATE INDEX "phasesTransactions" ON "Phases" ("Transact" ASC);
CREATE INDEX "messageTimes" ON "DebugMessages" ("Time" ASC);

16
DRAMSys/tests/ddr4_bankgroups/simulations/ddr4-example.json Normal file
View File

@@ -0,0 +1,16 @@
{
"simulation": {
"addressmapping": "am_ddr4_8x4Gbx8_dimm_p1KB_brc.json",
"mcconfig": "fr_fcfs.json",
"memspec": "MICRON_4Gb_DDR4-1866_8bit_A.json",
"simconfig": "ddr4.json",
"simulationid": "ddr4-bankgrp",
"thermalconfig": "config.json",
"tracesetup": [
{
"clkMhz": 933,
"name": "trace_test3.stl"
}
]
}
}

42
DRAMSys/tests/lpddr4/configs/amconfigs/am_lpddr4_8Gbx16_brc.json Normal file
View File

@@ -0,0 +1,42 @@
{
"CONGEN": {
"BANK_BIT": [
27,
28,
29
],
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
]
}
}

11
DRAMSys/tests/lpddr4/configs/mcconfigs/fifo.json Normal file
View File

@@ -0,0 +1,11 @@
{"mcconfig": {"PagePolicy": "Open",
"Scheduler": "Fifo",
"RequestBufferSize": 8,
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "Bankwise",
"RefreshMode": 1,
"RefreshMaxPostponed": 8,
"RefreshMaxPulledin": 8,
"PowerDownPolicy": "NoPowerDown",
"PowerDownTimeout": 100}}

46
DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json Normal file
View File

@@ -0,0 +1,46 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 2,
"nbrOfBanks": 8,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 65536,
"width": 16
},
"memoryId": "JEDEC_8Gb_LPDDR4-3200_16bit",
"memoryType": "LPDDR4",
"memtimingspec": {
"CCD": 8,
"CKE": 12,
"CMDCKE": 3,
"DQS2DQ": 2,
"DQSCK": 6,
"DQSS": 1,
"ESCKE": 3,
"FAW": 64,
"PPD": 4,
"RAS": 68,
"RCD": 29,
"REFI": 6246,
"REFIPB": 780,
"RFCAB": 448,
"RFCPB": 224,
"RL": 28,
"RPAB": 34,
"RPPB": 29,
"RPST": 0,
"RRD": 16,
"RTP": 12,
"SR": 24,
"WL": 14,
"WPRE": 2,
"WR": 29,
"WTR": 16,
"XP": 12,
"XSR": 460,
"clkMhz": 1600
}
}
}

21
DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json Normal file
View File

@@ -0,0 +1,21 @@
{
"simconfig": {
"AddressOffset": 0,
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"Debug": false,
"ECCControllerMode": "Disabled",
"EnableWindowing": false,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": 1,
"NumberOfMemChannels": 1,
"PowerAnalysis": false,
"SimulationName": "lpddr4",
"SimulationProgressBar": true,
"StoreMode": "NoStorage",
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

15
DRAMSys/tests/lpddr4/configs/thermalsim/config.json Normal file
View File

@@ -0,0 +1,15 @@
{
"thermalsimconfig": {
"TemperatureScale": "Celsius",
"StaticTemperatureDefaultValue": 89,
"ThermalSimPeriod":100,
"ThermalSimUnit":"us",
"PowerInfoFile": "powerInfo.json",
"IceServerIp": "127.0.0.1",
"IceServerPort": 11880,
"SimPeriodAdjustFactor" : 10,
"NPowStableCyclesToIncreasePeriod": 5,
"GenerateTemperatureMap": true,
"GeneratePowerMap": true
}
}

45
DRAMSys/tests/lpddr4/configs/thermalsim/core.flp Executable file
View File

@@ -0,0 +1,45 @@
CPUs :
position 0, 0 ;
dimension 2750, 4300 ;
GPU :
position 3350, 0 ;
dimension 2750, 4000 ;
BASEBAND1 :
position 4250, 4000 ;
dimension 1850, 3300 ;
BASEBAND2 :
position 3350, 7300 ;
dimension 2750, 3300 ;
LLCACHE :
position 0, 4300 ;
dimension 1900, 3000 ;
DRAMCTRL1 :
position 1900, 4300 ;
dimension 850, 3000 ;
DRAMCTRL2 :
position 3350, 4000 ;
dimension 900, 3300 ;
TSVS :
position 2750, 2300 ;
dimension 600, 6000 ;
ACELLERATORS :
position 0, 7300 ;
dimension 2750, 3300 ;

16
DRAMSys/tests/lpddr4/configs/thermalsim/mem.flp Executable file
View File

@@ -0,0 +1,16 @@
channel0 :
position 150, 100 ;
dimension 2600, 5200 ;
channel1 :
position 3350, 100 ;
dimension 2600, 5200 ;
channel2 :
position 150, 5300 ;
dimension 2600, 5200 ;
channel3 :
position 3350, 5300 ;
dimension 2600, 5200 ;

20
DRAMSys/tests/lpddr4/configs/thermalsim/powerInfo.json Normal file
View File

@@ -0,0 +1,20 @@
{
"powerInfo": {
"dram_die_channel0": {
"init_pow": 0,
"threshold": 1.0
},
"dram_die_channel1": {
"init_pow": 0,
"threshold": 1.0
},
"dram_die_channel2": {
"init_pow": 0,
"threshold": 1.0
},
"dram_die_channel3": {
"init_pow": 0,
"threshold": 1.0
}
}
}

49
DRAMSys/tests/lpddr4/configs/thermalsim/stack.stk Executable file
View File

@@ -0,0 +1,49 @@
material SILICON :
thermal conductivity 1.30e-4 ;
volumetric heat capacity 1.628e-12 ;
material BEOL :
thermal conductivity 2.25e-6 ;
volumetric heat capacity 2.175e-12 ;
material COPPER :
thermal conductivity 4.01e-04 ;
volumetric heat capacity 3.37e-12 ;
top heat sink :
//sink height 1e03, area 100e06, material COPPER ;
//spreader height 0.5e03, area 70e06, material SILICON ;
heat transfer coefficient 1.3e-09 ;
temperature 318.15 ;
dimensions :
chip length 6100, width 10600 ;
cell length 100, width 100 ;
layer PCB :
height 10 ;
material BEOL ;
die DRAM :
layer 58.5 SILICON ;
source 2 SILICON ;
layer 1.5 BEOL ;
layer 58.5 SILICON ;
stack:
die DRAM_DIE DRAM floorplan "./mem.flp" ;
layer CONN_TO_PCB PCB ;
solver:
transient step 0.01, slot 0.05 ;
initial temperature 300.0 ;
output:
Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot );
Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot );
Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot );
Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot );
Tmap (DRAM_DIE, "output1.txt", slot) ;
Pmap (DRAM_DIE, "output2.txt", slot) ;

94
DRAMSys/tests/lpddr4/scripts/createTraceDB.sql Normal file
View File

@@ -0,0 +1,94 @@
DROP TABLE IF EXISTS Phases;
DROP TABLE IF EXISTS GeneralInfo;
DROP TABLE IF EXISTS CommandLengths;
DROP TABLE IF EXISTS Comments;
DROP TABLE IF EXISTS ranges;
DROP TABLE IF EXISTS Transactions;
DROP TABLE IF EXISTS DebugMessages;
DROP TABLE IF EXISTS Power;
CREATE TABLE Phases(
ID INTEGER PRIMARY KEY,
PhaseName TEXT,
PhaseBegin INTEGER,
PhaseEnd INTEGER,
Transact INTEGER
);
CREATE TABLE GeneralInfo(
NumberOfTransactions INTEGER,
TraceEnd INTEGER,
NumberOfRanks INTEGER,
NumberOfBanks INTEGER,
clk INTEGER,
UnitOfTime TEXT,
MCconfig TEXT,
Memspec TEXT,
Traces TEXT,
WindowSize INTEGER,
FlexibleRefresh INTEGER,
MaxRefBurst INTEGER,
ControllerThread INTEGER
);
CREATE TABLE CommandLengths(
ACT INTEGER,
PRE INTEGER,
PREA INTEGER,
RD INTEGER,
RDA INTEGER,
WR INTEGER,
WRA INTEGER,
REFA INTEGER,
REFB INTEGER,
PDEA INTEGER,
PDXA INTEGER,
PDEP INTEGER,
PDXP INTEGER,
SREFEN INTEGER,
SREFEX INTEGER
);
CREATE TABLE Power(
time DOUBLE,
AveragePower DOUBLE
);
CREATE TABLE Comments(
Time INTEGER,
Text TEXT
);
CREATE TABLE DebugMessages(
Time INTEGER,
Message TEXT
);
-- use SQLITE R* TREE Module to make queries on timespans effecient (see http://www.sqlite.org/rtree.html)
CREATE VIRTUAL TABLE ranges USING rtree(
id,
begin, end
);
CREATE TABLE Transactions(
ID INTEGER,
Range INTEGER,
Address INTEGER,
Burstlength INTEGER,
TThread INTEGER,
TChannel INTEGER,
TRank INTEGER,
TBankgroup INTEGER,
TBank INTEGER,
TRow INTEGER,
TColumn INTEGER,
DataStrobeBegin INTEGER,
DataStrobeEnd INTEGER,
TimeOfGeneration INTEGER,
Command TEXT
);
CREATE INDEX ranges_index ON Transactions(Range);
CREATE INDEX "phasesTransactions" ON "Phases" ("Transact" ASC);
CREATE INDEX "messageTimes" ON "DebugMessages" ("Time" ASC);

16
DRAMSys/tests/lpddr4/simulations/lpddr4-example.json Normal file
View File

@@ -0,0 +1,16 @@
{
"simulation": {
"addressmapping": "am_lpddr4_8Gbx16_brc.json",
"mcconfig": "fifo.json",
"memspec": "JEDEC_8Gb_LPDDR4-3200_16bit.json",
"simconfig": "lpddr4.json",
"simulationid": "lpddr4-example",
"thermalconfig": "config.json",
"tracesetup": [
{
"clkMhz": 1600,
"name": "trace_lpddr4.stl"
}
]
}
}