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Remove old tests.

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This commit is contained in:
Lukas Steiner
2020-07-02 15:07:29 +02:00
parent 88821a2216
commit 7b4aeaf663
25 changed files with 0 additions and 1321 deletions
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1
DRAMSys/tests/.gitignore vendored
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*.txt

15
DRAMSys/tests/TLM_compliance/fifoStrict.xml
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<mcconfig>
<BankwiseLogic value="0"/>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
<Scheduler value="FifoStrict" />
<Capsize value="5" />
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Error Modelling -->
<ErrorChipSeed value="42" />
<ErrorCSVFile value="../../DRAMSys/library/src/error/error.csv" />
<!-- Modes: NoStorage, Store (store data without errormodel), ErrorModel (store data with errormodel) -->
<StoreMode value="NoStorage"/>
</mcconfig>

51
DRAMSys/tests/TLM_compliance/sim-batch.xml
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<simulation>
<!-- General Simulator Configuration (used for all simulation setups) -->
<simconfig>
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "0" />
<WindowSize value="1000" />
<NumberOfTracePlayers value="1"/>
<NumberOfMemChannels value="4"/>
<ControllerCoreRefDisable value="0"/>
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfDevicesOnDIMM value = "1" />
<CheckTLM2Protocol value = "1" />
</simconfig>
<!-- Temperature Simulator Configuration (used for all simulation setups) -->
<thermalsimconfig>
<TemperatureScale value="Celsius" />
<StaticTemperatureDefaultValue value="89" />
<ThermalSimPeriod value="10" />
<ThermalSimUnit value="ms" />
<PowerInfoFile value="../../DRAMSys/library/resources/configs/thermalsim/powerInfo.xml"/>
<IceServerIp value="127.0.0.1" />
<IceServerPort value="11880" />
<SimPeriodAdjustFactor value="10" />
<NPowStableCyclesToIncreasePeriod value="5" />
<GenerateTemperatureMap value="1" />
<GeneratePowerMap value="1" />
</thermalsimconfig>
<memspecs>
<memspec src="../../DRAMSys/library/resources/configs/memspecs/WideIO.xml"></memspec>
</memspecs>
<addressmappings>
<addressmapping src="../../DRAMSys/library/resources/configs/amconfigs/am_wideio.xml"></addressmapping>
</addressmappings>
<mcconfigs>
<mcconfig src="../../DRAMSys/tests/TLM_compliance/fifoStrict.xml"/>
</mcconfigs>
<tracesetups>
<tracesetup id="TLM_compliance_test">
<device clkMhz="200">chstone-adpcm_32.stl</device>
</tracesetup>
</tracesetups>
</simulation>

105
DRAMSys/tests/TLM_compliance/test.pl
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#!/usr/bin/perl -w
# Copyright (c) 2015, University of Kaiserslautern
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors:
# Matthias Jung, Felipe S. Prado, Thanh C. Tran
#
# Test TLM Compliance:
# This test runs the simulation with standard configuration
# Run Simulation:
# Get number of Cores:
use Config;
my $numberOfCores;
if ($Config{osname} eq "darwin")
{
$numberOfCores = `sysctl -n hw.ncpu`;
}
elsif ($Config{osname} eq "linux")
{
$numberOfCores = `cat /proc/cpuinfo | grep processor | wc -l`;
}
chdir("../../../build/simulator/");
$exampleInitiatorLine = `grep -n '#define USE_EXAMPLE_INITIATOR' ../../DRAMSys/library/src/simulation/SimulationManager.h | cut -d: -f 1`;
chomp $exampleInitiatorLine;
system("sed -i.bu '" . $exampleInitiatorLine . "s^.*^#define USE_EXAMPLE_INITIATOR 1^' ../../DRAMSys/library/src/simulation/SimulationManager.h");
`make -j$numberOfCores > /dev/null 2>&1`;
$storeModeLine = `grep -n '<StoreMode value=' ../../DRAMSys/tests/TLM_compliance/fifoStrict.xml | cut -d: -f 1`;
chomp $storeModeLine;
system("sed -i.bu '" . $storeModeLine . "s^.*^ <StoreMode value=\"Store\"/>^' ../../DRAMSys/tests/TLM_compliance/fifoStrict.xml");
`./DRAMSys ../../DRAMSys/tests/TLM_compliance/sim-batch.xml &> ../../DRAMSys/tests/TLM_compliance/output.txt`;
if("" ne `grep "Error: tlm2_protocol_checker" ../../DRAMSys/tests/TLM_compliance/output.txt`)
{
clean_backup_files();
exit -1;
}
system("sed -i.bu '" . $exampleInitiatorLine . "s^.*^#define USE_EXAMPLE_INITIATOR 0^' ../../DRAMSys/library/src/simulation/SimulationManager.h");
`make -j$numberOfCores > /dev/null 2>&1`;
system("sed -i.bu '" . $storeModeLine . "s^.*^ <StoreMode value=\"NoStorage\"/>^' ../../DRAMSys/tests/TLM_compliance/fifoStrict.xml");
`rm -f sim-batch/TLM_compliance_test*.tdb`;
`./DRAMSys ../../DRAMSys/tests/TLM_compliance/sim-batch.xml &> ../../DRAMSys/tests/TLM_compliance/output.txt`;
if("" ne `grep "Error: tlm2_protocol_checker" ../../DRAMSys/tests/TLM_compliance/output.txt`)
{
clean_backup_files();
exit -1;
}
clean_backup_files();
exit 0;
sub clean_backup_files {
`rm -rf ../../DRAMSys/library/src/simulation/SimulationManager.h.bu`;
`rm -rf ../../DRAMSys/tests/TLM_compliance/fifoStrict.xml.bu`;
}

150
DRAMSys/tests/continuous_testing_py/autotest.py
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# -*- coding: utf-8 -*-
# Copyright (c) 2016, University of Kaiserslautern
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Éder F. Zulian
#
import unittest
import subprocess
import os
import shutil
import multiprocessing
import sys
import tempfile
from memutil import *
devnull = None
# If you want to change the standard output and/or standard error output do
# that in the top-level script environment (the '__main__' at the very bottom
# of this file.
out = None
errout = None
rootdir = '../../..'
workingdir = os.getcwd()
tempfile.tempdir = workingdir + '/' + rootdir
builddir = tempfile.mkdtemp()
simdir = builddir + '/simulator'
mcConfigPath = rootdir + '/DRAMSys/library/resources/configs/mcconfigs'
memSpecsPath = rootdir + '/DRAMSys/library/resources/configs/memspecs'
baseConfigPath = workingdir + '/baseconfig.xml'
qmakeProjFile = '../DRAMSys/DRAMSys.pro'
def build_project():
if os.path.exists(builddir):
shutil.rmtree(builddir)
os.makedirs(builddir)
os.chdir(builddir)
subprocess.call(['qmake', qmakeProjFile], stdout=out, stderr=errout)
makejobs = '-j' + str(multiprocessing.cpu_count())
ret = subprocess.call(['make', makejobs], stdout=out, stderr=errout)
return ret
class TestBuild(unittest.TestCase):
def test_build_project(self):
""" The project's build process should succeed """
self.assertEqual(build_project(), 0)
def tearDown(self):
shutil.rmtree(builddir)
class TestRun(unittest.TestCase):
def setUp(self):
build_project()
def test_run_without_arguments(self):
""" running dramSys without arguments returns 0 """
os.chdir(simdir)
self.assertEqual(subprocess.call(['./DRAMSys'], stdout=out), 0)
def tearDown(self):
shutil.rmtree(builddir)
@unittest.skip("skipping this")
class TestOutput(unittest.TestCase):
def setUp(self):
self.tfd, self.tfpath = tempfile.mkstemp()
self.outrefpath = workingdir + '/baseconfig_expected.out'
build_project()
def filter_output(self, fname):
with open(fname, 'r') as f:
lines = f.readlines()
f.close()
return [l for l in lines if l.startswith('sim.dram')]
def test_run_with_base_config(self):
""" running dramSys with base config, output match reference """
os.chdir(simdir)
with open(self.tfpath, 'w') as f:
self.assertEqual(subprocess.call(['./DRAMSys', baseConfigPath],
stdout=f), 0)
f.close()
tout = self.filter_output(self.tfpath)
tref = self.filter_output(self.outrefpath)
self.assertListEqual(tout, tref)
def tearDown(self):
shutil.rmtree(builddir)
os.unlink(self.tfpath)
# This is an example that shows how to skip a test.
@unittest.skip("skipping this")
class TestDummy(unittest.TestCase):
def setUp(self):
os.chdir(workingdir)
def test_list_files(self):
""" Test that lists some configuration files with XML extension """
print('\nPath is: {}\n'.format(mcConfigPath))
for file in os.listdir(mcConfigPath):
if file.endswith(".xml"):
print(file)
print('\nPath is: {}\n'.format(memSpecsPath))
for file in os.listdir(memSpecsPath):
if file.endswith(".xml"):
print(file)
if __name__ == '__main__':
with open(os.devnull, 'wb') as devnull:
out = devnull
errout = devnull
# out = sys.stdout
# errout = sys.stderr
unittest.main()

56
DRAMSys/tests/continuous_testing_py/baseconfig.xml
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<simulation>
<!-- General Simulator Configuration (used for all simulation setups) -->
<simconfig>
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<WindowSize value="100" />
<NumberOfTracePlayers value="1"/>
<NumberOfMemChannels value="1"/>
<ControllerCoreRefDisable value="0"/>
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfDevicesOnDIMM value = "8" />
</simconfig>
<!-- Temperature Simulator Configuration (used for all simulation setups) -->
<thermalsimconfig>
<TemperatureScale value="Celsius" />
<StaticTemperatureDefaultValue value="89" />
<ThermalSimPeriod value="100" />
<ThermalSimUnit value="us" />
<PowerInfoFile value="../../DRAMSys/library/resources/configs/thermalsim/powerInfo.xml"/>
<IceServerIp value="127.0.0.1" />
<IceServerPort value="11880" />
<SimPeriodAdjustFactor value="10" />
<NPowStableCyclesToIncreasePeriod value="5" />
<GenerateTemperatureMap value="1" />
<GeneratePowerMap value="1" />
</thermalsimconfig>
<!-- Memory Device Specification: Which Device is on our simulated DDR3 DIMM -->
<memspecs>
<memspec src="../../DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml"></memspec>
</memspecs>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmappings>
<addressmapping src="../../DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml"></addressmapping>
</addressmappings>
<!-- Memory Controller Configuration -->
<mcconfigs>
<mcconfig src="../../DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml"/>
</mcconfigs>
<tracesetups>
<tracesetup id="continuous_testing_py">
<device clkMhz="200">ddr3_example.stl</device>
</tracesetup>
</tracesetups>
</simulation>

6
DRAMSys/tests/continuous_testing_py/baseconfig_expected.out
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sim.dram0 Total Energy: 45565500.00 pJ
sim.dram0 Average Power: 2156.95 mW
sim.dram0 Total Time: 20642500 ps
sim.dram0 AVG BW: 45.44 Gibit/s (45.44 %)
sim.dram0 AVG BW/IDLE: 45.44 Gibit/s (45.44 %)
sim.dram0 MAX BW: 100.00 Gibit/s

70
DRAMSys/tests/continuous_testing_py/memutil.py
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# -*- coding: utf-8 -*-
# Copyright (c) 2016, University of Kaiserslautern
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Éder F. Zulian
#
import xml.etree.ElementTree as ET
class MCConfig(object):
""" Memory Controller Configuration Class
The format used in memory specification XML files differs from the
format used in memory controller configuration XML files. Each class
uses the proper format when searching for elements.
"""
def getValue(self, id):
return self.xmlMCConfig.findall(id)[0].attrib['value']
def getIntValue(self, id):
return int(self.getValue(id))
def __init__(self, xmlfile):
self.xmlMCConfig = ET.parse(xmlfile)
class MemSpec(object):
""" Memory Specification Class
The format used in memory specification XML files differs from the
format used in memory configuration XML files. Each class uses the
proper format when searching for elements.
"""
def getValue(self, id):
return self.xmlMemSpec.findall(".//parameter[@id='{0}']".
format(id))[0].attrib['value']
def getIntValue(self, id):
return int(self.getValue(id))
def __init__(self, xmlfile):
self.xmlMemSpec = ET.parse(xmlfile)

1
DRAMSys/tests/error/.gitignore vendored
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*.stl

61
DRAMSys/tests/error/WideIO.xml
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<!DOCTYPE memspec SYSTEM "memspec.dtd">
<memspec>
<parameter id="memoryId" type="string" value="Matze_WideIO" />
<parameter id="memoryType" type="string" value="WIDEIO_SDR" />
<memarchitecturespec>
<parameter id="width" type="uint" value="128" />
<parameter id="nbrOfBanks" type="uint" value="8" />
<parameter id="nbrOfColumns" type="uint" value="128" />
<parameter id="nbrOfRows" type="uint" value="8192" />
<parameter id="dataRate" type="uint" value="1" />
<parameter id="burstLength" type="uint" value="4" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="166" />
<parameter id="RC" type="uint" value="9" /><!--tRP+tRAS-->
<parameter id="RCD" type="uint" value="3" />
<parameter id="RL" type="uint" value="3" />
<parameter id="RP" type="uint" value="3" />
<parameter id="RFC" type="uint" value="22" />
<parameter id="RAS" type="uint" value="6" />
<parameter id="WL" type="uint" value="1" />
<parameter id="AL" type="uint" value="0" />
<parameter id="RTP" type="uint" value="4" />
<parameter id="WR" type="uint" value="2" />
<parameter id="XP" type="uint" value="2" />
<parameter id="XS" type="uint" value="20" /><!--tRFC+2clk-->
<parameter id="REFI" type="uint" value="4000" />
<parameter id="TAW" type="uint" value="10" />
<parameter id="RRD" type="uint" value="2" />
<parameter id="CCD" type="uint" value="1" />
<parameter id="WTR" type="uint" value="3" />
<parameter id="CKE" type="uint" value="3" />
<parameter id="CKESR" type="uint" value="3" />
</memtimingspec>
<mempowerspec>
<parameter id="idd0" type="double" value="5.88" />
<parameter id="idd02" type="double" value="21.18" />
<parameter id="idd2p0" type="double" value="0.05" />
<parameter id="idd2p02" type="double" value="0.17" />
<parameter id="idd2p1" type="double" value="0.05" />
<parameter id="idd2p12" type="double" value="0.17" />
<parameter id="idd2n" type="double" value="0.13" />
<parameter id="idd2n2" type="double" value="4.04" />
<parameter id="idd3p0" type="double" value="0.25" />
<parameter id="idd3p02" type="double" value="1.49" />
<parameter id="idd3p1" type="double" value="0.25" />
<parameter id="idd3p12" type="double" value="1.49" />
<parameter id="idd3n" type="double" value="0.52" />
<parameter id="idd3n2" type="double" value="6.55" />
<parameter id="idd4r" type="double" value="1.41" />
<parameter id="idd4r2" type="double" value="85.73" />
<parameter id="idd4w" type="double" value="1.42" />
<parameter id="idd4w2" type="double" value="60.79" />
<parameter id="idd5" type="double" value="14.43" />
<parameter id="idd52" type="double" value="48.17" />
<parameter id="idd6" type="double" value="0.07" />
<parameter id="idd62" type="double" value="0.27" />
<parameter id="vdd" type="double" value="1.8" />
<parameter id="vdd2" type="double" value="1.2" />
</mempowerspec>
</memspec>

18
DRAMSys/tests/error/am_wideio.xml
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<addressmapping>
<channel from="27" to="28" />
<row from="14" to="26" />
<column from="7" to="13" />
<bank from="4" to="6" />
<bytes from="0" to="3" />
</addressmapping>
<!-- Magali values: -->
<!--
<addressmapping>
<channel from="27" to="28" />
<bank from="24" to="26" />
<row from="11" to="23" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>
-->

22
DRAMSys/tests/error/fr_fcfs.xml
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<mcconfig>
<BankwiseLogic value="0"/>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
<Scheduler value="FrFcfs" />
<Capsize value="5" />
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Error Model: -->
<ErrorChipSeed value="42" />
<ErrorCSVFile value="../../DRAMSys/library/src/error/error.csv" />
<!-- Modes: NoStorage, Store (store data without errormodel), ErrorModel (store data with errormodel) -->
<StoreMode value="ErrorModel" />
<!--
<ReadWriteGrouping value="false" />
<ModelStorage value="false" />
<ModelErrorInjection value="false" />
<ReorderBuffer value="false" />
<DatabaseRecording value="true" />
-->
</mcconfig>

63
DRAMSys/tests/error/generateErrorTest.pl
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#!/usr/bin/perl -w
use warnings;
use strict;
# Assuming this address mapping:
# <addressmapping>
# <channel from="27" to="28" />
# <row from="14" to="26" />
# <column from="7" to="13" />
# <bank from="4" to="6" />
# <bytes from="0" to="3" />
# </addressmapping>
# This is how it should look like later:
# 31: write 0x0 ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
my $numberOfRows = 8192;
my $numberOfColumnsPerRow = 128;
my $bytesPerColumn = 16;
my $burstLength = 4; # burst length of 4 columns --> 4 columns written or read per access
my $dataLength = $bytesPerColumn * $burstLength;
my $rowOffset = 0x4000;
my $colOffset = 0x80;
# Generate Data Pattern:
my $dataPatternByte = "ff";
my $dataPattern = "";
for(my $i = 0; $i < $dataLength; $i++)
{
$dataPattern .= $dataPatternByte;
}
my $clkCounter = 0;
my $addr = 0;
# Generate Trace file (writes):
for(my $row = 0; $row < ($numberOfRows * $rowOffset); $row = $row + $rowOffset)
{
for(my $col = 0; $col < ($numberOfColumnsPerRow * $colOffset); $col = $col + ($colOffset * $burstLength))
{
my $addrHex = sprintf("0x%x", $addr);
print "$clkCounter:\twrite\t$addrHex\t$dataPattern\n";
$clkCounter++;
$addr += $colOffset * $burstLength;
}
}
$clkCounter = 350000000;
$addr = 0;
# Generate Trace file (reads):
for(my $row = 0; $row < ($numberOfRows * $rowOffset); $row = $row + $rowOffset)
{
for(my $col = 0; $col < ($numberOfColumnsPerRow * $colOffset); $col = $col + ($colOffset * $burstLength))
{
my $addrHex = sprintf("0x%x", $addr);
print "$clkCounter:\tread\t$addrHex\t$dataPattern\n";
$clkCounter++;
$addr += $colOffset * $burstLength;
}
}

72
DRAMSys/tests/error/generateErrorTest_4ch.pl
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#!/usr/bin/perl -w
use warnings;
use strict;
# Assuming this address mapping:
# <addressmapping>
# <channel from="27" to="28" />
# <row from="14" to="26" />
# <column from="7" to="13" />
# <bank from="4" to="6" />
# <bytes from="0" to="3" />
# </addressmapping>
# This is how it should look like later:
# 31: write 0x0 ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
my $numberOfRows = 8192;
my $numberOfColumnsPerRow = 128;
my $bytesPerColumn = 16;
my $burstLength = 4; # burst length of 4 columns --> 4 columns written or read per access
my $dataLength = $bytesPerColumn * $burstLength;
my $rowOffset = 0x4000;
my $colOffset = 0x80;
# Generate Data Pattern:
my $dataPatternByte = "ff";
my $dataPattern = "";
for(my $i = 0; $i < $dataLength; $i++)
{
$dataPattern .= $dataPatternByte;
}
my $clkCounter = 0;
my $addr = 0;
# Generate Trace file (writes):
for(my $ch = 0; $ch < 4; $ch++) {
$addr = 0;
$addr |= $ch << 27;
for(my $row = 0; $row < ($numberOfRows * $rowOffset); $row = $row + $rowOffset)
{
for(my $col = 0; $col < ($numberOfColumnsPerRow * $colOffset); $col = $col + ($colOffset * $burstLength))
{
my $addrHex = sprintf("0x%x", $addr);
print "$clkCounter:\twrite\t$addrHex\t$dataPattern\n";
$clkCounter++;
$addr += $colOffset * $burstLength;
}
}
}
$clkCounter = 350000000;
$addr = 0;
# Generate Trace file (reads):
for(my $ch = 0; $ch < 4; $ch++) {
$addr = 0;
$addr |= $ch << 27;
for(my $row = 0; $row < ($numberOfRows * $rowOffset); $row = $row + $rowOffset)
{
for(my $col = 0; $col < ($numberOfColumnsPerRow * $colOffset); $col = $col + ($colOffset * $burstLength))
{
my $addrHex = sprintf("0x%x", $addr);
print "$clkCounter:\tread\t$addrHex\t$dataPattern\n";
$clkCounter++;
$addr += $colOffset * $burstLength;
}
}
}

52
DRAMSys/tests/error/sim-batch.xml
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@@ -1,52 +0,0 @@
<simulation>
<!-- General Simulator Configuration (used for all simulation setups) -->
<simconfig>
<Debug value="0" />
<DatabaseRecording value="0" />
<PowerAnalysis value="1" />
<EnableWindowing value = "0" />
<WindowSize value="1000" />
<NumberOfTracePlayers value="1"/>
<NumberOfMemChannels value="4"/>
<ControllerCoreRefDisable value="0"/>
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfDevicesOnDIMM value = "1" />
<CheckTLM2Protocol value = "0" />
</simconfig>
<!-- Temperature Simulator Configuration (used for all simulation setups) -->
<thermalsimconfig>
<TemperatureScale value="Celsius" />
<StaticTemperatureDefaultValue value="89" />
<ThermalSimPeriod value="10" />
<ThermalSimUnit value="ms" />
<PowerInfoFile value="../../DRAMSys/library/resources/configs/thermalsim/powerInfo.xml"/>
<IceServerIp value="127.0.0.1" />
<IceServerPort value="11880" />
<SimPeriodAdjustFactor value="10" />
<NPowStableCyclesToIncreasePeriod value="5" />
<GenerateTemperatureMap value="1" />
<GeneratePowerMap value="1" />
</thermalsimconfig>
<memspecs>
<memspec src="../../DRAMSys/tests/error/WideIO.xml"></memspec>
</memspecs>
<addressmappings>
<addressmapping src="../../DRAMSys/tests/error/am_wideio.xml"></addressmapping>
</addressmappings>
<mcconfigs>
<mcconfig src="../../DRAMSys/tests/error/fr_fcfs.xml"/>
</mcconfigs>
<tracesetups>
<tracesetup id="errorTest_fr_fcfs_test_error.stl">
<device clkMhz="1000">../../../tests/error/test_error.stl</device>
</tracesetup>
</tracesetups>
</simulation>

84
DRAMSys/tests/error/test.pl
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@@ -1,84 +0,0 @@
#!/usr/bin/perl -w
# Copyright (c) 2015, University of Kaiserslautern
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors:
# Matthias Jung
# Eder F. Zulian
#
# Test error:
# This test runs the simulation with error model enabled.
# The main configuration file for this test is DRAMSys/tests/error/sim-batch.xml.
#
use warnings;
use strict;
use Term::ANSIColor;
my $trace_file = "test_error.stl";
# Create the input file (first make sure the script is executable)
chdir("../../DRAMSys/tests/error");
if (! -e $trace_file) {
`chmod u+x ./generateErrorTest.pl`;
`./generateErrorTest.pl > $trace_file`;
}
# Run Simulation:
chdir("../../../build/simulator/");
`./DRAMSys ../../DRAMSys/tests/error/sim-batch.xml > ../../DRAMSys/tests/error/output.txt`;
chdir("../../DRAMSys/tests/error");
my @channels_retention_errors = ();
@channels_retention_errors = split(/\n/,`cat output.txt | grep 'Number of Retention Error Events' | cut -d= -f2 | sed 's/ //g'`);
if (!@channels_retention_errors) {
print color("red"), "\tError: ", color("green"), "error model output information not found.\n";
print color("yellow"), "\tCheck if error model is enabled.\n";
exit -1
}
my $errors_found = 0;
foreach (@channels_retention_errors) {
print "$_\n";
$errors_found += $_;
}
print color("green"), "Number of Retention Errors Events (all banks): $errors_found\n";
if ($errors_found == 0) {
# Fail, errors expected but not found.
exit -1;
}
# Success, at least one error was found.
exit 0;

24
DRAMSys/tests/simple/expected.txt
View File

@@ -1,24 +0,0 @@
sim.dram0 Total Energy: 4300303.75 pJ
sim.dram0 Average Power: 12.62 mW
sim.dram0 Total Time: 340669248 ps
sim.dram0 AVG BW: 1.00 Gibit/s (4.81 %)
sim.dram0 AVG BW/IDLE: 10.64 Gibit/s (51.27 %)
sim.dram0 MAX BW: 20.75 Gibit/s
sim.dram1 Total Energy: 2157481.55 pJ
sim.dram1 Average Power: 6.40 mW
sim.dram1 Total Time: 0 s
sim.dram1 AVG BW: -nan Gibit/s (-nan %)
sim.dram1 AVG BW/IDLE: -nan Gibit/s (-nan %)
sim.dram1 MAX BW: 20.75 Gibit/s
sim.dram2 Total Energy: 4202780.15 pJ
sim.dram2 Average Power: 12.34 mW
sim.dram2 Total Time: 340115040 ps
sim.dram2 AVG BW: 0.75 Gibit/s (3.63 %)
sim.dram2 AVG BW/IDLE: 15.65 Gibit/s (75.44 %)
sim.dram2 MAX BW: 20.75 Gibit/s
sim.dram3 Total Energy: 2293679.84 pJ
sim.dram3 Average Power: 6.81 mW
sim.dram3 Total Time: 312862464 ps
sim.dram3 AVG BW: 0.03 Gibit/s (0.14 %)
sim.dram3 AVG BW/IDLE: 9.21 Gibit/s (44.40 %)
sim.dram3 MAX BW: 20.75 Gibit/s

15
DRAMSys/tests/simple/fifoStrict.xml
View File

@@ -1,15 +0,0 @@
<mcconfig>
<BankwiseLogic value="0"/>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
<Scheduler value="FifoStrict" />
<Capsize value="5" />
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Error Modelling -->
<ErrorChipSeed value="42" />
<ErrorCSVFile value="../../DRAMSys/library/src/error/error.csv" />
<!-- Modes: NoStorage, Store (store data without errormodel), ErrorModel (store data with errormodel) -->
<StoreMode value="NoStorage" />
</mcconfig>

52
DRAMSys/tests/simple/sim-batch.xml
View File

@@ -1,52 +0,0 @@
<simulation>
<!-- General Simulator Configuration (used for all simulation setups) -->
<simconfig>
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "0" />
<WindowSize value="1000" />
<NumberOfTracePlayers value="1"/>
<NumberOfMemChannels value="4"/>
<ControllerCoreRefDisable value="0"/>
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfDevicesOnDIMM value = "1" />
<CheckTLM2Protocol value = "0" />
</simconfig>
<!-- Temperature Simulator Configuration (used for all simulation setups) -->
<thermalsimconfig>
<TemperatureScale value="Celsius" />
<StaticTemperatureDefaultValue value="89" />
<ThermalSimPeriod value="10" />
<ThermalSimUnit value="ms" />
<PowerInfoFile value="../../DRAMSys/library/resources/configs/thermalsim/powerInfo.xml"/>
<IceServerIp value="127.0.0.1" />
<IceServerPort value="11880" />
<SimPeriodAdjustFactor value="10" />
<NPowStableCyclesToIncreasePeriod value="5" />
<GenerateTemperatureMap value="1" />
<GeneratePowerMap value="1" />
</thermalsimconfig>
<memspecs>
<memspec src="../../DRAMSys/library/resources/configs/memspecs/WideIO.xml"></memspec>
</memspecs>
<addressmappings>
<addressmapping src="../../DRAMSys/library/resources/configs/amconfigs/am_wideio.xml"></addressmapping>
</addressmappings>
<mcconfigs>
<mcconfig src="../../DRAMSys/tests/simple/fifoStrict.xml"/>
</mcconfigs>
<tracesetups>
<tracesetup id="simple_test_fifoStrict_chstone-adpcm_32">
<device clkMhz="200">chstone-adpcm_32.stl</device>
</tracesetup>
</tracesetups>
</simulation>

57
DRAMSys/tests/simple/test.pl
View File

@@ -1,57 +0,0 @@
#!/usr/bin/perl -w
# Copyright (c) 2015, University of Kaiserslautern
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors:
# Matthias Jung
#
# Test Simple:
# This test runs the simulation with standard configuration
use File::Compare;
# Run Simulation:
chdir("../../../build/simulator/");
`./DRAMSys ../../DRAMSys/tests/simple/sim-batch.xml > ../../DRAMSys/tests/simple/output.txt`;
chdir("../../DRAMSys/tests/simple");
`cat output.txt | tail -n 24 > current.txt`;
if(compare("current.txt","expected.txt") == 0)
{
exit 0
}
else
{
exit -1
}

133
DRAMSys/tests/start.pl
View File

@@ -1,133 +0,0 @@
#!/usr/bin/perl -w
# Copyright (c) 2015, University of Kaiserslautern
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors:
# Matthias Jung
# Eder F. Zulian
# Thanh C. Tran
#
use warnings;
use strict;
use Term::ANSIColor;
use Time::localtime;
use Config;
my $pathSelector = shift || "";
if($pathSelector eq "absolute")
{
chdir("/home/test_dramsys/dram.sys/DRAMSys/tests") || die("chdir");
}
my $timestamp_color = "green";
print color("red")," |||\n";
print color("red")," +---+ Microelectronic Systems\n";
print color("red"),"=| |= Design Research Group\n";
print color("red"),"=| |= ", color("blue"),"University of Kaiserslautern\n";
print color("red")," +---+\n";
print color("red")," ||| ", color("green"),"DRAMSys Automated Test System\n", color("reset");
# Get number of Cores:
my $numberOfCores;
if ($Config{osname} eq "darwin")
{
$numberOfCores = `sysctl -n hw.ncpu`;
}
elsif ($Config{osname} eq "linux")
{
$numberOfCores = `cat /proc/cpuinfo | grep processor | wc -l`;
}
# Navigate to Build Folder
chdir("../../") || die("chdir");
`mkdir build >/dev/null 2>&1`;
chdir("build/") || die("chdir");
# Build the Project:
my $starttime = time();
print "\n", color($timestamp_color), timestamp(), color("reset"),"Build Project\t";
`qmake ../DRAMSys/DRAMSys.pro >/dev/null 2>&1`;
`make -j$numberOfCores > /dev/null 2>&1`;
my $took = time() - $starttime;
# Check if Build was sucessful:
if( -e "./simulator/DRAMSys" )
{
print color("reset"),"[ ", color("green"), "done", color("reset"), " ]\t", "(", $took, " seconds)\n";
}
else
{
print color("reset"),"[ ", color("red"), "fail", color("reset"), " ]\t", "(", $took, " seconds)\n";
exit -1;
}
# Find all tests:
# Navigate to Build Folder
chdir("../DRAMSys/tests") || die("chdir");
my @tests = split(/\n/,`find . -iname test.pl`);
# Run Tests:
foreach(@tests)
{
if($_ =~ /\.\/([\w\d]+)\/test\.pl/)
{
my $name = $1;
chdir("./$name") || die("chdir");
print color($timestamp_color), timestamp(), color("reset"),"Test: ".$name."\t";
$starttime = time();
`perl test.pl`;
$took = time() - $starttime;
if( $? == 0 )
{
print color("reset"),"[ ", color("green"), "done", color("reset"), " ]\t", "(", $took, " seconds)\n";
}
else
{
print color("reset"),"[ ", color("red"), "fail", color("reset"), " ]\t", "(", $took, " seconds)\n";
}
chdir("../") || die("chdir");
}
else
{
exit -1;
}
}
sub timestamp {
my $t = localtime;
return sprintf( "[%04d-%02d-%02d %02d:%02d:%02d]\t",
$t->year + 1900, $t->mon + 1, $t->mday,
$t->hour, $t->min, $t->sec );
}

46
DRAMSys/tests/tests.pri
View File

@@ -1,46 +0,0 @@
# Relative paths to "DRAMSys" because this file is included in
# "DRAMSys/DRAMSys.pro"
DISTFILES += tests/start.pl
# DDR:
DISTFILES += tests/DDR3/ci.yml
DISTFILES += tests/DDR3/configs/amconfigs/*
DISTFILES += tests/DDR3/configs/mcconfigs/*
DISTFILES += tests/DDR3/configs/memspecs/*
DISTFILES += tests/DDR3/configs/simulator/*
DISTFILES += tests/DDR3/configs/thermalsim/*
DISTFILES += tests/DDR3/expected/*
DISTFILES += tests/DDR3/scripts/*
DISTFILES += tests/DDR3/simulations/*
DISTFILES += tests/DDR3/traces/*
# simple test
DISTFILES += tests/simple/sim-batch.xml
DISTFILES += tests/simple/fifoStrict.xml
DISTFILES += tests/simple/test.pl
DISTFILES += tests/simple/expected.txt
# error test
DISTFILES += tests/error/sim-batch.xml
DISTFILES += tests/error/test.pl
DISTFILES += tests/error/am_wideio.xml
DISTFILES += tests/error/fr_fcfs.xml
DISTFILES += tests/error/generateErrorTest.pl
DISTFILES += tests/error/WideIO.xml
# timing compliance test
DISTFILES += tests/timing_compliance/sim-batch.xml
DISTFILES += tests/timing_compliance/fifoStrict.xml
DISTFILES += tests/timing_compliance/test.pl
# TLM compliance test
DISTFILES += tests/TLM_compliance/sim-batch.xml
DISTFILES += tests/TLM_compliance/fifoStrict.xml
DISTFILES += tests/TLM_compliance/test.pl
# python continuous testing
DISTFILES += tests/continuous_testing_py/autotest.py
DISTFILES += tests/continuous_testing_py/baseconfig_expected.out
DISTFILES += tests/continuous_testing_py/baseconfig.xml
DISTFILES += tests/continuous_testing_py/memutil.py

15
DRAMSys/tests/timing_compliance/fifoStrict.xml
View File

@@ -1,15 +0,0 @@
<mcconfig>
<BankwiseLogic value="1"/>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
<Scheduler value="FifoStrict" />
<Capsize value="5" />
<PowerDownMode value="TimeoutSREF" />
<PowerDownTimeout value="100" />
<!-- Error Modelling -->
<ErrorChipSeed value="42" />
<ErrorCSVFile value="../../DRAMSys/library/src/error/error.csv" />
<!-- Modes: NoStorage, Store (store data without errormodel), ErrorModel (store data with errormodel) -->
<StoreMode value="NoStorage" />
</mcconfig>

52
DRAMSys/tests/timing_compliance/sim-batch.xml
View File

@@ -1,52 +0,0 @@
<simulation>
<!-- General Simulator Configuration (used for all simulation setups) -->
<simconfig>
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="0" />
<EnableWindowing value = "0" />
<WindowSize value="1000" />
<NumberOfTracePlayers value="1"/>
<NumberOfMemChannels value="4"/>
<ControllerCoreRefDisable value="0"/>
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfDevicesOnDIMM value = "1" />
<CheckTLM2Protocol value = "0" />
</simconfig>
<!-- Temperature Simulator Configuration (used for all simulation setups) -->
<thermalsimconfig>
<TemperatureScale value="Celsius" />
<StaticTemperatureDefaultValue value="89" />
<ThermalSimPeriod value="10" />
<ThermalSimUnit value="ms" />
<PowerInfoFile value="../../DRAMSys/library/resources/configs/thermalsim/powerInfo.xml"/>
<IceServerIp value="127.0.0.1" />
<IceServerPort value="11880" />
<SimPeriodAdjustFactor value="10" />
<NPowStableCyclesToIncreasePeriod value="5" />
<GenerateTemperatureMap value="1" />
<GeneratePowerMap value="1" />
</thermalsimconfig>
<memspecs>
<memspec src="../../DRAMSys/library/resources/configs/memspecs/WideIO.xml"></memspec>
</memspecs>
<addressmappings>
<addressmapping src="../../DRAMSys/library/resources/configs/amconfigs/am_wideio.xml"></addressmapping>
</addressmappings>
<mcconfigs>
<mcconfig src="../../DRAMSys/tests/timing_compliance/fifoStrict.xml"/>
</mcconfigs>
<tracesetups>
<tracesetup id="timing_compliance_test_fifoStrict">
<device clkMhz="200">chstone-jpeg_32.stl</device>
</tracesetup>
</tracesetups>
</simulation>

100
DRAMSys/tests/timing_compliance/test.pl
View File

@@ -1,100 +0,0 @@
#!/usr/bin/perl -w
# Copyright (c) 2016, University of Kaiserslautern
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors:
# Matthias Jung, Felipe S. Prado, Thanh C. Tran
#
# Test Timing Compliance:
# This test runs the simulation with standard configuration
# Run Simulation:
$bankwiseLogicLine = `grep -n '<BankwiseLogic value=' fifoStrict.xml | cut -d: -f 1`;
chomp $bankwiseLogicLine;
$powerAnalysisLine = `grep -n '<PowerAnalysis value=' sim-batch.xml | cut -d: -f 1`;
chomp $powerAnalysisLine;
$powerDownModeLine = `grep -n '<PowerDownMode value=' fifoStrict.xml | cut -d: -f 1`;
chomp $powerDownModeLine;
$powerDownModes = `grep 'enum class EPowerDownMode' ../../library/src/controller/core/configuration/Configuration.h | cut -d } -f 1 | sed 's/ //g' | cut -d { -f 2`;
@powerDownModes = split(/,/,$powerDownModes);
chomp @powerDownModes;
chdir("../../../build/simulator/");
foreach (@powerDownModes)
{
system("sed -i.bu '" . $powerAnalysisLine . "s^.*^ <PowerAnalysis value=\"1\" />^' ../../DRAMSys/tests/timing_compliance/sim-batch.xml");
system("sed -i.bu '" . $bankwiseLogicLine . "s^.*^ <BankwiseLogic value=\"0\"/>^' ../../DRAMSys/tests/timing_compliance/fifoStrict.xml");
system("sed -i.bu '" . $powerDownModeLine . "s^.*^ <PowerDownMode value=\"$_\" />^' ../../DRAMSys/tests/timing_compliance/fifoStrict.xml");
`./DRAMSys ../../DRAMSys/tests/timing_compliance/sim-batch.xml`;
@files = `ls sim-batch/timing_compliance_test_fifoStrict_channel*.tdb`;
chomp @files;
foreach (@files)
{
`python3.5 ../../DRAMSys/traceAnalyzer/scripts/tests.py $_ > ../../DRAMSys/tests/timing_compliance/output.txt`;
if("All tests passed\n" ne `grep "All tests passed" ../../DRAMSys/tests/timing_compliance/output.txt`)
{
clean_backup_files();
exit -1;
}
}
system("sed -i.bu '" . $powerAnalysisLine . "s^.*^ <PowerAnalysis value=\"0\" />^' ../../DRAMSys/tests/timing_compliance/sim-batch.xml");
system("sed -i.bu '" . $bankwiseLogicLine . "s^.*^ <BankwiseLogic value=\"1\"/>^' ../../DRAMSys/tests/timing_compliance/fifoStrict.xml");
`./DRAMSys ../../DRAMSys/tests/timing_compliance/sim-batch.xml`;
foreach (@files)
{
`python3.5 ../../DRAMSys/traceAnalyzer/scripts/tests.py $_ > ../../DRAMSys/tests/timing_compliance/output.txt`;
if("All tests passed\n" ne `grep "All tests passed" ../../DRAMSys/tests/timing_compliance/output.txt`)
{
clean_backup_files();
exit -1;
}
}
}
clean_backup_files();
exit 0;
sub clean_backup_files {
`rm -rf ../../DRAMSys/tests/timing_compliance/sim-batch.xml.bu`;
`rm -rf ../../DRAMSys/tests/timing_compliance/fifoStrict.xml.bu`;
}