Files
DRAMSys/DRAMSys/tests/timing_compliance/sim-batch.xml
Éder F. Zulian c6e66305c1 Standard nomenclature for refresh related configs.
ControllerCoreRef* for refresh general configs.
ControllerCoreRGR* for RGR specific configs.
2018-07-10 09:44:48 +02:00

53 lines
1.8 KiB
XML

<simulation>
<!-- General Simulator Configuration (used for all simulation setups) -->
<simconfig>
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="0" />
<EnableWindowing value = "0" />
<WindowSize value="1000" />
<NumberOfTracePlayers value="1"/>
<NumberOfMemChannels value="4"/>
<ControllerCoreRefDisable value="0"/>
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfDevicesOnDIMM value = "1" />
<CheckTLM2Protocol value = "0" />
</simconfig>
<!-- Temperature Simulator Configuration (used for all simulation setups) -->
<thermalsimconfig>
<TemperatureScale value="Celsius" />
<StaticTemperatureDefaultValue value="89" />
<ThermalSimPeriod value="10" />
<ThermalSimUnit value="ms" />
<PowerInfoFile value="../../DRAMSys/library/resources/configs/thermalsim/powerInfo.xml"/>
<IceServerIp value="127.0.0.1" />
<IceServerPort value="11880" />
<SimPeriodAdjustFactor value="10" />
<NPowStableCyclesToIncreasePeriod value="5" />
<GenerateTemperatureMap value="1" />
<GeneratePowerMap value="1" />
</thermalsimconfig>
<memspecs>
<memspec src="../../DRAMSys/library/resources/configs/memspecs/WideIO.xml"></memspec>
</memspecs>
<addressmappings>
<addressmapping src="../../DRAMSys/library/resources/configs/amconfigs/am_wideio.xml"></addressmapping>
</addressmappings>
<mcconfigs>
<mcconfig src="../../DRAMSys/tests/timing_compliance/fifoStrict.xml"/>
</mcconfigs>
<tracesetups>
<tracesetup id="timing_compliance_test_fifoStrict">
<device clkMhz="200">chstone-jpeg_32.stl</device>
</tracesetup>
</tracesetups>
</simulation>