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Merge branch 'readme_updates2' into 'development'

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Readme updates.

See merge request ems/astdm/dram.sys!257
This commit is contained in:
Lukas Steiner
2020-07-02 15:22:45 +02:00
parent 8dd4f3f702 7b4aeaf663
commit 3a03119d78
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coverage: '/Total:\|(\d+\.?\d+\%)/'
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## DRAMSys with gem5
Install gem5 by following the instructions on the [gem5 wiki](http://gem5.org/Documentation#Getting_Started).
Optionally, use the scripts from [gem5.TnT] to install gem5, build it, get some benchmark programs and learn more about gem5.
In order to understand the SystemC coupling with gem5 it is recommended to
read the documentation in the gem5 repository *util/tlm/README* and [1].
The main steps for building gem5 and libgem5 follow:
```bash
scons build/ARM/gem5.opt
```
```bash
scons --with-cxx-config --without-python --without-tcmalloc build/ARM/libgem5_opt.so
```
For MacOS:
```bash
scons --with-cxx-config --without-python --without-tcmalloc build/ARM/libgem5_opt.dylib
```
In order to use gem5 with DRAMSys set the **GEM5** environment variable to the
path to gem5, for example in the *QtCreator under Projects > Build
& Run > Build Environment*:
```
GEM5=/path/to/gem5/
```
Example:
```
GEM5=$HOME/gem5_tnt/gem5
```
Optionally, export environment variables in your **~/.bashrc** file or
equivalent and open a new terminal:
```bash
# In this example gem5 is located at $HOME/gem5_tnt/gem5.
export GEM5=$HOME/gem5_tnt/gem5
# Add the folder containing libgem5_opt.so to the list where libraries should
# be searched for.
export LD_LIBRARY_PATH=${LD_LIBRARY_PATH}:${GEM5}/build/ARM
```
The project file [DRAMSys.pro](DRAMSys/DRAMSys.pro) checks whether the
environment variable **GEM5** is defined or not and configures automatically
the corresponding build target **gem5** for QtCreator.
In order to run gem5 with DRAMSys it is mandatory to run gem5 first without
DRAMSys and generate a configuration file **config.ini** which will be the
value of the second parameter passed to DRAMSys_gem5.
### DRAMSys with gem5 traffic generator
In the following we will run a simple example with a gem5 traffic generator:
```
Base System Architecture:
+-------------+ +------+ ^
| System Port | | TGEN | |
+-------+-----+ +--+---+ |
| | | gem5 World
| +----+ |
| | |
+-------v------v-------+ |
| Membus | v
+---------------+------+ External Port (see sc_slave_port.*)
| ^
+----v----+ | TLM World
| DRAMSys | | (see sc_target.*)
+---------+ v
```
As mentioned before we first need to create a config.ini
that represents the gem5 configuration. We do so by starting gem5 with the
desired python configuration script.
```bash
cd gem5/utils/tlm/
../../build/ARM/gem5.opt conf/tlm_slave.py
```
**Ignore the message below.**
```
"fatal: Can't find port handler type 'tlm_slave'"
```
The configuration file config.ini will be stored in the **m5out** directory.
Copy this configuration file to the building directory of DRAMSys where the
executable **DRAMSys_gem5** is located:
```
dram.sys/build-DRAMSys-Desktop_Qt_5_7_0_clang_64bit-Debug/gem5
```
Also the traffic generatior configuration file (conf/tgen.cfg) must be stored
in a conf directory of this building directory.
Then the simulation can be started with:
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.json config.ini 1
```
Let the simulation run for some seconds and then stop it with **CTRL-C**.
Observe the output of the simulation in the trace analyzer. The trace database
can be found inside the gem5 directory in the building directory.
### Gem5 SE mode and DRAMSys
All essential files for some functional examples are provided.
Execute a hello world application:
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/configs/hello.ini 1
```
A **Hello world!** message should be printed to the standard output.
Execute applications:
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/Oscar/config.ini 1
```
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/Bubblesort/config.ini 1
```
Wait some minutes for the application to finish.
The hello application binary was copied from gem5 repository.
Other applications were obtained with [gem5.TnT].
Command template for generating **.ini** configuration files follows:
```bash
build/ARM/gem5.opt configs/example/se.py \
-c <application> --mem-size=512MB --mem-channels=1 \
--caches --l2cache --mem-type=SimpleMemory \
--cpu-type=TimingSimpleCPU --num-cpu=1 \
--tlm-memory=transactor
```
An overview of the architcture being simulated is presented below:
![arch](images/gem5_se_mode_arch.png)
**Note**: this is a gem5 generated file, therefore DRAMSys is omitted. DRAMSys is
direct connected as external tlm slave.
**Note**: workaround in se.py required:
```python
...
if options.tlm_memory:
system.physmem = SimpleMemory()
MemConfig.config_mem(options, system)
...
```
A convenience script to execute several applications automatically
[**run.sh**](DRAMSys/gem5/gem5_se/run.sh) is provided . Take a look and learn
from it.
### [PARSEC] FS Mode
Full system simulation files for ARM available in [DRAMSys/gem5/gem5_fs/parsec_arm_minor_2c_8GB](DRAMSys/gem5/gem5_fs/parsec_arm_minor_2c_8GB).
Choose the benchmark in [parsec_arm_minor_2c_8GB.rcS](DRAMSys/gem5/gem5_fs/parsec_arm_minor_2c_8GB/parsec_arm_minor_2c_8GB.rcS).
Edit the paths in [config.ini](DRAMSys/gem5/gem5_fs/parsec_arm_minor_2c_8GB/config.ini).
All files required to build DRAMSys_gem5 and execute the simulation (gem5
library, benchmarks, disk image, etc.) can be obtained with [gem5.TnT].
Start a simulation. Example:
```bash
dram.sys/build/gem5$ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/rgrsim-gem5-fs.json ../../DRAMSys/gem5/gem5_fs/parsec_arm_minor_2c_8GB/config.ini 1
```
Optionally, open another terminal or tab and connect to gem5.
```bash
$ telnet localhost 3456
```
Note: the port may vary, gem5 prints it during initialization. Example:
```
system.terminal: Listening for connections on port 3456
```
### [PARSEC] SE Mode
Binaries and gem5 SE configuration files for ARM available in [DRAMSys/gem5/gem5_se/parsec-arm](DRAMSys/gem5/gem5_se/parsec-arm).
Use [gem5.TnT] to download parsec. Example:
Go to your **gem5.TnT** folder. Then go to **arch/arm** folder. Execute the
script *build-parsec-serial.sh*.
```bash
gem5.TnT/arch/arm$ ./build-parsec-serial.sh
```
Extract inputs files. Example:
```bash
cd $HOME/gem5_tnt/benchmarks/parsec-3.0/pkgs/kernels/canneal/inputs
tar -xf input_simdev.tar
tar -xf input_test.tar
tar -xf input_simmedium.tar
tar -xf input_simsmall.tar
tar -xf input_native.tar
tar -xf input_simlarge.tar
cd $HOME/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/fluidanimate/inputs
tar -xf input_simdev.tar
tar -xf input_test.tar
tar -xf input_native.tar
tar -xf input_simlarge.tar
tar -xf input_simmedium.tar
tar -xf input_simsmall.tar
cd $HOME/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/blackscholes/inputs
tar -xf input_simdev.tar
tar -xf input_test.tar
tar -xf input_native.tar
tar -xf input_simlarge.tar
tar -xf input_simmedium.tar
tar -xf input_simsmall.tar
```
Open [DRAMSys/gem5/gem5_se/parsec-arm/config.ini](DRAMSys/gem5/gem5_se/parsec-arm/config.ini)
Edit **cmd=**.
Edit **executable=**.
Examples (**Replace USER. Use the correct path in your computer.**):
```
-- canneal --
cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/canneal/canneal 1 5 100 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/kernels/canneal/inputs/10.nets 1
cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/canneal/canneal 1 100 300 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/kernels/canneal/inputs/100.nets 2
cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/canneal/canneal 1 10000 2000 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/kernels/canneal/inputs/100000.nets 32
cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/canneal/canneal 1 15000 2000 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/kernels/canneal/inputs/200000.nets 64
cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/canneal/canneal 1 15000 2000 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/kernels/canneal/inputs/400000.nets 128
executable=../../DRAMSys/gem5/gem5_se/parsec-arm/canneal/canneal
-- streamcluster --
cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/streamcluster/streamcluster 2 5 1 10 10 5 none output.txt 1
cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/streamcluster/streamcluster 3 10 3 16 16 10 none output.txt 1
cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/streamcluster/streamcluster 10 20 32 4096 4096 1000 none output.txt 1
cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/streamcluster/streamcluster 10 20 64 8192 8192 1000 none output.txt 1
cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/streamcluster/streamcluster 10 20 128 16384 16384 1000 none output.txt 1
cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/streamcluster/streamcluster 10 20 128 1000000 200000 5000 none output.txt 1
executable=../../DRAMSys/gem5/gem5_se/parsec-arm/streamcluster/streamcluster
-- swaptions --
cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/swaptions/swaptions -ns 1 -sm 5 -nt 1
cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/swaptions/swaptions -ns 3 -sm 50 -nt 1
cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/swaptions/swaptions -ns 16 -sm 5000 -nt 1
cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/swaptions/swaptions -ns 32 -sm 10000 -nt 1
cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/swaptions/swaptions -ns 64 -sm 20000 -nt 1
executable=../../DRAMSys/gem5/gem5_se/parsec-arm/swaptions/swaptions
-- fluidanimate --
cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/fluidanimate/fluidanimate 1 1 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/fluidanimate/inputs/in_5K.fluid out.fluid
cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/fluidanimate/fluidanimate 1 3 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/fluidanimate/inputs/in_15K.fluid out.fluid
cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/fluidanimate/fluidanimate 1 5 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/fluidanimate/inputs/in_35K.fluid out.fluid
cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/fluidanimate/fluidanimate 1 5 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/fluidanimate/inputs/in_100K.fluid out.fluid
cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/fluidanimate/fluidanimate 1 5 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/fluidanimate/inputs/in_300K.fluid out.fluid
executable=../../DRAMSys/gem5/gem5_se/parsec-arm/fluidanimate/fluidanimate
-- blackscholes --
cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/blackscholes/blackscholes 1 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/blackscholes/inputs/in_4.txt prices.txt
cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/blackscholes/blackscholes 1 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/blackscholes/inputs/in_16.txt prices.txt
cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/blackscholes/blackscholes 1 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/blackscholes/inputs/in_4K.txt prices.txt
cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/blackscholes/blackscholes 1 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/blackscholes/inputs/in_16K.txt prices.txt
cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/blackscholes/blackscholes 1 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/blackscholes/inputs/in_64K.txt prices.txt
executable=../../DRAMSys/gem5/gem5_se/parsec-arm/blackscholes/blackscholes
```
Start a simulation. Example:
```bash
dram.sys/build/gem5$ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/rgrsim-gem5-se.json ../../DRAMSys/gem5/gem5_se/parsec-arm/config.ini 1
```
### Boot Linux with gem5 and DRAMSys
The procedure is very similar to the traffic generator example above.
First we have to generate the config.ini file by starting gem5 with the following configuration:
```bash
build/ARM/gem5.opt configs/example/fs.py \
--tlm-memory=transactor --cpu-type=TimingSimpleCPU --num-cpu=1 \
--mem-type=SimpleMemory --mem-size=512MB --mem-channels=1 --caches \
--l2cache --machine-type=VExpress_EMM \
--dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \
--kernel=vmlinux.aarch32.ll_20131205.0-gem5 \
--disk-image=linux-aarch32-ael.img
```
The config.ini should be copied again to the DRAMSys_gem5 build folder.
The simconfig should be changed in order to support storage and address offsets:
``` json
{
"simconfig": {
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"Debug": false,
"ECCControllerMode": "Disabled",
"EnableWindowing": false,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": 8,
"NumberOfMemChannels": 1,
"PowerAnalysis": false,
"SimulationName": "ddr3",
"SimulationProgressBar": true,
"ThermalSimulation": false,
"WindowSize": 1000,
"StoreMode": "Store",
"AddressOffset": 2147483648,
"UseMalloc": true
}
}
```
Then start DRAMSys_gem5 with the following command:
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.json config.ini 1
```
For further sophisticated address mappings or scenarios checkout the file DRAMSys/gem5/main.cpp
#### Boot Linux with gem5 and DRAMSys Example
**All essential files for a functional example are provided.**
Unzip the disk image:
```bash
tar -xaf DRAMSys/gem5/boot_linux/linux-aarch32-ael.img.tar.gz -C DRAMSys/gem5/boot_linux/
```
Execute the example:
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-boot-linux.json ../../DRAMSys/gem5/configs/boot_linux.ini 1
```
Open a new terminal and connect to gem5:
```bash
telnet localhost 3456
```
Wait some minutes for the Linux boot process to complete then login. Username is
**root** no password required.
### DRAMSys with gem5 Elastic Traces
For understanding elastic traces and their generation, study the [gem5
wiki](http://gem5.org/TraceCPU) and the paper [2].
Some predefined configs are stored [here](DRAMSys/gem5/configs) and the related
python files are stored [here](DRAMSys/gem5/examples).
This is an example for running an elastic trace:
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.json ../../DRAMSys/gem5/configs/singleElasticTraceReplay.ini 1
```
An overview of the architcture being simulated is presented below:
![arch](images/singleElasticTraceReplay.png)
Note that the address offset is usually zero for elastic traces.
Another example with L2 cache:
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.json ../../DRAMSys/gem5/configs/singleElasticTraceReplayWithL2.ini 1
```
If two elastic traces should be used run the simulation with the following example:
```
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.json ../../DRAMSys/gem5/configs/dualElasticTraceReplay.ini 2
```
An overview of the architcture being simulated is presented below:
![arch](images/dualElasticTraceReplay.png)
For more spophisticated setups, even with l2 caches the proper ini file should be created.
If you need help please contact Matthias Jung.
### DRAMSys + GEM5 Log Collector Scripts
Users can profit of running multiple **DRAMSys + gem5** simulations
automatically with [gem5ilva.sh] for **gem5 syscall emulation (SE) mode** and
[gem5ilva_fs.sh] for **gem5 full system (FS) mode**.
Normally you will have to push your changes before running the scripts. This
approach makes it easier to track back what exactly was tested by the scripts.
The scripts provide variables that tell **git** where to get the source
code from (repository URL), user name to be used (your git account),
**branch** to checkout (your working branch), etc. They are:
```bash
# Git info.
git_user="$USER"
git_branch="master"
git_url="git.eit.uni-kl.de:ems/astdm/dram.sys.git"
git_url_https="git.eit.uni-kl.de/ems/astdm/dram.sys.git"
```
The default values of the variables presented above assume that your git
account uses the same name as your user name in your PC. If that is not the
case, replace the value of the **git_user** variable with your git account
name. Similarly, replace the value of the variable **git_branch** with your
working branch name. There (in your working branch) you can push your changes
and/or new files before executing the scripts.
Open the script in QtCreator or another text editor of your choice and set the
variables with values that fit your needs.
Nevertheless, for some cases, you may want to have gem5 essential files out of
the main repository (usually because they are too big to be added to the
repository).
For those cases uncomment and properly set the variable
**external_inifile_path** in [gem5ilva_fs.sh].
This allows you to use a gem5 **config.ini** file external to the repository.
Note, however, that in this case it is up to you to keep track of your
simulation setup.
**Hint:**
[gem5.TnT] provides convenience scripts
to create gem5 disk images with benchmarking programs embedded.
### Coverage Check
Coverage check is enabled by default and can be disabled with an environment
variable.
```bash
export COVERAGE=true
```
### DRAMSys + GEM5 x86
Make sure you have built **gem5/build/X86/libgem5_opt.so**. If you build with
[gem5.TnT] you can check if the library exists as follows.
```bash
$ ls $HOME/gem5_tnt/gem5/build/X86/libgem5_opt.so
```
Change your ~/.bashrc.
```bash
# In this example gem5 is located at $HOME/gem5_tnt/gem5.
export GEM5=$HOME/gem5_tnt/gem5
# Add the folder containing libgem5_opt.so to the list where libraries should
# be searched for.
#export LD_LIBRARY_PATH=${LD_LIBRARY_PATH}:${GEM5}/build/ARM
export LD_LIBRARY_PATH=${LD_LIBRARY_PATH}:${GEM5}/build/X86
```
After that close QtCreator and all terminals.
Open a new terminal.
Change the architecture in [DRAMSys/gem5/gem5.pro](DRAMSys/gem5/gem5.pro).
```
gem5_arch = 'X86'
```
Delete the file **DRAMSys/DRAMSys.pro.user** from the repository.
```bash
$ rm DRAMSys/DRAMSys.pro.user
```
Open a new QtCreator.
Build DRAMSys as usual.
After building, go the the folder where *DRAMSys_gem5* is located.
Test with a hello world application for X86.
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/hello-x86/config.ini 1
```
A **Hello world!** message should be printed to the standard output.
### [MiBench]
Applications for x86 and configuration files available in [DRAMSys/gem5/gem5_se/MiBench](DRAMSys/gem5/gem5_se/MiBench).
Examples:
**Automotive Applications**
**Basicmath**
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/basicmath/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/basicmath/large/config.ini 1
```
**Bitcount**
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/bitcount/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/bitcount/large/config.ini 1
```
**Qsort**
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/qsort/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/qsort/large/config.ini 1
```
**Susan**
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/small/corners/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/large/corners/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/small/edges/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/large/edges/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/small/smoothing/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/large/smoothing/config.ini 1
```
**Network Applications**
**Dijkstra**
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/network/dijkstra/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/network/dijkstra/large/config.ini 1
```
**Patricia**
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/network/patricia/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/network/patricia/large/config.ini 1
```
**Security Applications**
**Blowfish Encode**
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/encode/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/encode/large/config.ini 1
```
**Blowfish Decode**
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/decode/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/decode/large/config.ini 1
```
**SHA**
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/sha/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/sha/large/config.ini 1
```
**Telecom Applications**
**CRC32**
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/crc32/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/crc32/large/config.ini 1
```
**FFT**
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft/large/config.ini 1
```
**FFT-INV**
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft-inv/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft-inv/large/config.ini 1
```
**GSM Encode**
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/encode/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/encode/large/config.ini 1
```
**GSM Decode**
```bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/decode/small/config.ini 1
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/decode/large/config.ini 1
```
Check the folder [DRAMSys/gem5/gem5_se/MiBench](DRAMSys/gem5/gem5_se/MiBench) for all applications and configuration files.
### More AARCH64 Apps
Full system simulation files for ARM available in [DRAMSys/gem5/gem5_fs/arm64](DRAMSys/gem5/gem5_fs/arm64).
You can edit [arm64.rcS](DRAMSys/gem5/gem5_fs/arm64/arm64.rcS) to start an application and call *m5 exit* when it finishes.
Edit the paths in [config.ini](DRAMSys/gem5/gem5_fs/arm64/config.ini).
All files required to build DRAMSys_gem5 and execute the simulation (gem5
library, benchmarks, disk image, etc.) can be obtained with [gem5.TnT].
Start a simulation. Example:
```bash
dram.sys/build/gem5$ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/rgrsim-gem5-fs.json ../../DRAMSys/gem5/gem5_fs/arm64/config.ini 1
```
Optionally, open another terminal or tab and connect to gem5.
```bash
$ telnet localhost 3456
```
Note: the port may vary, gem5 prints it during initialization. Example:
```
system.terminal: Listening for connections on port 3456
```
[1] System Simulation with gem5 and SystemC: The Keystone for Full Interoperability
C. Menard, M. Jung, J. Castrillon, N. Wehn. IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2017, Samos Island, Greece.
[2] Exploring System Performance using Elastic Traces: Fast, Accurate and Portable
R. Jagtap, S. Diestelhorst, A. Hansson, M. Jung, N. Wehn, IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), 2016, Samos Island, Greece.
[gem5.TnT]: https://github.com/tukl-msd/gem5.TnT
[gem5ilva.sh]: DRAMSys/library/resources/scripts/DRAMSylva/gem5ilva.sh
[gem5ilva_fs.sh]: DRAMSys/library/resources/scripts/DRAMSylva/gem5ilva_fs.sh
[Elwetritsch]: https://elwe.rhrk.uni-kl.de/
[DRAMSylva.sh]: DRAMSys/library/resources/scripts/DRAMSylva/DRAMSylva.sh
[DRAMSylva folder]: DRAMSys/library/resources/scripts/DRAMSylva
[configs_json]: DRAMSys/library/resources/scripts/DRAMSylva/configs_json
[MiBench]: http://vhosts.eecs.umich.edu/mibench/
[PARSEC]: http://parsec.cs.princeton.edu/

0
DRAMSys/docs/images/gem5_se_mode_arch.svg → DRAMSys/gem5/images/gem5_se_mode_arch.svg
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4
DRAMSys/library/CMakeLists.txt
View File

@@ -288,8 +288,8 @@ add_library(DRAMSysLibrary
resources/traces/chstone-adpcm_32.stl
)
if(DEFINED ENV{LIBTHREED_ICE_HOME} AND DEFINED ENV{LIBSUPERLU_HOME})
message("-- 3D-ICE and SuperLU available")
if(DEFINED ENV{LIBTHREED_ICE_HOME})
message("-- Thermal simulation available")
add_definitions(-DTHERMALSIM)
target_include_directories(DRAMSysLibrary
PRIVATE $ENV{LIBTHREED_ICE_HOME}/include/

1
DRAMSys/library/resources/configs/mcconfigs/fifo.json
View File

@@ -6,7 +6,6 @@
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "Rankwise",
"RefreshMode": 1,
"RefreshMaxPostponed": 8,
"RefreshMaxPulledin": 8,
"PowerDownPolicy": "NoPowerDown",

1
DRAMSys/library/resources/configs/mcconfigs/fifoStrict.json
View File

@@ -6,7 +6,6 @@
"CmdMux": "Strict",
"RespQueue": "Fifo",
"RefreshPolicy": "Rankwise",
"RefreshMode": 1,
"RefreshMaxPostponed": 8,
"RefreshMaxPulledin": 8,
"PowerDownPolicy": "NoPowerDown",

1
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.json
View File

@@ -6,7 +6,6 @@
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "Rankwise",
"RefreshMode": 1,
"RefreshMaxPostponed": 8,
"RefreshMaxPulledin": 8,
"PowerDownPolicy": "NoPowerDown",

3
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.json
View File

@@ -3,10 +3,9 @@
"PagePolicy": "Open",
"Scheduler": "FrFcfsGrp",
"RequestBufferSize": 8,
"CmdMux": "Oldest",
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "Rankwise",
"RefreshMode": 1,
"RefreshMaxPostponed": 8,
"RefreshMaxPulledin": 8,
"PowerDownPolicy": "NoPowerDown",

1
DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json
View File

@@ -43,6 +43,7 @@
"RAS": 32,
"RC": 45,
"RCD": 13,
"REFM": 1,
"REFI": 7280,
"RFC": 243,
"RFC2": 150,

1
DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json
View File

@@ -43,6 +43,7 @@
"RAS": 39,
"RC": 55,
"RCD": 16,
"REFM": 1,
"REFI": 9360,
"RFC": 312,
"RFC2": 192,

1
DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json
View File

@@ -43,6 +43,7 @@
"RAS": 32,
"RC": 45,
"RCD": 13,
"REFM": 1,
"REFI": 3644,
"RFC": 243,
"RL": 13,

1
DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json
View File

@@ -43,6 +43,7 @@
"RAS": 39,
"RC": 55,
"RCD": 16,
"REFM": 1,
"REFI": 4680,
"RFC": 313,
"RL": 16,

2
DRAMSys/library/src/configuration/Configuration.cpp
View File

@@ -92,8 +92,6 @@ void Configuration::setParameter(std::string name, nlohmann::json value)
respQueue = value;
else if (name == "RefreshPolicy")
refreshPolicy = value;
else if (name == "RefreshMode")
refreshMode = value;
else if (name == "RefreshMaxPostponed")
refreshMaxPostponed = value;
else if (name == "RefreshMaxPulledin")

1
DRAMSys/library/src/configuration/Configuration.h
View File

@@ -75,7 +75,6 @@ public:
std::string respQueue = "Fifo";
unsigned int requestBufferSize = 8;
std::string refreshPolicy = "Rankwise";
unsigned int refreshMode = 1;
unsigned int refreshMaxPostponed = 0;
unsigned int refreshMaxPulledin = 0;
std::string powerDownPolicy = "NoPowerDown";

18
DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp
View File

@@ -68,16 +68,16 @@ MemSpecDDR4::MemSpecDDR4(json &memspec)
tCCD_S (tCK * parseUint(memspec["memtimingspec"]["CCD_S"], "CCD_S")),
tCCD_L (tCK * parseUint(memspec["memtimingspec"]["CCD_L"], "CCD_L")),
tFAW (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")),
tREFI ((Configuration::getInstance().refreshMode == 1) ?
(tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")) :
((Configuration::getInstance().refreshMode == 2) ?
tREFI ((parseUint(memspec["memtimingspec"]["REFM"], "REFM") == 4) ?
(tCK * (parseUint(memspec["memtimingspec"]["REFI"], "REFI") / 4)) :
((parseUint(memspec["memtimingspec"]["REFM"], "REFM") == 2) ?
(tCK * (parseUint(memspec["memtimingspec"]["REFI"], "REFI") / 2)) :
(tCK * (parseUint(memspec["memtimingspec"]["REFI"], "REFI") / 4)))),
tRFC ((Configuration::getInstance().refreshMode == 1) ?
(tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")) :
((Configuration::getInstance().refreshMode == 2) ?
(tCK * (parseUint(memspec["memtimingspec"]["RFC2"], "RFC2") / 2)) :
(tCK * (parseUint(memspec["memtimingspec"]["RFC4"], "RFC4") / 4)))),
(tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")))),
tRFC ((parseUint(memspec["memtimingspec"]["REFM"], "REFM") == 4) ?
(tCK * parseUint(memspec["memtimingspec"]["RFC4"], "RFC4")) :
((parseUint(memspec["memtimingspec"]["REFM"], "REFM") == 2) ?
(tCK * parseUint(memspec["memtimingspec"]["RFC2"], "RFC2")) :
(tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")))),
tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
tRRD_S (tCK * parseUint(memspec["memtimingspec"]["RRD_S"], "RRD_S")),
tRRD_L (tCK * parseUint(memspec["memtimingspec"]["RRD_L"], "RRD_L")),

2
DRAMSys/library/src/controller/Controller.cpp
View File

@@ -341,7 +341,7 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &trans,
timeToAcquire = sc_time_stamp() + notificationDelay;
beginReqEvent.notify(notificationDelay);
}
else if (phase = END_RESP)
else if (phase == END_RESP)
{
timeToRelease = sc_time_stamp() + notificationDelay;
endRespEvent.notify(notificationDelay);

1
DRAMSys/library/src/controller/respqueue/RespQueueIF.h
View File

@@ -44,6 +44,7 @@ public:
virtual void insertPayload(tlm::tlm_generic_payload *, sc_time) = 0;
virtual tlm::tlm_generic_payload *nextPayload() = 0;
virtual sc_time getTriggerTime() const = 0;
virtual ~RespQueueIF() {}
};
#endif // RESPQUEUEIF_H

2
DRAMSys/library/src/simulation/dram/DramRecordable.cpp
View File

@@ -57,7 +57,7 @@ DramRecordable<BaseDram>::DramRecordable(sc_module_name name, TlmRecorder *tlmRe
{
// Create a thread that is triggered every $powerWindowSize
// to generate a Power over Time plot in the Trace analyzer:
if (Configuration::getInstance().powerAnalysis)
if (Configuration::getInstance().powerAnalysis && Configuration::getInstance().enableWindowing)
SC_THREAD(powerWindow);
}

1
DRAMSys/tests/.gitignore vendored
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@@ -1 +0,0 @@
*.txt

7
DRAMSys/tests/DDR4/ci.yml
View File

@@ -1,6 +1,6 @@
# DDR4 with 4 bank groups, flexible rankwise refresh and FrFcfs scheduler:
example_ddr4:
stage: DDR4
example_DDR4:
stage: tests
script:
- export GCOV_PREFIX=$(pwd)
- export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}')
@@ -25,5 +25,4 @@ example_ddr4:
paths:
- build/simulator/ddr4-bankgrp_ddr4_ch0.tdb
- coverage/${CI_JOB_NAME}.out
expire_in: 2 days
expire_in: 2 days

1
DRAMSys/tests/DDR4/configs/mcconfigs/fr_fcfs.json
View File

@@ -5,7 +5,6 @@
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "Rankwise",
"RefreshMode": 1,
"RefreshMaxPostponed": 8,
"RefreshMaxPulledin": 8,
"PowerDownPolicy": "NoPowerDown",

3
DRAMSys/tests/DDR4/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json
View File

@@ -43,6 +43,7 @@
"RAS": 32,
"RC": 45,
"RCD": 13,
"REFM": 1,
"REFI": 3644,
"RFC": 243,
"RL": 13,
@@ -65,4 +66,4 @@
"clkMhz": 933
}
}
}
}

48
DRAMSys/tests/HBM2/ci.yml
View File

@@ -1,25 +1,25 @@
example_HBM2:
artifacts:
expire_in: "2 days"
paths:
- build/simulator/hbm2-example_hbm2_ch0.tdb
- "coverage/${CI_JOB_NAME}.out"
cache:
key: build
paths:
- build/
policy: pull
script:
- "export GCOV_PREFIX=$(pwd)"
- "export GCOV_PREFIX_STRIP=$(pwd | awk -F\"/\" '{print NF-1}')"
- "cd build/simulator"
- "./DRAMSys ../../DRAMSys/tests/HBM2/simulations/hbm2-example.json ../../DRAMSys/tests/HBM2/"
- "ls -lah"
- "ls -lah ../../DRAMSys/tests/HBM2/expected/"
- "sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch0.tdb hbm2-example_hbm2_ch0.tdb"
- "perl -e 'if(`sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch0.tdb hbm2-example_hbm2_ch0.tdb` eq \"\") {exit(0)} else {exit(-1)}'"
- "sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch1.tdb hbm2-example_hbm2_ch1.tdb"
- "perl -e 'if(`sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch1.tdb hbm2-example_hbm2_ch1.tdb` eq \"\") {exit(0)} else {exit(-1)}'"
- "lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out"
stage: HBM2
stage: tests
script:
- "export GCOV_PREFIX=$(pwd)"
- "export GCOV_PREFIX_STRIP=$(pwd | awk -F\"/\" '{print NF-1}')"
- "cd build/simulator"
- "./DRAMSys ../../DRAMSys/tests/HBM2/simulations/hbm2-example.json ../../DRAMSys/tests/HBM2/"
- "ls -lah"
- "ls -lah ../../DRAMSys/tests/HBM2/expected/"
- "sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch0.tdb hbm2-example_hbm2_ch0.tdb"
- "perl -e 'if(`sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch0.tdb hbm2-example_hbm2_ch0.tdb` eq \"\") {exit(0)} else {exit(-1)}'"
- "sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch1.tdb hbm2-example_hbm2_ch1.tdb"
- "perl -e 'if(`sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch1.tdb hbm2-example_hbm2_ch1.tdb` eq \"\") {exit(0)} else {exit(-1)}'"
- "lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out"
cache:
key: build
paths:
- build/
policy: pull
artifacts:
paths:
- build/simulator/hbm2-example_hbm2_ch0.tdb
- "coverage/${CI_JOB_NAME}.out"
expire_in: "2 days"

25
DRAMSys/tests/HBM2/configs/mcconfigs/fifoStrict.json
View File

@@ -1,11 +1,14 @@
{"mcconfig": {"PagePolicy": "Closed",
"Scheduler": "Fifo",
"RequestBufferSize": 8,
"CmdMux": "Strict",
"RespQueue": "Fifo",
"RefreshPolicy": "Rankwise",
"RefreshMode": 1,
"RefreshMaxPostponed": 0,
"RefreshMaxPulledin": 0,
"PowerDownPolicy": "NoPowerDown",
"PowerDownTimeout": 100}}
{
"mcconfig": {
"PagePolicy": "Closed",
"Scheduler": "Fifo",
"RequestBufferSize": 8,
"CmdMux": "Strict",
"RespQueue": "Fifo",
"RefreshPolicy": "NoRefresh",
"RefreshMaxPostponed": 0,
"RefreshMaxPulledin": 0,
"PowerDownPolicy": "NoPowerDown",
"PowerDownTimeout": 100
}
}

15
DRAMSys/tests/TLM_compliance/fifoStrict.xml
View File

@@ -1,15 +0,0 @@
<mcconfig>
<BankwiseLogic value="0"/>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
<Scheduler value="FifoStrict" />
<Capsize value="5" />
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Error Modelling -->
<ErrorChipSeed value="42" />
<ErrorCSVFile value="../../DRAMSys/library/src/error/error.csv" />
<!-- Modes: NoStorage, Store (store data without errormodel), ErrorModel (store data with errormodel) -->
<StoreMode value="NoStorage"/>
</mcconfig>

51
DRAMSys/tests/TLM_compliance/sim-batch.xml
View File

@@ -1,51 +0,0 @@
<simulation>
<!-- General Simulator Configuration (used for all simulation setups) -->
<simconfig>
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "0" />
<WindowSize value="1000" />
<NumberOfTracePlayers value="1"/>
<NumberOfMemChannels value="4"/>
<ControllerCoreRefDisable value="0"/>
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfDevicesOnDIMM value = "1" />
<CheckTLM2Protocol value = "1" />
</simconfig>
<!-- Temperature Simulator Configuration (used for all simulation setups) -->
<thermalsimconfig>
<TemperatureScale value="Celsius" />
<StaticTemperatureDefaultValue value="89" />
<ThermalSimPeriod value="10" />
<ThermalSimUnit value="ms" />
<PowerInfoFile value="../../DRAMSys/library/resources/configs/thermalsim/powerInfo.xml"/>
<IceServerIp value="127.0.0.1" />
<IceServerPort value="11880" />
<SimPeriodAdjustFactor value="10" />
<NPowStableCyclesToIncreasePeriod value="5" />
<GenerateTemperatureMap value="1" />
<GeneratePowerMap value="1" />
</thermalsimconfig>
<memspecs>
<memspec src="../../DRAMSys/library/resources/configs/memspecs/WideIO.xml"></memspec>
</memspecs>
<addressmappings>
<addressmapping src="../../DRAMSys/library/resources/configs/amconfigs/am_wideio.xml"></addressmapping>
</addressmappings>
<mcconfigs>
<mcconfig src="../../DRAMSys/tests/TLM_compliance/fifoStrict.xml"/>
</mcconfigs>
<tracesetups>
<tracesetup id="TLM_compliance_test">
<device clkMhz="200">chstone-adpcm_32.stl</device>
</tracesetup>
</tracesetups>
</simulation>

105
DRAMSys/tests/TLM_compliance/test.pl
View File

@@ -1,105 +0,0 @@
#!/usr/bin/perl -w
# Copyright (c) 2015, University of Kaiserslautern
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors:
# Matthias Jung, Felipe S. Prado, Thanh C. Tran
#
# Test TLM Compliance:
# This test runs the simulation with standard configuration
# Run Simulation:
# Get number of Cores:
use Config;
my $numberOfCores;
if ($Config{osname} eq "darwin")
{
$numberOfCores = `sysctl -n hw.ncpu`;
}
elsif ($Config{osname} eq "linux")
{
$numberOfCores = `cat /proc/cpuinfo | grep processor | wc -l`;
}
chdir("../../../build/simulator/");
$exampleInitiatorLine = `grep -n '#define USE_EXAMPLE_INITIATOR' ../../DRAMSys/library/src/simulation/SimulationManager.h | cut -d: -f 1`;
chomp $exampleInitiatorLine;
system("sed -i.bu '" . $exampleInitiatorLine . "s^.*^#define USE_EXAMPLE_INITIATOR 1^' ../../DRAMSys/library/src/simulation/SimulationManager.h");
`make -j$numberOfCores > /dev/null 2>&1`;
$storeModeLine = `grep -n '<StoreMode value=' ../../DRAMSys/tests/TLM_compliance/fifoStrict.xml | cut -d: -f 1`;
chomp $storeModeLine;
system("sed -i.bu '" . $storeModeLine . "s^.*^ <StoreMode value=\"Store\"/>^' ../../DRAMSys/tests/TLM_compliance/fifoStrict.xml");
`./DRAMSys ../../DRAMSys/tests/TLM_compliance/sim-batch.xml &> ../../DRAMSys/tests/TLM_compliance/output.txt`;
if("" ne `grep "Error: tlm2_protocol_checker" ../../DRAMSys/tests/TLM_compliance/output.txt`)
{
clean_backup_files();
exit -1;
}
system("sed -i.bu '" . $exampleInitiatorLine . "s^.*^#define USE_EXAMPLE_INITIATOR 0^' ../../DRAMSys/library/src/simulation/SimulationManager.h");
`make -j$numberOfCores > /dev/null 2>&1`;
system("sed -i.bu '" . $storeModeLine . "s^.*^ <StoreMode value=\"NoStorage\"/>^' ../../DRAMSys/tests/TLM_compliance/fifoStrict.xml");
`rm -f sim-batch/TLM_compliance_test*.tdb`;
`./DRAMSys ../../DRAMSys/tests/TLM_compliance/sim-batch.xml &> ../../DRAMSys/tests/TLM_compliance/output.txt`;
if("" ne `grep "Error: tlm2_protocol_checker" ../../DRAMSys/tests/TLM_compliance/output.txt`)
{
clean_backup_files();
exit -1;
}
clean_backup_files();
exit 0;
sub clean_backup_files {
`rm -rf ../../DRAMSys/library/src/simulation/SimulationManager.h.bu`;
`rm -rf ../../DRAMSys/tests/TLM_compliance/fifoStrict.xml.bu`;
}

150
DRAMSys/tests/continuous_testing_py/autotest.py
View File

@@ -1,150 +0,0 @@
# -*- coding: utf-8 -*-
# Copyright (c) 2016, University of Kaiserslautern
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Éder F. Zulian
#
import unittest
import subprocess
import os
import shutil
import multiprocessing
import sys
import tempfile
from memutil import *
devnull = None
# If you want to change the standard output and/or standard error output do
# that in the top-level script environment (the '__main__' at the very bottom
# of this file.
out = None
errout = None
rootdir = '../../..'
workingdir = os.getcwd()
tempfile.tempdir = workingdir + '/' + rootdir
builddir = tempfile.mkdtemp()
simdir = builddir + '/simulator'
mcConfigPath = rootdir + '/DRAMSys/library/resources/configs/mcconfigs'
memSpecsPath = rootdir + '/DRAMSys/library/resources/configs/memspecs'
baseConfigPath = workingdir + '/baseconfig.xml'
qmakeProjFile = '../DRAMSys/DRAMSys.pro'
def build_project():
if os.path.exists(builddir):
shutil.rmtree(builddir)
os.makedirs(builddir)
os.chdir(builddir)
subprocess.call(['qmake', qmakeProjFile], stdout=out, stderr=errout)
makejobs = '-j' + str(multiprocessing.cpu_count())
ret = subprocess.call(['make', makejobs], stdout=out, stderr=errout)
return ret
class TestBuild(unittest.TestCase):
def test_build_project(self):
""" The project's build process should succeed """
self.assertEqual(build_project(), 0)
def tearDown(self):
shutil.rmtree(builddir)
class TestRun(unittest.TestCase):
def setUp(self):
build_project()
def test_run_without_arguments(self):
""" running dramSys without arguments returns 0 """
os.chdir(simdir)
self.assertEqual(subprocess.call(['./DRAMSys'], stdout=out), 0)
def tearDown(self):
shutil.rmtree(builddir)
@unittest.skip("skipping this")
class TestOutput(unittest.TestCase):
def setUp(self):
self.tfd, self.tfpath = tempfile.mkstemp()
self.outrefpath = workingdir + '/baseconfig_expected.out'
build_project()
def filter_output(self, fname):
with open(fname, 'r') as f:
lines = f.readlines()
f.close()
return [l for l in lines if l.startswith('sim.dram')]
def test_run_with_base_config(self):
""" running dramSys with base config, output match reference """
os.chdir(simdir)
with open(self.tfpath, 'w') as f:
self.assertEqual(subprocess.call(['./DRAMSys', baseConfigPath],
stdout=f), 0)
f.close()
tout = self.filter_output(self.tfpath)
tref = self.filter_output(self.outrefpath)
self.assertListEqual(tout, tref)
def tearDown(self):
shutil.rmtree(builddir)
os.unlink(self.tfpath)
# This is an example that shows how to skip a test.
@unittest.skip("skipping this")
class TestDummy(unittest.TestCase):
def setUp(self):
os.chdir(workingdir)
def test_list_files(self):
""" Test that lists some configuration files with XML extension """
print('\nPath is: {}\n'.format(mcConfigPath))
for file in os.listdir(mcConfigPath):
if file.endswith(".xml"):
print(file)
print('\nPath is: {}\n'.format(memSpecsPath))
for file in os.listdir(memSpecsPath):
if file.endswith(".xml"):
print(file)
if __name__ == '__main__':
with open(os.devnull, 'wb') as devnull:
out = devnull
errout = devnull
# out = sys.stdout
# errout = sys.stderr
unittest.main()

56
DRAMSys/tests/continuous_testing_py/baseconfig.xml
View File

@@ -1,56 +0,0 @@
<simulation>
<!-- General Simulator Configuration (used for all simulation setups) -->
<simconfig>
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<WindowSize value="100" />
<NumberOfTracePlayers value="1"/>
<NumberOfMemChannels value="1"/>
<ControllerCoreRefDisable value="0"/>
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfDevicesOnDIMM value = "8" />
</simconfig>
<!-- Temperature Simulator Configuration (used for all simulation setups) -->
<thermalsimconfig>
<TemperatureScale value="Celsius" />
<StaticTemperatureDefaultValue value="89" />
<ThermalSimPeriod value="100" />
<ThermalSimUnit value="us" />
<PowerInfoFile value="../../DRAMSys/library/resources/configs/thermalsim/powerInfo.xml"/>
<IceServerIp value="127.0.0.1" />
<IceServerPort value="11880" />
<SimPeriodAdjustFactor value="10" />
<NPowStableCyclesToIncreasePeriod value="5" />
<GenerateTemperatureMap value="1" />
<GeneratePowerMap value="1" />
</thermalsimconfig>
<!-- Memory Device Specification: Which Device is on our simulated DDR3 DIMM -->
<memspecs>
<memspec src="../../DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml"></memspec>
</memspecs>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmappings>
<addressmapping src="../../DRAMSys/library/resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml"></addressmapping>
</addressmappings>
<!-- Memory Controller Configuration -->
<mcconfigs>
<mcconfig src="../../DRAMSys/library/resources/configs/mcconfigs/fifoStrict.xml"/>
</mcconfigs>
<tracesetups>
<tracesetup id="continuous_testing_py">
<device clkMhz="200">ddr3_example.stl</device>
</tracesetup>
</tracesetups>
</simulation>

6
DRAMSys/tests/continuous_testing_py/baseconfig_expected.out
View File

@@ -1,6 +0,0 @@
sim.dram0 Total Energy: 45565500.00 pJ
sim.dram0 Average Power: 2156.95 mW
sim.dram0 Total Time: 20642500 ps
sim.dram0 AVG BW: 45.44 Gibit/s (45.44 %)
sim.dram0 AVG BW/IDLE: 45.44 Gibit/s (45.44 %)
sim.dram0 MAX BW: 100.00 Gibit/s

70
DRAMSys/tests/continuous_testing_py/memutil.py
View File

@@ -1,70 +0,0 @@
# -*- coding: utf-8 -*-
# Copyright (c) 2016, University of Kaiserslautern
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Éder F. Zulian
#
import xml.etree.ElementTree as ET
class MCConfig(object):
""" Memory Controller Configuration Class
The format used in memory specification XML files differs from the
format used in memory controller configuration XML files. Each class
uses the proper format when searching for elements.
"""
def getValue(self, id):
return self.xmlMCConfig.findall(id)[0].attrib['value']
def getIntValue(self, id):
return int(self.getValue(id))
def __init__(self, xmlfile):
self.xmlMCConfig = ET.parse(xmlfile)
class MemSpec(object):
""" Memory Specification Class
The format used in memory specification XML files differs from the
format used in memory configuration XML files. Each class uses the
proper format when searching for elements.
"""
def getValue(self, id):
return self.xmlMemSpec.findall(".//parameter[@id='{0}']".
format(id))[0].attrib['value']
def getIntValue(self, id):
return int(self.getValue(id))
def __init__(self, xmlfile):
self.xmlMemSpec = ET.parse(xmlfile)

7
DRAMSys/tests/ddr3_multirank/ci.yml
View File

@@ -1,6 +1,6 @@
# DDR3 Dual Rank Test with Staggered Power Down Policy and Scheduler FrFcfsGrp
example_ddr3:
stage: DDR3
example_DDR3:
stage: tests
script:
- export GCOV_PREFIX=$(pwd)
- export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}')
@@ -25,5 +25,4 @@ example_ddr3:
paths:
- build/simulator/ddr3-dual-rank_ddr3_ch0.tdb
- coverage/${CI_JOB_NAME}.out
expire_in: 2 days
expire_in: 2 days

26
DRAMSys/tests/ddr3_multirank/configs/mcconfigs/fr_fcfs_grp.json
View File

@@ -1,12 +1,14 @@
{"mcconfig":
{"PagePolicy": "Open",
"Scheduler": "FrFcfsGrp",
"RequestBufferSize": 8,
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "Rankwise",
"RefreshMode": 1,
"RefreshMaxPostponed": 0,
"RefreshMaxPulledin": 0,
"PowerDownPolicy": "Staggered",
"PowerDownTimeout": 100}}
{
"mcconfig": {
"PagePolicy": "Open",
"Scheduler": "FrFcfsGrp",
"RequestBufferSize": 8,
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "Rankwise",
"RefreshMaxPostponed": 0,
"RefreshMaxPulledin": 0,
"PowerDownPolicy": "Staggered",
"PowerDownTimeout": 100
}
}

1
DRAMSys/tests/error/.gitignore vendored
View File

@@ -1 +0,0 @@
*.stl

61
DRAMSys/tests/error/WideIO.xml
View File

@@ -1,61 +0,0 @@
<!DOCTYPE memspec SYSTEM "memspec.dtd">
<memspec>
<parameter id="memoryId" type="string" value="Matze_WideIO" />
<parameter id="memoryType" type="string" value="WIDEIO_SDR" />
<memarchitecturespec>
<parameter id="width" type="uint" value="128" />
<parameter id="nbrOfBanks" type="uint" value="8" />
<parameter id="nbrOfColumns" type="uint" value="128" />
<parameter id="nbrOfRows" type="uint" value="8192" />
<parameter id="dataRate" type="uint" value="1" />
<parameter id="burstLength" type="uint" value="4" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="166" />
<parameter id="RC" type="uint" value="9" /><!--tRP+tRAS-->
<parameter id="RCD" type="uint" value="3" />
<parameter id="RL" type="uint" value="3" />
<parameter id="RP" type="uint" value="3" />
<parameter id="RFC" type="uint" value="22" />
<parameter id="RAS" type="uint" value="6" />
<parameter id="WL" type="uint" value="1" />
<parameter id="AL" type="uint" value="0" />
<parameter id="RTP" type="uint" value="4" />
<parameter id="WR" type="uint" value="2" />
<parameter id="XP" type="uint" value="2" />
<parameter id="XS" type="uint" value="20" /><!--tRFC+2clk-->
<parameter id="REFI" type="uint" value="4000" />
<parameter id="TAW" type="uint" value="10" />
<parameter id="RRD" type="uint" value="2" />
<parameter id="CCD" type="uint" value="1" />
<parameter id="WTR" type="uint" value="3" />
<parameter id="CKE" type="uint" value="3" />
<parameter id="CKESR" type="uint" value="3" />
</memtimingspec>
<mempowerspec>
<parameter id="idd0" type="double" value="5.88" />
<parameter id="idd02" type="double" value="21.18" />
<parameter id="idd2p0" type="double" value="0.05" />
<parameter id="idd2p02" type="double" value="0.17" />
<parameter id="idd2p1" type="double" value="0.05" />
<parameter id="idd2p12" type="double" value="0.17" />
<parameter id="idd2n" type="double" value="0.13" />
<parameter id="idd2n2" type="double" value="4.04" />
<parameter id="idd3p0" type="double" value="0.25" />
<parameter id="idd3p02" type="double" value="1.49" />
<parameter id="idd3p1" type="double" value="0.25" />
<parameter id="idd3p12" type="double" value="1.49" />
<parameter id="idd3n" type="double" value="0.52" />
<parameter id="idd3n2" type="double" value="6.55" />
<parameter id="idd4r" type="double" value="1.41" />
<parameter id="idd4r2" type="double" value="85.73" />
<parameter id="idd4w" type="double" value="1.42" />
<parameter id="idd4w2" type="double" value="60.79" />
<parameter id="idd5" type="double" value="14.43" />
<parameter id="idd52" type="double" value="48.17" />
<parameter id="idd6" type="double" value="0.07" />
<parameter id="idd62" type="double" value="0.27" />
<parameter id="vdd" type="double" value="1.8" />
<parameter id="vdd2" type="double" value="1.2" />
</mempowerspec>
</memspec>

18
DRAMSys/tests/error/am_wideio.xml
View File

@@ -1,18 +0,0 @@
<addressmapping>
<channel from="27" to="28" />
<row from="14" to="26" />
<column from="7" to="13" />
<bank from="4" to="6" />
<bytes from="0" to="3" />
</addressmapping>
<!-- Magali values: -->
<!--
<addressmapping>
<channel from="27" to="28" />
<bank from="24" to="26" />
<row from="11" to="23" />
<column from="4" to="10" />
<bytes from="0" to="3" />
</addressmapping>
-->

22
DRAMSys/tests/error/fr_fcfs.xml
View File

@@ -1,22 +0,0 @@
<mcconfig>
<BankwiseLogic value="0"/>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
<Scheduler value="FrFcfs" />
<Capsize value="5" />
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Error Model: -->
<ErrorChipSeed value="42" />
<ErrorCSVFile value="../../DRAMSys/library/src/error/error.csv" />
<!-- Modes: NoStorage, Store (store data without errormodel), ErrorModel (store data with errormodel) -->
<StoreMode value="ErrorModel" />
<!--
<ReadWriteGrouping value="false" />
<ModelStorage value="false" />
<ModelErrorInjection value="false" />
<ReorderBuffer value="false" />
<DatabaseRecording value="true" />
-->
</mcconfig>

63
DRAMSys/tests/error/generateErrorTest.pl
View File

@@ -1,63 +0,0 @@
#!/usr/bin/perl -w
use warnings;
use strict;
# Assuming this address mapping:
# <addressmapping>
# <channel from="27" to="28" />
# <row from="14" to="26" />
# <column from="7" to="13" />
# <bank from="4" to="6" />
# <bytes from="0" to="3" />
# </addressmapping>
# This is how it should look like later:
# 31: write 0x0 ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
my $numberOfRows = 8192;
my $numberOfColumnsPerRow = 128;
my $bytesPerColumn = 16;
my $burstLength = 4; # burst length of 4 columns --> 4 columns written or read per access
my $dataLength = $bytesPerColumn * $burstLength;
my $rowOffset = 0x4000;
my $colOffset = 0x80;
# Generate Data Pattern:
my $dataPatternByte = "ff";
my $dataPattern = "";
for(my $i = 0; $i < $dataLength; $i++)
{
$dataPattern .= $dataPatternByte;
}
my $clkCounter = 0;
my $addr = 0;
# Generate Trace file (writes):
for(my $row = 0; $row < ($numberOfRows * $rowOffset); $row = $row + $rowOffset)
{
for(my $col = 0; $col < ($numberOfColumnsPerRow * $colOffset); $col = $col + ($colOffset * $burstLength))
{
my $addrHex = sprintf("0x%x", $addr);
print "$clkCounter:\twrite\t$addrHex\t$dataPattern\n";
$clkCounter++;
$addr += $colOffset * $burstLength;
}
}
$clkCounter = 350000000;
$addr = 0;
# Generate Trace file (reads):
for(my $row = 0; $row < ($numberOfRows * $rowOffset); $row = $row + $rowOffset)
{
for(my $col = 0; $col < ($numberOfColumnsPerRow * $colOffset); $col = $col + ($colOffset * $burstLength))
{
my $addrHex = sprintf("0x%x", $addr);
print "$clkCounter:\tread\t$addrHex\t$dataPattern\n";
$clkCounter++;
$addr += $colOffset * $burstLength;
}
}

72
DRAMSys/tests/error/generateErrorTest_4ch.pl
View File

@@ -1,72 +0,0 @@
#!/usr/bin/perl -w
use warnings;
use strict;
# Assuming this address mapping:
# <addressmapping>
# <channel from="27" to="28" />
# <row from="14" to="26" />
# <column from="7" to="13" />
# <bank from="4" to="6" />
# <bytes from="0" to="3" />
# </addressmapping>
# This is how it should look like later:
# 31: write 0x0 ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
my $numberOfRows = 8192;
my $numberOfColumnsPerRow = 128;
my $bytesPerColumn = 16;
my $burstLength = 4; # burst length of 4 columns --> 4 columns written or read per access
my $dataLength = $bytesPerColumn * $burstLength;
my $rowOffset = 0x4000;
my $colOffset = 0x80;
# Generate Data Pattern:
my $dataPatternByte = "ff";
my $dataPattern = "";
for(my $i = 0; $i < $dataLength; $i++)
{
$dataPattern .= $dataPatternByte;
}
my $clkCounter = 0;
my $addr = 0;
# Generate Trace file (writes):
for(my $ch = 0; $ch < 4; $ch++) {
$addr = 0;
$addr |= $ch << 27;
for(my $row = 0; $row < ($numberOfRows * $rowOffset); $row = $row + $rowOffset)
{
for(my $col = 0; $col < ($numberOfColumnsPerRow * $colOffset); $col = $col + ($colOffset * $burstLength))
{
my $addrHex = sprintf("0x%x", $addr);
print "$clkCounter:\twrite\t$addrHex\t$dataPattern\n";
$clkCounter++;
$addr += $colOffset * $burstLength;
}
}
}
$clkCounter = 350000000;
$addr = 0;
# Generate Trace file (reads):
for(my $ch = 0; $ch < 4; $ch++) {
$addr = 0;
$addr |= $ch << 27;
for(my $row = 0; $row < ($numberOfRows * $rowOffset); $row = $row + $rowOffset)
{
for(my $col = 0; $col < ($numberOfColumnsPerRow * $colOffset); $col = $col + ($colOffset * $burstLength))
{
my $addrHex = sprintf("0x%x", $addr);
print "$clkCounter:\tread\t$addrHex\t$dataPattern\n";
$clkCounter++;
$addr += $colOffset * $burstLength;
}
}
}

52
DRAMSys/tests/error/sim-batch.xml
View File

@@ -1,52 +0,0 @@
<simulation>
<!-- General Simulator Configuration (used for all simulation setups) -->
<simconfig>
<Debug value="0" />
<DatabaseRecording value="0" />
<PowerAnalysis value="1" />
<EnableWindowing value = "0" />
<WindowSize value="1000" />
<NumberOfTracePlayers value="1"/>
<NumberOfMemChannels value="4"/>
<ControllerCoreRefDisable value="0"/>
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfDevicesOnDIMM value = "1" />
<CheckTLM2Protocol value = "0" />
</simconfig>
<!-- Temperature Simulator Configuration (used for all simulation setups) -->
<thermalsimconfig>
<TemperatureScale value="Celsius" />
<StaticTemperatureDefaultValue value="89" />
<ThermalSimPeriod value="10" />
<ThermalSimUnit value="ms" />
<PowerInfoFile value="../../DRAMSys/library/resources/configs/thermalsim/powerInfo.xml"/>
<IceServerIp value="127.0.0.1" />
<IceServerPort value="11880" />
<SimPeriodAdjustFactor value="10" />
<NPowStableCyclesToIncreasePeriod value="5" />
<GenerateTemperatureMap value="1" />
<GeneratePowerMap value="1" />
</thermalsimconfig>
<memspecs>
<memspec src="../../DRAMSys/tests/error/WideIO.xml"></memspec>
</memspecs>
<addressmappings>
<addressmapping src="../../DRAMSys/tests/error/am_wideio.xml"></addressmapping>
</addressmappings>
<mcconfigs>
<mcconfig src="../../DRAMSys/tests/error/fr_fcfs.xml"/>
</mcconfigs>
<tracesetups>
<tracesetup id="errorTest_fr_fcfs_test_error.stl">
<device clkMhz="1000">../../../tests/error/test_error.stl</device>
</tracesetup>
</tracesetups>
</simulation>

84
DRAMSys/tests/error/test.pl
View File

@@ -1,84 +0,0 @@
#!/usr/bin/perl -w
# Copyright (c) 2015, University of Kaiserslautern
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors:
# Matthias Jung
# Eder F. Zulian
#
# Test error:
# This test runs the simulation with error model enabled.
# The main configuration file for this test is DRAMSys/tests/error/sim-batch.xml.
#
use warnings;
use strict;
use Term::ANSIColor;
my $trace_file = "test_error.stl";
# Create the input file (first make sure the script is executable)
chdir("../../DRAMSys/tests/error");
if (! -e $trace_file) {
`chmod u+x ./generateErrorTest.pl`;
`./generateErrorTest.pl > $trace_file`;
}
# Run Simulation:
chdir("../../../build/simulator/");
`./DRAMSys ../../DRAMSys/tests/error/sim-batch.xml > ../../DRAMSys/tests/error/output.txt`;
chdir("../../DRAMSys/tests/error");
my @channels_retention_errors = ();
@channels_retention_errors = split(/\n/,`cat output.txt | grep 'Number of Retention Error Events' | cut -d= -f2 | sed 's/ //g'`);
if (!@channels_retention_errors) {
print color("red"), "\tError: ", color("green"), "error model output information not found.\n";
print color("yellow"), "\tCheck if error model is enabled.\n";
exit -1
}
my $errors_found = 0;
foreach (@channels_retention_errors) {
print "$_\n";
$errors_found += $_;
}
print color("green"), "Number of Retention Errors Events (all banks): $errors_found\n";
if ($errors_found == 0) {
# Fail, errors expected but not found.
exit -1;
}
# Success, at least one error was found.
exit 0;

6
DRAMSys/tests/lpddr4/ci.yml
View File

@@ -1,6 +1,6 @@
# LPDDR4 with Bankwise Flexible Refresh and FIFO Scheduler:
example_lpddr4:
stage: LPDDR4
example_LPDDR4:
stage: tests
script:
- export GCOV_PREFIX=$(pwd)
- export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}')
@@ -25,4 +25,4 @@ example_lpddr4:
paths:
- build/simulator/lpddr4-example_lpddr4_ch0.tdb
- coverage/${CI_JOB_NAME}.out
expire_in: 2 days
expire_in: 2 days

25
DRAMSys/tests/lpddr4/configs/mcconfigs/fifo.json
View File

@@ -1,11 +1,14 @@
{"mcconfig": {"PagePolicy": "OpenAdaptive",
"Scheduler": "Fifo",
"RequestBufferSize": 8,
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "Bankwise",
"RefreshMode": 1,
"RefreshMaxPostponed": 8,
"RefreshMaxPulledin": 8,
"PowerDownPolicy": "NoPowerDown",
"PowerDownTimeout": 100}}
{
"mcconfig": {
"PagePolicy": "OpenAdaptive",
"Scheduler": "Fifo",
"RequestBufferSize": 8,
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "Bankwise",
"RefreshMaxPostponed": 8,
"RefreshMaxPulledin": 8,
"PowerDownPolicy": "NoPowerDown",
"PowerDownTimeout": 100
}
}

24
DRAMSys/tests/simple/expected.txt
View File

@@ -1,24 +0,0 @@
sim.dram0 Total Energy: 4300303.75 pJ
sim.dram0 Average Power: 12.62 mW
sim.dram0 Total Time: 340669248 ps
sim.dram0 AVG BW: 1.00 Gibit/s (4.81 %)
sim.dram0 AVG BW/IDLE: 10.64 Gibit/s (51.27 %)
sim.dram0 MAX BW: 20.75 Gibit/s
sim.dram1 Total Energy: 2157481.55 pJ
sim.dram1 Average Power: 6.40 mW
sim.dram1 Total Time: 0 s
sim.dram1 AVG BW: -nan Gibit/s (-nan %)
sim.dram1 AVG BW/IDLE: -nan Gibit/s (-nan %)
sim.dram1 MAX BW: 20.75 Gibit/s
sim.dram2 Total Energy: 4202780.15 pJ
sim.dram2 Average Power: 12.34 mW
sim.dram2 Total Time: 340115040 ps
sim.dram2 AVG BW: 0.75 Gibit/s (3.63 %)
sim.dram2 AVG BW/IDLE: 15.65 Gibit/s (75.44 %)
sim.dram2 MAX BW: 20.75 Gibit/s
sim.dram3 Total Energy: 2293679.84 pJ
sim.dram3 Average Power: 6.81 mW
sim.dram3 Total Time: 312862464 ps
sim.dram3 AVG BW: 0.03 Gibit/s (0.14 %)
sim.dram3 AVG BW/IDLE: 9.21 Gibit/s (44.40 %)
sim.dram3 MAX BW: 20.75 Gibit/s

15
DRAMSys/tests/simple/fifoStrict.xml
View File

@@ -1,15 +0,0 @@
<mcconfig>
<BankwiseLogic value="0"/>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
<Scheduler value="FifoStrict" />
<Capsize value="5" />
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Error Modelling -->
<ErrorChipSeed value="42" />
<ErrorCSVFile value="../../DRAMSys/library/src/error/error.csv" />
<!-- Modes: NoStorage, Store (store data without errormodel), ErrorModel (store data with errormodel) -->
<StoreMode value="NoStorage" />
</mcconfig>

52
DRAMSys/tests/simple/sim-batch.xml
View File

@@ -1,52 +0,0 @@
<simulation>
<!-- General Simulator Configuration (used for all simulation setups) -->
<simconfig>
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "0" />
<WindowSize value="1000" />
<NumberOfTracePlayers value="1"/>
<NumberOfMemChannels value="4"/>
<ControllerCoreRefDisable value="0"/>
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfDevicesOnDIMM value = "1" />
<CheckTLM2Protocol value = "0" />
</simconfig>
<!-- Temperature Simulator Configuration (used for all simulation setups) -->
<thermalsimconfig>
<TemperatureScale value="Celsius" />
<StaticTemperatureDefaultValue value="89" />
<ThermalSimPeriod value="10" />
<ThermalSimUnit value="ms" />
<PowerInfoFile value="../../DRAMSys/library/resources/configs/thermalsim/powerInfo.xml"/>
<IceServerIp value="127.0.0.1" />
<IceServerPort value="11880" />
<SimPeriodAdjustFactor value="10" />
<NPowStableCyclesToIncreasePeriod value="5" />
<GenerateTemperatureMap value="1" />
<GeneratePowerMap value="1" />
</thermalsimconfig>
<memspecs>
<memspec src="../../DRAMSys/library/resources/configs/memspecs/WideIO.xml"></memspec>
</memspecs>
<addressmappings>
<addressmapping src="../../DRAMSys/library/resources/configs/amconfigs/am_wideio.xml"></addressmapping>
</addressmappings>
<mcconfigs>
<mcconfig src="../../DRAMSys/tests/simple/fifoStrict.xml"/>
</mcconfigs>
<tracesetups>
<tracesetup id="simple_test_fifoStrict_chstone-adpcm_32">
<device clkMhz="200">chstone-adpcm_32.stl</device>
</tracesetup>
</tracesetups>
</simulation>

57
DRAMSys/tests/simple/test.pl
View File

@@ -1,57 +0,0 @@
#!/usr/bin/perl -w
# Copyright (c) 2015, University of Kaiserslautern
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors:
# Matthias Jung
#
# Test Simple:
# This test runs the simulation with standard configuration
use File::Compare;
# Run Simulation:
chdir("../../../build/simulator/");
`./DRAMSys ../../DRAMSys/tests/simple/sim-batch.xml > ../../DRAMSys/tests/simple/output.txt`;
chdir("../../DRAMSys/tests/simple");
`cat output.txt | tail -n 24 > current.txt`;
if(compare("current.txt","expected.txt") == 0)
{
exit 0
}
else
{
exit -1
}

133
DRAMSys/tests/start.pl
View File

@@ -1,133 +0,0 @@
#!/usr/bin/perl -w
# Copyright (c) 2015, University of Kaiserslautern
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors:
# Matthias Jung
# Eder F. Zulian
# Thanh C. Tran
#
use warnings;
use strict;
use Term::ANSIColor;
use Time::localtime;
use Config;
my $pathSelector = shift || "";
if($pathSelector eq "absolute")
{
chdir("/home/test_dramsys/dram.sys/DRAMSys/tests") || die("chdir");
}
my $timestamp_color = "green";
print color("red")," |||\n";
print color("red")," +---+ Microelectronic Systems\n";
print color("red"),"=| |= Design Research Group\n";
print color("red"),"=| |= ", color("blue"),"University of Kaiserslautern\n";
print color("red")," +---+\n";
print color("red")," ||| ", color("green"),"DRAMSys Automated Test System\n", color("reset");
# Get number of Cores:
my $numberOfCores;
if ($Config{osname} eq "darwin")
{
$numberOfCores = `sysctl -n hw.ncpu`;
}
elsif ($Config{osname} eq "linux")
{
$numberOfCores = `cat /proc/cpuinfo | grep processor | wc -l`;
}
# Navigate to Build Folder
chdir("../../") || die("chdir");
`mkdir build >/dev/null 2>&1`;
chdir("build/") || die("chdir");
# Build the Project:
my $starttime = time();
print "\n", color($timestamp_color), timestamp(), color("reset"),"Build Project\t";
`qmake ../DRAMSys/DRAMSys.pro >/dev/null 2>&1`;
`make -j$numberOfCores > /dev/null 2>&1`;
my $took = time() - $starttime;
# Check if Build was sucessful:
if( -e "./simulator/DRAMSys" )
{
print color("reset"),"[ ", color("green"), "done", color("reset"), " ]\t", "(", $took, " seconds)\n";
}
else
{
print color("reset"),"[ ", color("red"), "fail", color("reset"), " ]\t", "(", $took, " seconds)\n";
exit -1;
}
# Find all tests:
# Navigate to Build Folder
chdir("../DRAMSys/tests") || die("chdir");
my @tests = split(/\n/,`find . -iname test.pl`);
# Run Tests:
foreach(@tests)
{
if($_ =~ /\.\/([\w\d]+)\/test\.pl/)
{
my $name = $1;
chdir("./$name") || die("chdir");
print color($timestamp_color), timestamp(), color("reset"),"Test: ".$name."\t";
$starttime = time();
`perl test.pl`;
$took = time() - $starttime;
if( $? == 0 )
{
print color("reset"),"[ ", color("green"), "done", color("reset"), " ]\t", "(", $took, " seconds)\n";
}
else
{
print color("reset"),"[ ", color("red"), "fail", color("reset"), " ]\t", "(", $took, " seconds)\n";
}
chdir("../") || die("chdir");
}
else
{
exit -1;
}
}
sub timestamp {
my $t = localtime;
return sprintf( "[%04d-%02d-%02d %02d:%02d:%02d]\t",
$t->year + 1900, $t->mon + 1, $t->mday,
$t->hour, $t->min, $t->sec );
}

46
DRAMSys/tests/tests.pri
View File

@@ -1,46 +0,0 @@
# Relative paths to "DRAMSys" because this file is included in
# "DRAMSys/DRAMSys.pro"
DISTFILES += tests/start.pl
# DDR:
DISTFILES += tests/DDR3/ci.yml
DISTFILES += tests/DDR3/configs/amconfigs/*
DISTFILES += tests/DDR3/configs/mcconfigs/*
DISTFILES += tests/DDR3/configs/memspecs/*
DISTFILES += tests/DDR3/configs/simulator/*
DISTFILES += tests/DDR3/configs/thermalsim/*
DISTFILES += tests/DDR3/expected/*
DISTFILES += tests/DDR3/scripts/*
DISTFILES += tests/DDR3/simulations/*
DISTFILES += tests/DDR3/traces/*
# simple test
DISTFILES += tests/simple/sim-batch.xml
DISTFILES += tests/simple/fifoStrict.xml
DISTFILES += tests/simple/test.pl
DISTFILES += tests/simple/expected.txt
# error test
DISTFILES += tests/error/sim-batch.xml
DISTFILES += tests/error/test.pl
DISTFILES += tests/error/am_wideio.xml
DISTFILES += tests/error/fr_fcfs.xml
DISTFILES += tests/error/generateErrorTest.pl
DISTFILES += tests/error/WideIO.xml
# timing compliance test
DISTFILES += tests/timing_compliance/sim-batch.xml
DISTFILES += tests/timing_compliance/fifoStrict.xml
DISTFILES += tests/timing_compliance/test.pl
# TLM compliance test
DISTFILES += tests/TLM_compliance/sim-batch.xml
DISTFILES += tests/TLM_compliance/fifoStrict.xml
DISTFILES += tests/TLM_compliance/test.pl
# python continuous testing
DISTFILES += tests/continuous_testing_py/autotest.py
DISTFILES += tests/continuous_testing_py/baseconfig_expected.out
DISTFILES += tests/continuous_testing_py/baseconfig.xml
DISTFILES += tests/continuous_testing_py/memutil.py

15
DRAMSys/tests/timing_compliance/fifoStrict.xml
View File

@@ -1,15 +0,0 @@
<mcconfig>
<BankwiseLogic value="1"/>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
<Scheduler value="FifoStrict" />
<Capsize value="5" />
<PowerDownMode value="TimeoutSREF" />
<PowerDownTimeout value="100" />
<!-- Error Modelling -->
<ErrorChipSeed value="42" />
<ErrorCSVFile value="../../DRAMSys/library/src/error/error.csv" />
<!-- Modes: NoStorage, Store (store data without errormodel), ErrorModel (store data with errormodel) -->
<StoreMode value="NoStorage" />
</mcconfig>

52
DRAMSys/tests/timing_compliance/sim-batch.xml
View File

@@ -1,52 +0,0 @@
<simulation>
<!-- General Simulator Configuration (used for all simulation setups) -->
<simconfig>
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="0" />
<EnableWindowing value = "0" />
<WindowSize value="1000" />
<NumberOfTracePlayers value="1"/>
<NumberOfMemChannels value="4"/>
<ControllerCoreRefDisable value="0"/>
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfDevicesOnDIMM value = "1" />
<CheckTLM2Protocol value = "0" />
</simconfig>
<!-- Temperature Simulator Configuration (used for all simulation setups) -->
<thermalsimconfig>
<TemperatureScale value="Celsius" />
<StaticTemperatureDefaultValue value="89" />
<ThermalSimPeriod value="10" />
<ThermalSimUnit value="ms" />
<PowerInfoFile value="../../DRAMSys/library/resources/configs/thermalsim/powerInfo.xml"/>
<IceServerIp value="127.0.0.1" />
<IceServerPort value="11880" />
<SimPeriodAdjustFactor value="10" />
<NPowStableCyclesToIncreasePeriod value="5" />
<GenerateTemperatureMap value="1" />
<GeneratePowerMap value="1" />
</thermalsimconfig>
<memspecs>
<memspec src="../../DRAMSys/library/resources/configs/memspecs/WideIO.xml"></memspec>
</memspecs>
<addressmappings>
<addressmapping src="../../DRAMSys/library/resources/configs/amconfigs/am_wideio.xml"></addressmapping>
</addressmappings>
<mcconfigs>
<mcconfig src="../../DRAMSys/tests/timing_compliance/fifoStrict.xml"/>
</mcconfigs>
<tracesetups>
<tracesetup id="timing_compliance_test_fifoStrict">
<device clkMhz="200">chstone-jpeg_32.stl</device>
</tracesetup>
</tracesetups>
</simulation>

100
DRAMSys/tests/timing_compliance/test.pl
View File

@@ -1,100 +0,0 @@
#!/usr/bin/perl -w
# Copyright (c) 2016, University of Kaiserslautern
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors:
# Matthias Jung, Felipe S. Prado, Thanh C. Tran
#
# Test Timing Compliance:
# This test runs the simulation with standard configuration
# Run Simulation:
$bankwiseLogicLine = `grep -n '<BankwiseLogic value=' fifoStrict.xml | cut -d: -f 1`;
chomp $bankwiseLogicLine;
$powerAnalysisLine = `grep -n '<PowerAnalysis value=' sim-batch.xml | cut -d: -f 1`;
chomp $powerAnalysisLine;
$powerDownModeLine = `grep -n '<PowerDownMode value=' fifoStrict.xml | cut -d: -f 1`;
chomp $powerDownModeLine;
$powerDownModes = `grep 'enum class EPowerDownMode' ../../library/src/controller/core/configuration/Configuration.h | cut -d } -f 1 | sed 's/ //g' | cut -d { -f 2`;
@powerDownModes = split(/,/,$powerDownModes);
chomp @powerDownModes;
chdir("../../../build/simulator/");
foreach (@powerDownModes)
{
system("sed -i.bu '" . $powerAnalysisLine . "s^.*^ <PowerAnalysis value=\"1\" />^' ../../DRAMSys/tests/timing_compliance/sim-batch.xml");
system("sed -i.bu '" . $bankwiseLogicLine . "s^.*^ <BankwiseLogic value=\"0\"/>^' ../../DRAMSys/tests/timing_compliance/fifoStrict.xml");
system("sed -i.bu '" . $powerDownModeLine . "s^.*^ <PowerDownMode value=\"$_\" />^' ../../DRAMSys/tests/timing_compliance/fifoStrict.xml");
`./DRAMSys ../../DRAMSys/tests/timing_compliance/sim-batch.xml`;
@files = `ls sim-batch/timing_compliance_test_fifoStrict_channel*.tdb`;
chomp @files;
foreach (@files)
{
`python3.5 ../../DRAMSys/traceAnalyzer/scripts/tests.py $_ > ../../DRAMSys/tests/timing_compliance/output.txt`;
if("All tests passed\n" ne `grep "All tests passed" ../../DRAMSys/tests/timing_compliance/output.txt`)
{
clean_backup_files();
exit -1;
}
}
system("sed -i.bu '" . $powerAnalysisLine . "s^.*^ <PowerAnalysis value=\"0\" />^' ../../DRAMSys/tests/timing_compliance/sim-batch.xml");
system("sed -i.bu '" . $bankwiseLogicLine . "s^.*^ <BankwiseLogic value=\"1\"/>^' ../../DRAMSys/tests/timing_compliance/fifoStrict.xml");
`./DRAMSys ../../DRAMSys/tests/timing_compliance/sim-batch.xml`;
foreach (@files)
{
`python3.5 ../../DRAMSys/traceAnalyzer/scripts/tests.py $_ > ../../DRAMSys/tests/timing_compliance/output.txt`;
if("All tests passed\n" ne `grep "All tests passed" ../../DRAMSys/tests/timing_compliance/output.txt`)
{
clean_backup_files();
exit -1;
}
}
}
clean_backup_files();
exit 0;
sub clean_backup_files {
`rm -rf ../../DRAMSys/tests/timing_compliance/sim-batch.xml.bu`;
`rm -rf ../../DRAMSys/tests/timing_compliance/fifoStrict.xml.bu`;
}

1931
README.md
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