Merge branch 'ci_tests' into 'development'

Include new CI for DRAMSys4.0 on KOA

See merge request ems/astdm/dram.sys!256

.gitignore

@@ -5,6 +5,7 @@
 /dram/build
 *.user
 *.tdb
+!/DRAMSys/tests/*/expected/*.tdb
 *.tdb-journal
 *.out
 /build-simulation

.gitlab-ci.yml

@@ -6,9 +6,10 @@ variables:
 
 stages:
     - build
-    - dramsys-gem5-build
-    - WIDEIO
+    - LPDDR4
     - DDR3
+    - DDR4
+    - HBM2
     - Coverage
 
 build:
@@ -19,12 +20,14 @@ build:
         - rm -rf build
         - mkdir -p build
         - cd build
+        - export COVERAGE=true
         - cmake ../DRAMSys
-        - make -j16
+        - make -j 16
         - find . -name "*.o" -type f -delete
         - rm -rf ${CI_PROJECT_DIR}/coverage
         - mkdir -p ${CI_PROJECT_DIR}/coverage
-
+      
+ 
     cache:
         key: build
         paths:
@@ -34,7 +37,7 @@ build:
     artifacts:
         paths:
             - coverage/
-
+        
 coverage:
     stage: Coverage
     coverage: '/Total:\|(\d+\.?\d+\%)/'
@@ -42,15 +45,18 @@ coverage:
         # delete all empty files since they produce errors 
         - find coverage -size 0 -type f -delete
         - ls coverage/ -lah
-        - lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final.out
-        - lcov --list coverage/final.out
-
+        - lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final.out        
+        - lcov --remove coverage/final.out '*/systemc*/include/*' '*/traceAnalyzer/*' '*/gcc*/include/*' '/usr/include/*' '*/third_party/*' -o coverage/final_dramsys.out
+        - lcov --list coverage/final_dramsys.out
+        
     artifacts:
         paths:
             - coverage/final.out
-           
+            - coverage/final_dramsys.out
 
 include:
-    - '/DRAMSys/tests/DDR3/ci.yml'
-    - '/DRAMSys/tests/WIDEIO/ci.yml'
-    #- '/DRAMSys/tests/dramsys-gem5/ci.yml' # Should be activated again when a new gitlab runner with right dependencies is used
+    - '/DRAMSys/tests/lpddr4/ci.yml'
+    - '/DRAMSys/tests/ddr3_multirank/ci.yml'
+    - '/DRAMSys/tests/DDR4/ci.yml'
+    - '/DRAMSys/tests/HBM2/ci.yml'
+   #- '/DRAMSys/tests/dramsys-gem5/ci.yml' # Should be activated again when a new gitlab runner with right dependencies is used

DRAMSys/CMakeLists.txt

@@ -38,6 +38,13 @@ project(DRAMSys)
 # Configuration:
 set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version")
 set(DCMAKE_SH "CMAKE_SH-NOTFOUND" CACHE STRING "Ignore sh.exe error on Windows")
+if(DEFINED ENV{COVERAGE})
+    set(GCC_COVERAGE_COMPILE_FLAGS "-g -O0 -coverage -fprofile-arcs -ftest-coverage")
+    set(GCC_COVERAGE_LINK_FLAGS "-coverage -lgcov")
+    set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}")
+    set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${GCC_COVERAGE_LINK_FLAGS}")
+    message("-- Coverage check enabled")
+endif()
 
 # Add DRAMSysLibrary:
 add_subdirectory(library)
@@ -54,3 +61,4 @@ add_subdirectory(simulator)
 if(DEFINED ENV{GEM5})
     add_subdirectory(gem5)
 endif()
+

DRAMSys/library/CMakeLists.txt

@@ -38,6 +38,12 @@ project(DRAMSysLibrary)
 # Configuration:
 set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version")
 set(DCMAKE_SH="CMAKE_SH-NOTFOUND")
+if(DEFINED ENV{COVERAGE})
+    set(GCC_COVERAGE_COMPILE_FLAGS "-g -O0 -coverage -fprofile-arcs -ftest-coverage")
+    set(GCC_COVERAGE_LINK_FLAGS "-coverage -lgcov")
+    set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}")
+    set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${GCC_COVERAGE_LINK_FLAGS}")
+endif()
 
 # Add DRAMPower:
 add_subdirectory(src/common/third_party/DRAMPower)
@@ -172,6 +178,7 @@ add_library(DRAMSysLibrary
     resources/simulations/lpddr4-example.json
     resources/simulations/ranktest.json
     resources/simulations/wideio-example.json
+    resources/simulations/wideio-thermal.json
 
     # Address Mapping Config Files
     resources/configs/amconfigs/am_ddr3_1Gbx8_p1KB_brc.json
@@ -266,9 +273,11 @@ add_library(DRAMSysLibrary
     resources/configs/simulator/hbm2.json
     resources/configs/simulator/lpddr4.json
     resources/configs/simulator/wideio.json
+    resources/configs/simulator/wideio_thermal.json
 
     # Thermal Simulation Config Files
     resources/configs/thermalsim/config.json
+    resources/configs/thermalsim/powerInfo.json
 
     # Trace Files
     resources/traces/test_ecc.stl

DRAMSys/library/resources/configs/memspecs/HBM2.json

@@ -8,7 +8,8 @@
             "nbrOfColumns": 128,
             "nbrOfRanks": 2,
             "nbrOfRows": 32768,
-            "width": 64
+            "width": 64,
+            "nbrOfChannels": 1
         },
         "memoryId": "https://www.computerbase.de/2019-05/amd-memory-tweak-vram-oc/#bilder",
         "memoryType": "HBM2",
@@ -43,4 +44,4 @@
             "clkMhz": 1000
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json

@@ -7,7 +7,8 @@
             "nbrOfColumns": 128,
             "nbrOfRanks": 1,
             "nbrOfRows": 4096,
-            "width": 128
+            "width": 128,
+            "nbrOfChannels": 4
         },
         "memoryId": "JEDEC_256Mb_WIDEIO_SDR-200_128bit",
         "memoryType": "WIDEIO_SDR",
@@ -62,4 +63,4 @@
             "clkMhz": 200
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json

@@ -7,7 +7,8 @@
             "nbrOfColumns": 128,
             "nbrOfRanks": 1,
             "nbrOfRows": 4096,
-            "width": 128
+            "width": 128,
+            "nbrOfChannels": 4
         },
         "memoryId": "JEDEC_256Mb_WIDEIO_SDR-266_128bit",
         "memoryType": "WIDEIO_SDR",
@@ -62,4 +63,4 @@
             "clkMhz": 266
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json

@@ -8,7 +8,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 32768,
-            "width": 8
+            "width": 8,
+            "nbrOfDevicesOnDIMM": 8,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A",
         "memoryType": "DDR4",
@@ -65,4 +67,4 @@
             "clkMhz": 933
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json

@@ -8,7 +8,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 32768,
-            "width": 8
+            "width": 8,
+            "nbrOfDevicesOnDIMM": 8,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_4Gb_DDR4-2400_8bit_A",
         "memoryType": "DDR4",
@@ -65,4 +67,4 @@
             "clkMhz": 1200
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json

@@ -7,7 +7,8 @@
             "nbrOfColumns": 512,
             "nbrOfRanks": 1,
             "nbrOfRows": 8192,
-            "width": 64
+            "width": 64,
+            "nbrOfChannels": 4
         },
         "memoryId": "JEDEC_4x64_2Gb_WIDEIO2-400_64bit",
         "memoryType": "WIDEIO2",
@@ -39,4 +40,4 @@
             "clkMhz": 400
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json

@@ -7,7 +7,8 @@
             "nbrOfColumns": 512,
             "nbrOfRanks": 1,
             "nbrOfRows": 8192,
-            "width": 64
+            "width": 64,
+            "nbrOfChannels": 4
         },
         "memoryId": "JEDEC_4x64_2Gb_WIDEIO2-533_64bit",
         "memoryType": "WIDEIO2",
@@ -39,4 +40,4 @@
             "clkMhz": 533
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json

@@ -7,7 +7,8 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 65536,
-            "width": 16
+            "width": 16,
+            "nbrOfChannels": 1
         },
         "memoryId": "JEDEC_8Gb_LPDDR4-3200_16bit",
         "memoryType": "LPDDR4",
@@ -93,4 +94,4 @@
             "clkMhz": 1600
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 8192,
-            "width": 16
+            "width": 16,
+       	    "nbrOfDevicesOnDIMM": 4,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_1Gb_DDR2-1066_16bit_H",
         "memoryType": "DDR2",
@@ -52,4 +54,4 @@
             "clkMhz": 533
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 8192,
-            "width": 16
+            "width": 16,
+       	    "nbrOfDevicesOnDIMM": 4,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_1Gb_DDR2-800_16bit_H",
         "memoryType": "DDR2",
@@ -52,4 +54,4 @@
             "clkMhz": 400
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 8192,
-            "width": 16
+            "width": 16,
+       	    "nbrOfDevicesOnDIMM": 4,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G",
         "memoryType": "DDR3",
@@ -56,4 +58,4 @@
             "clkMhz": 533
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 8192,
-            "width": 16
+            "width": 16,
+       	    "nbrOfDevicesOnDIMM": 4,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G_2s",
         "memoryType": "DDR3",
@@ -56,4 +58,4 @@
             "clkMhz": 533
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 8192,
-            "width": 16
+            "width": 16,
+       	    "nbrOfDevicesOnDIMM": 4,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G_3s",
         "memoryType": "DDR3",
@@ -56,4 +58,4 @@
             "clkMhz": 533
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 8192,
-            "width": 16
+            "width": 16,
+       	    "nbrOfDevicesOnDIMM": 4,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G_mu",
         "memoryType": "DDR3",
@@ -56,4 +58,4 @@
             "clkMhz": 533
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 16384,
-            "width": 8
+            "width": 8,
+       	    "nbrOfDevicesOnDIMM": 8,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G",
         "memoryType": "DDR3",
@@ -56,4 +58,4 @@
             "clkMhz": 533
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 16384,
-            "width": 8
+            "width": 8,
+       	    "nbrOfDevicesOnDIMM": 8,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G_2s",
         "memoryType": "DDR3",
@@ -56,4 +58,4 @@
             "clkMhz": 533
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 16384,
-            "width": 8
+            "width": 8,
+       	    "nbrOfDevicesOnDIMM": 8,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G_3s",
         "memoryType": "DDR3",
@@ -56,4 +58,4 @@
             "clkMhz": 533
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 16384,
-            "width": 8
+            "width": 8,
+       	    "nbrOfDevicesOnDIMM": 8,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G_mu",
         "memoryType": "DDR3",
@@ -56,4 +58,4 @@
             "clkMhz": 533
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 16384,
-            "width": 8
+            "width": 8,
+       	    "nbrOfDevicesOnDIMM": 8,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G",
         "memoryType": "DDR3",

DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 16384,
-            "width": 8
+            "width": 8,
+       	    "nbrOfDevicesOnDIMM": 8,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G_2s",
         "memoryType": "DDR3",
@@ -56,4 +58,4 @@
             "clkMhz": 800
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 16384,
-            "width": 8
+            "width": 8,
+       	    "nbrOfDevicesOnDIMM": 8,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G_3s",
         "memoryType": "DDR3",
@@ -56,4 +58,4 @@
             "clkMhz": 800
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 16384,
-            "width": 8
+            "width": 8,
+       	    "nbrOfDevicesOnDIMM": 8,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G",
         "memoryType": "DDR3",
@@ -56,4 +58,4 @@
             "clkMhz": 800
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 16384,
-            "width": 8
+            "width": 8,
+       	    "nbrOfDevicesOnDIMM": 8,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G_mu",
         "memoryType": "DDR3",
@@ -56,4 +58,4 @@
             "clkMhz": 800
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 16384,
-            "width": 8
+            "width": 8,
+            "nbrOfDevicesOnDIMM": 8,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_1Gb_DDR3-800_8bit_G",
         "memoryType": "DDR3",
@@ -56,4 +58,4 @@
             "clkMhz": 400
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 2,
             "nbrOfRows": 16384,
-            "width": 64
+            "width": 64,
+       	    "nbrOfDevicesOnDIMM": 1,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM",
         "memoryType": "DDR3",
@@ -56,4 +58,4 @@
             "clkMhz": 533
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 2,
             "nbrOfRows": 16384,
-            "width": 64
+            "width": 64,
+       	    "nbrOfDevicesOnDIMM": 1,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_2GB_DDR3-1066_64bit_G_UDIMM",
         "memoryType": "DDR3",
@@ -56,4 +58,4 @@
             "clkMhz": 533
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 2,
             "nbrOfRows": 16384,
-            "width": 64
+            "width": 64,
+       	    "nbrOfDevicesOnDIMM": 1,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_2GB_DDR3-1333_64bit_D_SODIMM",
         "memoryType": "DDR3",
@@ -56,4 +58,4 @@
             "clkMhz": 666
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 2,
             "nbrOfRows": 16384,
-            "width": 64
+            "width": 64,
+       	    "nbrOfDevicesOnDIMM": 1,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_2GB_DDR3-1600_64bit_G_UDIMM",
         "memoryType": "DDR3",
@@ -56,4 +58,4 @@
             "clkMhz": 800
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 32768,
-            "width": 8
+            "width": 8,
+       	    "nbrOfDevicesOnDIMM": 8,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D",
         "memoryType": "DDR3",
@@ -56,4 +58,4 @@
             "clkMhz": 533
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 32768,
-            "width": 8
+            "width": 8,
+       	    "nbrOfDevicesOnDIMM": 8,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D_2s",
         "memoryType": "DDR3",
@@ -56,4 +58,4 @@
             "clkMhz": 533
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 32768,
-            "width": 8
+            "width": 8,
+       	    "nbrOfDevicesOnDIMM": 8,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D_3s",
         "memoryType": "DDR3",
@@ -56,4 +58,4 @@
             "clkMhz": 533
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 32768,
-            "width": 8
+            "width": 8,
+       	    "nbrOfDevicesOnDIMM": 8,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D_mu",
         "memoryType": "DDR3",
@@ -56,4 +58,4 @@
             "clkMhz": 533
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 16384,
-            "width": 16
+            "width": 16,
+       	    "nbrOfDevicesOnDIMM": 4,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D",
         "memoryType": "DDR3",
@@ -56,4 +58,4 @@
             "clkMhz": 800
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 16384,
-            "width": 16
+            "width": 16,
+       	    "nbrOfDevicesOnDIMM": 4,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D_2s",
         "memoryType": "DDR3",
@@ -56,4 +58,4 @@
             "clkMhz": 800
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 16384,
-            "width": 16
+            "width": 16,
+       	    "nbrOfDevicesOnDIMM": 4,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D_3s",
         "memoryType": "DDR3",
@@ -56,4 +58,4 @@
             "clkMhz": 800
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 16384,
-            "width": 16
+            "width": 16,
+       	    "nbrOfDevicesOnDIMM": 4,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D_mu",
         "memoryType": "DDR3",
@@ -56,4 +58,4 @@
             "clkMhz": 800
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json

@@ -7,7 +7,8 @@
             "nbrOfColumns": 2048,
             "nbrOfRanks": 1,
             "nbrOfRows": 16384,
-            "width": 16
+            "width": 16,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_2Gb_LPDDR-266_16bit_A",
         "memoryType": "LPDDR",
@@ -51,4 +52,4 @@
             "clkMhz": 133
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json

@@ -7,7 +7,8 @@
             "nbrOfColumns": 2048,
             "nbrOfRanks": 1,
             "nbrOfRows": 16384,
-            "width": 16
+            "width": 16,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_2Gb_LPDDR-333_16bit_A",
         "memoryType": "LPDDR",
@@ -51,4 +52,4 @@
             "clkMhz": 166
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json

@@ -7,7 +7,8 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 16384,
-            "width": 16
+            "width": 16,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_2Gb_LPDDR2-1066-S4_16bit_A",
         "memoryType": "LPDDR2",
@@ -64,4 +65,4 @@
             "clkMhz": 533
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json

@@ -7,7 +7,8 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 16384,
-            "width": 16
+            "width": 16,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_2Gb_LPDDR2-800-S4_16bit_A",
         "memoryType": "LPDDR2",
@@ -64,4 +65,4 @@
             "clkMhz": 400
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json

@@ -8,7 +8,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 32768,
-            "width": 8
+            "width": 8,
+            "nbrOfDevicesOnDIMM": 8,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A",
         "memoryType": "DDR4",
@@ -63,4 +65,4 @@
             "clkMhz": 933
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json

@@ -8,7 +8,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 32768,
-            "width": 8
+            "width": 8,
+            "nbrOfDevicesOnDIMM": 8,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_4Gb_DDR4-2400_8bit_A",
         "memoryType": "DDR4",
@@ -63,4 +65,4 @@
             "clkMhz": 1200
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json

@@ -7,7 +7,8 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 16384,
-            "width": 32
+            "width": 32,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_4Gb_LPDDR3-1333_32bit_A",
         "memoryType": "LPDDR3",
@@ -64,4 +65,4 @@
             "clkMhz": 667
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json

@@ -7,7 +7,8 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 16384,
-            "width": 32
+            "width": 32,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_4Gb_LPDDR3-1600_32bit_A",
         "memoryType": "LPDDR3",
@@ -64,4 +65,4 @@
             "clkMhz": 800
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json

@@ -7,7 +7,8 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 49152,
-            "width": 16
+            "width": 16,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_6Gb_LPDDR3-3200_16bit_A",
         "memoryType": "LPDDR4",
@@ -92,4 +93,4 @@
             "clkMhz": 1600
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 8192,
-            "width": 16
+            "width": 16,
+            "nbrOfChannels": 1,
+            "nbrOfDevicesOnDIMM": 1,
         },
         "memoryId": "SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit",
         "memoryType": "DDR3",
@@ -56,4 +58,4 @@
             "clkMhz": 800
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json

@@ -7,7 +7,9 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 1,
             "nbrOfRows": 32768,
-            "width": 16
+            "width": 16,
+       	    "nbrOfDevicesOnDIMM": 1,
+            "nbrOfChannels": 1
         },
         "memoryId": "SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit",
         "memoryType": "DDR3",
@@ -56,4 +58,4 @@
             "clkMhz": 533
         }
     }
-}
+}

DRAMSys/library/resources/configs/memspecs/memspec_ranktest.json

@@ -7,7 +7,8 @@
             "nbrOfColumns": 1024,
             "nbrOfRanks": 4,
             "nbrOfRows": 16384,
-            "width": 8
+            "width": 8,
+            "nbrOfChannels": 1
         },
         "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G",
         "memoryType": "DDR3",
@@ -56,4 +57,4 @@
             "clkMhz": 800
         }
     }
-}
+}

DRAMSys/library/resources/configs/simulator/ddr3-single-device.json

@@ -8,8 +8,6 @@
         "EnableWindowing": true,
         "ErrorCSVFile": "",
         "ErrorChipSeed": 42,
-        "NumberOfDevicesOnDIMM": 1,
-        "NumberOfMemChannels": 1,
         "PowerAnalysis": true,
         "SimulationName": "ddr3_single_dev",
         "SimulationProgressBar": true,
@@ -18,4 +16,4 @@
         "UseMalloc": false,
         "WindowSize": 1000
     }
-}
+}

DRAMSys/library/resources/configs/simulator/ddr3.json

@@ -8,8 +8,6 @@
         "EnableWindowing": false,
         "ErrorCSVFile": "",
         "ErrorChipSeed": 42,
-        "NumberOfDevicesOnDIMM": 8,
-        "NumberOfMemChannels": 1,
         "PowerAnalysis": false,
         "SimulationName": "ddr3",
         "SimulationProgressBar": true,

DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.json

@@ -8,8 +8,6 @@
         "EnableWindowing": true,
         "ErrorCSVFile": "",
         "ErrorChipSeed": 42,
-        "NumberOfDevicesOnDIMM": 8,
-        "NumberOfMemChannels": 1,
         "PowerAnalysis": true,
         "SimulationName": "ddr3",
         "SimulationProgressBar": true,
@@ -18,4 +16,4 @@
         "UseMalloc": true,
         "WindowSize": 1000
     }
-}
+}

DRAMSys/library/resources/configs/simulator/ddr3_ecc.json

@@ -8,8 +8,6 @@
         "EnableWindowing": true,
         "ErrorCSVFile": "",
         "ErrorChipSeed": 42,
-        "NumberOfDevicesOnDIMM": 8,
-        "NumberOfMemChannels": 1,
         "PowerAnalysis": true,
         "SimulationName": "ddr3",
         "SimulationProgressBar": true,
@@ -18,4 +16,4 @@
         "UseMalloc": false,
         "WindowSize": 1000
     }
-}
+}

DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.json

@@ -8,8 +8,6 @@
         "EnableWindowing": true,
         "ErrorCSVFile": "",
         "ErrorChipSeed": 42,
-        "NumberOfDevicesOnDIMM": 8,
-        "NumberOfMemChannels": 1,
         "PowerAnalysis": true,
         "SimulationName": "ddr3",
         "SimulationProgressBar": true,
@@ -18,4 +16,4 @@
         "UseMalloc": false,
         "WindowSize": 1000
     }
-}
+}

DRAMSys/library/resources/configs/simulator/ddr4.json

@@ -8,8 +8,6 @@
         "EnableWindowing": false,
         "ErrorCSVFile": "",
         "ErrorChipSeed": 42,
-        "NumberOfDevicesOnDIMM": 8,
-        "NumberOfMemChannels": 1,
         "PowerAnalysis": false,
         "SimulationName": "ddr4",
         "SimulationProgressBar": true,
@@ -18,4 +16,4 @@
         "UseMalloc": false,
         "WindowSize": 1000
     }
-}
+}

DRAMSys/library/resources/configs/simulator/hbm2.json

@@ -8,8 +8,6 @@
         "EnableWindowing": false,
         "ErrorCSVFile": "",
         "ErrorChipSeed": 42,
-        "NumberOfDevicesOnDIMM": 1,
-        "NumberOfMemChannels": 1,
         "PowerAnalysis": false,
         "SimulationName": "hbm2",
         "SimulationProgressBar": true,
@@ -18,4 +16,4 @@
         "UseMalloc": false,
         "WindowSize": 1000
     }
-}
+}

DRAMSys/library/resources/configs/simulator/lpddr4.json

@@ -8,7 +8,6 @@
         "EnableWindowing": false,
         "ErrorCSVFile": "",
         "ErrorChipSeed": 42,
-        "NumberOfDevicesOnDIMM": 1,
         "NumberOfMemChannels": 1,
         "PowerAnalysis": false,
         "SimulationName": "lpddr4",
@@ -18,4 +17,4 @@
         "UseMalloc": false,
         "WindowSize": 1000
     }
-}
+}

DRAMSys/library/resources/configs/simulator/wideio.json

@@ -7,8 +7,6 @@
         "EnableWindowing": true,
         "ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv",
         "ErrorChipSeed": 42,
-        "NumberOfDevicesOnDIMM": 1,
-        "NumberOfMemChannels": 4,
         "PowerAnalysis": true,
         "SimulationName": "wideio",
         "SimulationProgressBar": true,
@@ -17,4 +15,4 @@
         "UseMalloc": false,
         "WindowSize": 1000
     }
-}
+}

DRAMSys/library/resources/configs/simulator/wideio_ecc.json

@@ -7,8 +7,6 @@
         "EnableWindowing": true,
         "ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv",
         "ErrorChipSeed": 42,
-        "NumberOfDevicesOnDIMM": 1,
-        "NumberOfMemChannels": 1,
         "PowerAnalysis": true,
         "SimulationName": "wideio_ecc",
         "SimulationProgressBar": true,
@@ -17,4 +15,4 @@
         "UseMalloc": false,
         "WindowSize": 1000
     }
-}
+}

DRAMSys/library/resources/configs/simulator/wideio_thermal.json

@@ -7,8 +7,6 @@
         "EnableWindowing": true,
         "ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv",
         "ErrorChipSeed": 42,
-        "NumberOfDevicesOnDIMM": 1,
-        "NumberOfMemChannels": 4,
         "PowerAnalysis": true,
         "SimulationName": "wideio",
         "SimulationProgressBar": true,
@@ -17,4 +15,4 @@
         "UseMalloc": false,
         "WindowSize": 1000
     }
-}
+}

DRAMSys/library/src/common/AddressDecoder.cpp

@@ -143,10 +143,10 @@ AddressDecoder::AddressDecoder(std::string pathToAddressMapping)
     Configuration &config = Configuration::getInstance();
     MemSpec *memSpec = config.memSpec;
 
-    if (config.numberOfMemChannels != channels || memSpec->numberOfRanks != ranks
+    if (memSpec->numberOfChannels != channels || memSpec->numberOfRanks != ranks
             || memSpec->numberOfBankGroups != bankgroups || memSpec->numberOfBanks != banks
             || memSpec->numberOfRows != rows || memSpec->numberOfColumns != columns
-            || config.numberOfDevicesOnDIMM * memSpec->bitWidth != bytes * 8)
+            || memSpec->numberOfDevicesOnDIMM * memSpec->bitWidth != bytes * 8)
         SC_REPORT_FATAL("AddressDecoder", "Memspec and address mapping do not match");
 }
 

DRAMSys/library/src/configuration/Configuration.cpp

@@ -121,20 +121,10 @@ void Configuration::setParameter(std::string name, nlohmann::json value)
     }
     else if (name == "Debug")
         debug = value;
-    else if (name == "NumberOfMemChannels")
-        numberOfMemChannels = value;
     else if (name == "ThermalSimulation")
         thermalSimulation = value;
     else if (name == "SimulationProgressBar")
         simulationProgressBar = value;
-    else if (name == "NumberOfDevicesOnDIMM")
-    {
-        numberOfDevicesOnDIMM = value;
-        if (numberOfDevicesOnDIMM == 0)
-            SC_REPORT_FATAL("Configuration",
-                            ("Invalid value for parameter " + name +
-                             ". This parameter must be at least one.").c_str());
-    }
     else if (name == "AddressOffset")
     {
 #ifdef DRAMSYS_GEM5
@@ -209,12 +199,13 @@ std::uint64_t Configuration::getSimMemSizeInBytes()
     std::uint64_t rows = memSpec->numberOfRows;
     std::uint64_t columns = memSpec->numberOfColumns;
     std::uint64_t bitWidth = memSpec->bitWidth;
+    std::uint64_t devicesOnDIMM = memSpec->numberOfDevicesOnDIMM;
     // 2. Calculate size of one DRAM chip in bits
     std::uint64_t chipBitSize = banks * rows * columns * bitWidth;
     // 3. Calculate size of one DRAM chip in bytes
     std::uint64_t chipSize = chipBitSize / 8;
     // 4. Total memory size in Bytes of one DIMM (with only support of 1 rank on a DIMM)
-    std::uint64_t memorySize = chipSize * numberOfDevicesOnDIMM;
+    std::uint64_t memorySize = chipSize * memSpec->numberOfDevicesOnDIMM;
 
     std::cout << headline << std::endl;
     std::cout << "Per Channel Configuration:" << std::endl << std::endl;
@@ -228,7 +219,7 @@ std::uint64_t Configuration::getSimMemSizeInBytes()
     std::cout << " Chip data bus width:   " << bitWidth              << std::endl;
     std::cout << " Chip size in bits:     " << chipBitSize           << std::endl;
     std::cout << " Chip Size in bytes:    " << chipSize              << std::endl;
-    std::cout << " Devices/Chips on DIMM: " << numberOfDevicesOnDIMM << std::endl;
+    std::cout << " Devices/Chips on DIMM: " << devicesOnDIMM         << std::endl;
     std::cout << std::endl;
 
     assert(memorySize > 0);
@@ -241,7 +232,7 @@ std::uint64_t Configuration::getSimMemSizeInBytes()
 // The bus width is given in bits, e.g., 64-bit data bus, 128-bit data bus, etc.
 unsigned int Configuration::getDataBusWidth()
 {
-    return memSpec->bitWidth * numberOfDevicesOnDIMM;
+    return memSpec->bitWidth * memSpec->numberOfDevicesOnDIMM;
 }
 
 // Returns the number of bytes transfered in a burst

DRAMSys/library/src/configuration/Configuration.h

@@ -88,10 +88,8 @@ public:
     bool enableWindowing = false;
     unsigned int windowSize = 1000;
     bool debug = false;
-    unsigned int numberOfMemChannels = 1;
     bool thermalSimulation = false;
     bool simulationProgressBar = false;
-    unsigned int numberOfDevicesOnDIMM = 8;
     bool checkTLM2Protocol = false;
     std::string ECCMode = "Disabled";
     ECCBaseClass *pECC = nullptr;

DRAMSys/library/src/configuration/memspec/MemSpec.cpp

@@ -43,15 +43,19 @@
 using namespace tlm;
 using json = nlohmann::json;
 
-MemSpec::MemSpec(json &memspec, unsigned numberOfRanks, unsigned banksPerRank,
+MemSpec::MemSpec(json &memspec, unsigned numberOfChannels,
+                 unsigned numberOfRanks, unsigned banksPerRank,
                  unsigned groupsPerRank, unsigned banksPerGroup,
-                 unsigned numberOfBanks, unsigned numberOfBankGroups)
-    : numberOfRanks(numberOfRanks),
+                 unsigned numberOfBanks, unsigned numberOfBankGroups,
+                 unsigned numberOfDevicesOnDIMM)
+    : numberOfChannels(numberOfChannels),
+      numberOfRanks(numberOfRanks),
       banksPerRank(banksPerRank),
       groupsPerRank(groupsPerRank),
       banksPerGroup(banksPerGroup),
       numberOfBanks(numberOfBanks),
       numberOfBankGroups(numberOfBankGroups),
+      numberOfDevicesOnDIMM(numberOfDevicesOnDIMM),
       numberOfRows(parseUint(memspec["memarchitecturespec"]["nbrOfRows"],"nbrOfRows")),
       numberOfColumns(parseUint(memspec["memarchitecturespec"]["nbrOfColumns"],"nbrOfColumns")),
       burstLength(parseUint(memspec["memarchitecturespec"]["burstLength"],"burstLength")),
@@ -59,9 +63,9 @@ MemSpec::MemSpec(json &memspec, unsigned numberOfRanks, unsigned banksPerRank,
       bitWidth(parseUint(memspec["memarchitecturespec"]["width"],"width")),
       fCKMHz(parseUdouble(memspec["memtimingspec"]["clkMhz"], "clkMhz")),
       tCK(sc_time(1.0 / fCKMHz, SC_US)),
-      burstDuration(tCK * (burstLength / dataRate)),
       memoryId(parseString(memspec["memoryId"], "memoryId")),
-      memoryType(parseString(memspec["memoryType"], "memoryType"))
+      memoryType(parseString(memspec["memoryType"], "memoryType")),
+      burstDuration(tCK * (burstLength / dataRate))
 {
     commandLengthInCycles = std::vector<unsigned>(numberOfCommands(), 1);
 }

DRAMSys/library/src/configuration/memspec/MemSpec.h

@@ -48,12 +48,14 @@
 class MemSpec
 {
 public:
+    unsigned numberOfChannels;
     unsigned numberOfRanks;
     unsigned banksPerRank;
     unsigned groupsPerRank;
     unsigned banksPerGroup;
     unsigned numberOfBanks;
     unsigned numberOfBankGroups;
+    unsigned numberOfDevicesOnDIMM;
     unsigned numberOfRows;
     unsigned numberOfColumns;
     unsigned burstLength;
@@ -78,9 +80,11 @@ public:
     sc_time getCommandLength(Command) const;
 
 protected:
-    MemSpec(nlohmann::json &memspec, unsigned numberOfRanks, unsigned banksPerRank,
+    MemSpec(nlohmann::json &memspec, unsigned numberOfChannels,
+            unsigned numberOfRanks, unsigned banksPerRank,
             unsigned groupsPerRank, unsigned banksPerGroup,
-            unsigned numberOfBanks, unsigned numberOfBankGroups);
+            unsigned numberOfBanks, unsigned numberOfBankGroups,
+            unsigned numberOfDevicesOnDIMM);
 
     // Command lengths in cycles on bus, usually one clock cycle
     std::vector<unsigned> commandLengthInCycles;

DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp

@@ -40,13 +40,15 @@ using json = nlohmann::json;
 
 MemSpecDDR3::MemSpecDDR3(json &memspec)
     : MemSpec(memspec,
+      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
       parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
       parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
       1,
       parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
       parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
           * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
+      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"]["nbrOfDevicesOnDIMM"],"nbrOfDevicesOnDIMM")),
       tCKE     (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
       tPD      (tCKE),
       tCKESR   (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")),

DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp

@@ -41,6 +41,7 @@ using json = nlohmann::json;
 
 MemSpecDDR4::MemSpecDDR4(json &memspec)
     : MemSpec(memspec,
+      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
       parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
       parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
       parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
@@ -49,7 +50,8 @@ MemSpecDDR4::MemSpecDDR4(json &memspec)
       parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
           * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
       parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups")
-          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
+          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"]["nbrOfDevicesOnDIMM"],"nbrOfDevicesOnDIMM")),
       tCKE     (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
       tPD      (tCKE),
       tCKESR   (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")),

DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp

@@ -40,6 +40,7 @@ using json = nlohmann::json;
 
 MemSpecGDDR5::MemSpecGDDR5(json &memspec)
     : MemSpec(memspec,
+      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
       parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
       parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
       parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
@@ -48,7 +49,8 @@ MemSpecGDDR5::MemSpecGDDR5(json &memspec)
       parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
           * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
       parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups")
-          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
+          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
+      1),
       tRP        (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
       tRAS       (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
       tRC        (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),

DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp

@@ -40,6 +40,7 @@ using json = nlohmann::json;
 
 MemSpecGDDR5X::MemSpecGDDR5X(json &memspec)
     : MemSpec(memspec,
+      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
       parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
       parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
       parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
@@ -48,7 +49,8 @@ MemSpecGDDR5X::MemSpecGDDR5X(json &memspec)
       parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
           * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
       parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups")
-          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
+          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
+      1),
       tRP        (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
       tRAS       (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
       tRC        (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),

DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp

@@ -40,6 +40,7 @@ using json = nlohmann::json;
 
 MemSpecGDDR6::MemSpecGDDR6(json &memspec)
     : MemSpec(memspec,
+      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
       parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
       parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
       parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
@@ -48,7 +49,8 @@ MemSpecGDDR6::MemSpecGDDR6(json &memspec)
       parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
           * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
       parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups")
-          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
+          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
+      1),
       tRP        (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
       tRAS       (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
       tRC        (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),

DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp

@@ -40,6 +40,7 @@ using json = nlohmann::json;
 
 MemSpecHBM2::MemSpecHBM2(json &memspec)
     : MemSpec(memspec,
+      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
       parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
       parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
       parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
@@ -48,7 +49,8 @@ MemSpecHBM2::MemSpecHBM2(json &memspec)
       parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
           * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
       parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups")
-          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
+          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
+      1),
       tDQSCK  (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")),
       tRC     (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),
       tRAS    (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),

DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp

@@ -40,13 +40,15 @@ using json = nlohmann::json;
 
 MemSpecLPDDR4::MemSpecLPDDR4(json &memspec)
     : MemSpec(memspec,
+      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
       parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
       parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
       1,
       parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
       parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
           * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
+      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
+      1),
       tREFI   (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")),
       tREFIpb (tCK * parseUint(memspec["memtimingspec"]["REFIPB"], "REFIPB")),
       tRFCab  (tCK * parseUint(memspec["memtimingspec"]["RFCAB"], "RFCAB")),

DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp

@@ -40,13 +40,15 @@ using json = nlohmann::json;
 
 MemSpecWideIO::MemSpecWideIO(json &memspec)
     : MemSpec(memspec,
+      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
       parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
       parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
       1,
       parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
       parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
           * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
+      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
+      1),
       tCKE    (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
       tCKESR  (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")),
       tDQSCK  (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")),

DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp

@@ -40,13 +40,15 @@ using json = nlohmann::json;
 
 MemSpecWideIO2::MemSpecWideIO2(json &memspec)
     : MemSpec(memspec,
+      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
       parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
       parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
       1,
       parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
       parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
           * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")),
+      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
+      1),
       tDQSCK  (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")),
       tDQSS   (tCK * parseUint(memspec["memtimingspec"]["DQSS"], "DQSS")),
       tCKE    (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),

DRAMSys/library/src/controller/ControllerIF.h

@@ -35,7 +35,7 @@ public:
                                   // BusWidth e.g. 8 or 64
                                   * Configuration::getInstance().memSpec->bitWidth
                                   //   Number of devices on a DIMM e.g. 8
-                                  * Configuration::getInstance().numberOfDevicesOnDIMM ) / ( 1024 );
+                                  * Configuration::getInstance().memSpec->numberOfDevicesOnDIMM ) / ( 1024 );
 
         std::cout << name() << std::string("  Total Time:     ")
              << sc_time_stamp().to_string()

DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp

@@ -164,7 +164,7 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, Bank
     }
     else if (command == Command::ACT)
     {
-        lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][rank.ID()];
+        lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
         if (lastCommandStart != SC_ZERO_TIME)
             earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCpb);
 

DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp

@@ -91,14 +91,17 @@ sc_time RefreshManagerBankwise::start()
             bool forcedRefresh = (flexibilityCounter == maxPostponed);
             bool allBanksBusy = true;
 
-            for (auto it = remainingBankMachines.begin(); it != remainingBankMachines.end(); it++)
+            if (!skipSelection)
             {
-                if ((*it)->isIdle())
+                for (auto it = remainingBankMachines.begin(); it != remainingBankMachines.end(); it++)
                 {
-                    currentIterator = it;
-                    currentBankMachine = *it;
-                    allBanksBusy = false;
-                    break;
+                    if ((*it)->isIdle())
+                    {
+                        currentIterator = it;
+                        currentBankMachine = *it;
+                        allBanksBusy = false;
+                        break;
+                    }
                 }
             }
 
@@ -113,7 +116,16 @@ sc_time RefreshManagerBankwise::start()
                 if (currentBankMachine->getState() == BmState::Activated)
                     nextCommand = Command::PRE;
                 else
+                {
                     nextCommand = Command::REFB;
+
+                    if (forcedRefresh)
+                    {
+                        currentBankMachine->block();
+                        skipSelection = true;
+                    }
+                }
+
                 timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank,
                         currentBankMachine->getBankGroup(), currentBankMachine->getBank());
                 return timeToSchedule;
@@ -161,6 +173,7 @@ void RefreshManagerBankwise::updateState(Command command, tlm_generic_payload *p
     switch (command)
     {
     case Command::REFB:
+        skipSelection = false;
         remainingBankMachines.erase(currentIterator);
         if (remainingBankMachines.empty())
             remainingBankMachines = allBankMachines;

DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h

@@ -74,6 +74,7 @@ private:
     int maxPulledin = 0;
 
     bool sleeping = false;
+    bool skipSelection = false;
 };
 
 #endif // REFRESHMANAGERBANKWISE_H

DRAMSys/library/src/simulation/Arbiter.cpp

@@ -49,7 +49,7 @@ Arbiter::Arbiter(sc_module_name name, std::string pathToAddressMapping) :
     // Anytime an transaction comes from a memory unity to the arbiter the "bw" callback is called.
     iSocket.register_nb_transport_bw(this, &Arbiter::nb_transport_bw);
 
-    for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; ++i)
+    for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; ++i)
     {
         channelIsFree.push_back(true);
         pendingRequests.push_back(std::queue<tlm_generic_payload *>());
@@ -130,7 +130,7 @@ void Arbiter::peqCallback(tlm_generic_payload &payload, const tlm_phase &phase)
 
     // Check the valid range of thread ID and channel Id
     // TODO: thread ID not checked
-    assert(channelId < Configuration::getInstance().numberOfMemChannels);
+    assert(channelId < Configuration::getInstance().memSpec->numberOfChannels);
 
     // Phases initiated by the intiator side from arbiter's point of view (devices performing memory requests to the arbiter)
     if (phase == BEGIN_REQ)

DRAMSys/library/src/simulation/DRAMSys.cpp

@@ -192,7 +192,7 @@ void DRAMSys::instantiateModules(const std::string &pathToResources,
 
     // Create controllers and DRAMs
     std::string memoryType = Configuration::getInstance().memSpec->memoryType;
-    for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++)
+    for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++)
     {
         std::string str = "controller" + std::to_string(i);
 
@@ -251,7 +251,7 @@ void DRAMSys::bindSockets()
 
     if (Configuration::getInstance().checkTLM2Protocol)
     {
-        for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++)
+        for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++)
         {
             arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket);
             controllersTlmCheckers[i]->initiator_socket.bind(controllers[i]->tSocket);
@@ -260,7 +260,7 @@ void DRAMSys::bindSockets()
     }
     else
     {
-        for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++)
+        for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++)
         {
             arbiter->iSocket.bind(controllers[i]->tSocket);
             controllers[i]->iSocket.bind(drams[i]->tSocket);

DRAMSys/library/src/simulation/DRAMSysRecordable.cpp

@@ -91,7 +91,7 @@ void DRAMSysRecordable::setupTlmRecorders(const std::string &traceName,
                                           const std::string &pathToResources)
 {
     // Create TLM Recorders, one per channel.
-    for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++)
+    for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++)
     {
         std::string sqlScriptURI = pathToResources
                                    + std::string("scripts/createTraceDB.sql");
@@ -140,7 +140,7 @@ void DRAMSysRecordable::instantiateModules(const std::string &traceName,
 
     // Create controllers and DRAMs
     std::string memoryType = Configuration::getInstance().memSpec->memoryType;
-    for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++)
+    for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++)
     {
         std::string str = "controller" + std::to_string(i);
 
@@ -199,7 +199,7 @@ void DRAMSysRecordable::bindSockets()
 
     if (Configuration::getInstance().checkTLM2Protocol)
     {
-        for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++)
+        for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++)
         {
             arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket);
             controllersTlmCheckers[i]->initiator_socket.bind(controllers[i]->tSocket);
@@ -208,7 +208,7 @@ void DRAMSysRecordable::bindSockets()
     }
     else
     {
-        for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++)
+        for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++)
         {
             arbiter->iSocket.bind(controllers[i]->tSocket);
             controllers[i]->iSocket.bind(drams[i]->tSocket);

DRAMSys/library/src/simulation/dram/Dram.cpp

@@ -129,14 +129,14 @@ void Dram::reportPower()
         std::cout << name() << std::string("  Total Energy:   ")
              << std::fixed << std::setprecision( 2 )
              << DRAMPower->getEnergy().total_energy
-             * Configuration::getInstance().numberOfDevicesOnDIMM
+             * Configuration::getInstance().memSpec->numberOfDevicesOnDIMM
              << std::string(" pJ")
              << std::endl;
 
         std::cout << name() << std::string("  Average Power:  ")
              << std::fixed << std::setprecision( 2 )
              << DRAMPower->getPower().average_power
-             * Configuration::getInstance().numberOfDevicesOnDIMM
+             * Configuration::getInstance().memSpec->numberOfDevicesOnDIMM
              << std::string(" mW") << std::endl;
     }
 }

DRAMSys/library/src/simulation/dram/DramRecordable.cpp

@@ -67,7 +67,7 @@ void DramRecordable<BaseDram>::reportPower()
     BaseDram::reportPower();
     tlmRecorder->recordPower(sc_time_stamp().to_seconds(),
                          this->DRAMPower->getPower().window_average_power
-                         * Configuration::getInstance().numberOfDevicesOnDIMM);
+                         * Configuration::getInstance().memSpec->numberOfDevicesOnDIMM);
 }
 
 template<class BaseDram>
@@ -132,15 +132,15 @@ void DramRecordable<BaseDram>::powerWindow()
         // Store the time (in seconds) and the current average power (in mW) into the database
         tlmRecorder->recordPower(sc_time_stamp().to_seconds(),
                                  this->DRAMPower->getPower().window_average_power
-                                 * Configuration::getInstance().numberOfDevicesOnDIMM);
+                                 * Configuration::getInstance().memSpec->numberOfDevicesOnDIMM);
 
         // Here considering that DRAMPower provides the energy in pJ and the power in mW
         PRINTDEBUGMESSAGE(this->name(), std::string("\tWindow Energy: \t") + std::to_string(
                               this->DRAMPower->getEnergy().window_energy *
-                              Configuration::getInstance().numberOfDevicesOnDIMM) + std::string("\t[pJ]"));
+                              Configuration::getInstance().memSpec->numberOfDevicesOnDIMM) + std::string("\t[pJ]"));
         PRINTDEBUGMESSAGE(this->name(), std::string("\tWindow Average Power: \t") + std::to_string(
                               this->DRAMPower->getPower().window_average_power *
-                              Configuration::getInstance().numberOfDevicesOnDIMM) + std::string("\t[mW]"));
+                              Configuration::getInstance().memSpec->numberOfDevicesOnDIMM) + std::string("\t[mW]"));
 
     } while (true);
 }

DRAMSys/simulator/CMakeLists.txt

@@ -38,6 +38,12 @@ project(DRAMSysSimulator)
 # Configuration:
 set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version")
 set(DCMAKE_SH="CMAKE_SH-NOTFOUND")
+if(DEFINED ENV{COVERAGE})
+    set(GCC_COVERAGE_COMPILE_FLAGS "-g -O0 -coverage -fprofile-arcs -ftest-coverage")
+    set(GCC_COVERAGE_LINK_FLAGS "-coverage -lgcov")
+    set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}")
+    set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${GCC_COVERAGE_LINK_FLAGS}")
+endif()
 
 if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/../library/src/simulation/DRAMSysRecordable.cpp)
     add_definitions(-DRECORDING)

DRAMSys/tests/DDR3/ci.yml

@@ -1,83 +0,0 @@
-# Standard DDR3 Test:
-example_ddr3:
-    stage: DDR3
-    script:
-        - export GCOV_PREFIX=$(pwd)
-        - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}')
-        - cd build/simulator
-        - ./DRAMSys ../../DRAMSys/tests/DDR3/simulations/ddr3-example.xml ../../DRAMSys/tests/DDR3/
-        - ls -lah
-        - ls -lah ../../DRAMSys/tests/DDR3/expected/
-        - sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-example_ddr3_ch0.tdb ddr3-example_ddr3_ch0.tdb
-        - perl -e 'if(`sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-example_ddr3_ch0.tdb ddr3-example_ddr3_ch0.tdb` eq "") {exit(0)} else {exit(-1)}'
-        - cd ../traceAnalyzer
-        - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/ddr3-example_ddr3_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi
-        # Run Code Coverage
-        - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out
- 
-    cache:
-        key: build
-        paths:
-            - build/
-        policy: pull
-
-    artifacts:
-        paths:
-          - build/simulator/ddr3-example_ddr3_ch0.tdb
-          - coverage/${CI_JOB_NAME}.out
-        expire_in: 2 days
-
-# Testing Reordering with FR_FCFS Scheduling Algorithm:
-fr_fcfs:
-    stage: DDR3
-    script:
-        - export GCOV_PREFIX=$(pwd)
-        - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}')
-        - cd build/simulator
-        - ./DRAMSys ../../DRAMSys/tests/DDR3/simulations/ddr3-fr_fcfs.xml ../../DRAMSys/tests/DDR3/
-        - ls -lah
-        - ls -lah ../../DRAMSys/tests/DDR3/expected/
-        - sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-fr_fcfs_ddr3_ch0.tdb ddr3-fr_fcfs_ddr3_ch0.tdb
-        - perl -e 'if(`sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-fr_fcfs_ddr3_ch0.tdb ddr3-fr_fcfs_ddr3_ch0.tdb` eq "") {exit(0)} else {exit(-1)}'
-        - cd ../traceAnalyzer
-        - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/ddr3-fr_fcfs_ddr3_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi
-        # Run Code Coverage
-        - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out
-
-    cache:
-        key: build
-        paths:
-            - build/
-        policy: pull
-
-    allow_failure: true # TODO should be removed after first tests
-
-    artifacts:
-        paths:
-          - build/simulator/ddr3-fr_fcfs_ddr3_ch0.tdb
-          - coverage/${CI_JOB_NAME}.out
-        expire_in: 2 days
-
-# Testing with TLM Protocol Checker
-protocol_checker:
-    stage: DDR3
-    script:
-        - export GCOV_PREFIX=$(pwd)
-        - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}')
-        - cd build/simulator
-        - ./DRAMSys ../../DRAMSys/tests/DDR3/simulations/ddr3-protocol_checker.xml ../../DRAMSys/tests/DDR3/ > output.txt
-        - echo "TODO"
-        - ls -lah
-        # Run Code Coverage
-        - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out
-
-    cache:
-        key: build
-        paths:
-            - build/
-        policy: pull
-
-    artifacts:
-        paths:
-            - coverage/${CI_JOB_NAME}.out
-        expire_in: 2 days

DRAMSys/tests/DDR3/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml

@@ -1,34 +0,0 @@
-<CONGEN>
-    <SOLUTION ID="0">
-        <BYTE_BIT>0</BYTE_BIT>
-        <BYTE_BIT>1</BYTE_BIT>
-        <BYTE_BIT>2</BYTE_BIT>
-        <COLUMN_BIT>3</COLUMN_BIT>
-        <COLUMN_BIT>4</COLUMN_BIT>
-        <COLUMN_BIT>5</COLUMN_BIT>
-        <COLUMN_BIT>6</COLUMN_BIT>
-        <COLUMN_BIT>7</COLUMN_BIT>
-        <COLUMN_BIT>8</COLUMN_BIT>
-        <COLUMN_BIT>9</COLUMN_BIT>
-        <COLUMN_BIT>10</COLUMN_BIT>
-        <COLUMN_BIT>11</COLUMN_BIT>
-        <COLUMN_BIT>12</COLUMN_BIT>
-        <ROW_BIT>13</ROW_BIT>
-        <ROW_BIT>14</ROW_BIT>
-        <ROW_BIT>15</ROW_BIT>
-        <ROW_BIT>16</ROW_BIT>
-        <ROW_BIT>17</ROW_BIT>
-        <ROW_BIT>18</ROW_BIT>
-        <ROW_BIT>19</ROW_BIT>
-        <ROW_BIT>20</ROW_BIT>
-        <ROW_BIT>21</ROW_BIT>
-        <ROW_BIT>22</ROW_BIT>
-        <ROW_BIT>23</ROW_BIT>
-        <ROW_BIT>24</ROW_BIT>
-        <ROW_BIT>25</ROW_BIT>
-        <ROW_BIT>26</ROW_BIT>
-        <BANK_BIT>27</BANK_BIT>
-        <BANK_BIT>28</BANK_BIT>
-        <BANK_BIT>29</BANK_BIT>
-    </SOLUTION>
-</CONGEN>

DRAMSys/tests/DDR3/configs/mcconfigs/fifoStrict.xml

@@ -1,20 +0,0 @@
-<mcconfig>
-	<!-- Open, OpenAdaptive, Closed, ClosedAdaptive -->
-	<PagePolicy value="Open" />
-	<!-- Fifo, FrFcfs, FrFcfsGrp -->
-    <Scheduler value="Fifo" />
-	<RequestBufferSize value="8" />
-	<!-- Oldest, Strict -->
-	<CmdMux value="Strict" />
-	<!-- Fifo, Reorder -->
-	<RespQueue value="Fifo" />
-	<!-- NoRefresh, Rankwise, Bankwise -->
-	<RefreshPolicy value="Rankwise" />
-	<!-- 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
-	<RefreshMode value="1" />
-	<RefreshMaxPostponed value="0"/>
-    <RefreshMaxPulledin value="0"/>
-    <!-- NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
-    <PowerDownPolicy value="NoPowerDown" />
-    <PowerDownTimeout value="100" />
-</mcconfig>

DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml

@@ -1,20 +0,0 @@
-<mcconfig>
-	<!-- Open, OpenAdaptive, Closed, ClosedAdaptive -->
-	<PagePolicy value="Open" />
-	<!-- Fifo, FrFcfs, FrFcfsGrp -->
-    <Scheduler value="FrFcfs" />
-	<RequestBufferSize value="8" />
-	<!-- Oldest, Strict -->
-	<CmdMux value="Oldest" />
-	<!-- Fifo, Reorder -->
-	<RespQueue value="Fifo" />
-	<!-- NoRefresh, Rankwise, Bankwise -->
-	<RefreshPolicy value="Rankwise" />
-	<!-- 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
-	<RefreshMode value="1" />
-	<RefreshMaxPostponed value="0"/>
-    <RefreshMaxPulledin value="0"/>
-    <!-- NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
-    <PowerDownPolicy value="NoPowerDown" />
-    <PowerDownTimeout value="100" />
-</mcconfig>

DRAMSys/tests/DDR3/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml

@@ -1,55 +0,0 @@
-<!DOCTYPE memspec SYSTEM "memspec.dtd">
-<memspec>
-
-  <parameter id="memoryId" type="string" value="MICRON_1Gb_DDR3-1600_8bit_G" />
-  <parameter id="memoryType" type="string" value="DDR3" />
-  <memarchitecturespec>
-    <parameter id="width" type="uint" value="8" />
-    <parameter id="nbrOfBanks" type="uint" value="8" />
-    <parameter id="nbrOfRanks" type="uint" value="1" />
-    <parameter id="nbrOfColumns" type="uint" value="1024" />
-    <parameter id="nbrOfRows" type="uint" value="16384" />
-    <parameter id="dataRate" type="uint" value="2" />
-    <parameter id="burstLength" type="uint" value="8" />
-  </memarchitecturespec>
-  <memtimingspec>
-      <parameter id="clkMhz" type="double" value="800" />
-      <parameter id="RC" type="uint" value="38" />
-      <parameter id="RCD" type="uint" value="10" />
-      <parameter id="RL" type="uint" value="10" />
-      <parameter id="RP" type="uint" value="10" />
-      <parameter id="RFC" type="uint" value="88" />
-      <parameter id="RAS" type="uint" value="28" />
-      <parameter id="WL" type="uint" value="8" />
-      <parameter id="AL" type="uint" value="0" />
-      <parameter id="DQSCK" type="uint" value="0" />
-      <parameter id="RTP" type="uint" value="6" />
-      <parameter id="WR" type="uint" value="12" />
-      <parameter id="XP" type="uint" value="6" />
-      <parameter id="XPDLL" type="uint" value="20" />
-      <parameter id="XS" type="uint" value="96" />
-      <parameter id="XSDLL" type="uint" value="512" />
-      <parameter id="REFI" type="uint" value="6240" />
-      <parameter id="CL" type="uint" value="10" />
-      <parameter id="FAW" type="uint" value="24" />
-      <parameter id="RRD" type="uint" value="5" />
-      <parameter id="CCD" type="uint" value="4" />
-      <parameter id="WTR" type="uint" value="6" />
-      <parameter id="CKE" type="uint" value="3" />
-      <parameter id="CKESR" type="uint" value="4" />
-  </memtimingspec>
-  <mempowerspec>
-      <parameter id="idd0" type="double" value="70.0" />
-      <parameter id="idd2p0" type="double" value="12.0" />
-      <parameter id="idd2p1" type="double" value="30.0" />
-      <parameter id="idd2n" type="double" value="45.0" />
-      <parameter id="idd3p0" type="double" value="35.0" />
-      <parameter id="idd3p1" type="double" value="35.0" />
-      <parameter id="idd3n" type="double" value="45.0" />
-      <parameter id="idd4w" type="double" value="145.0" />
-      <parameter id="idd4r" type="double" value="140.0" />
-      <parameter id="idd5" type="double" value="170.0" />
-      <parameter id="idd6" type="double" value="8.0" />
-      <parameter id="vdd" type="double" value="1.5" />
-  </mempowerspec>
-</memspec>

DRAMSys/tests/DDR3/configs/simulator/ddr3-protocol_checker.xml

@@ -1,29 +0,0 @@
-<simconfig>
-    <SimulationName value="ddr3" />
-    <Debug value="0" />
-    <DatabaseRecording value="1" />
-    <PowerAnalysis value="1" />
-    <EnableWindowing value = "1" />
-    <WindowSize value="1000" />
-    <ThermalSimulation value="0"/>
-    <SimulationProgressBar value="1"/>
-    <NumberOfMemChannels value="1"/>
-    <NumberOfDevicesOnDIMM value = "8" />
-    <CheckTLM2Protocol value = "1" />
-    <AddressOffset value = "0" />
-    <ECCControllerMode value = "Disabled" />
-    <ErrorChipSeed value="42" />
-    <ErrorCSVFile value="" />
-    <!-- Modes:
-	- NoStorage,
-	- Store (store data without errormodel),
-	- ErrorModel (store data with errormodel)
-    -->
-    <StoreMode value="NoStorage" />
-    <!-- Gem5 Related Configuration:
-    In the memory controller file the storage mode should be set to Store
-    E.g. the DRAM is located at 0x80000000 for gem5
-    <AddressOffset value = "2147483648" />
-    -->
-    <UseMalloc value="0" />
-</simconfig>

DRAMSys/tests/DDR3/configs/simulator/ddr3.xml

@@ -1,29 +0,0 @@
-<simconfig>
-    <SimulationName value="ddr3" />
-    <Debug value="0" />
-    <DatabaseRecording value="1" />
-    <PowerAnalysis value="1" />
-    <EnableWindowing value = "1" />
-    <WindowSize value="1000" />
-    <ThermalSimulation value="0"/>
-    <SimulationProgressBar value="1"/>
-    <NumberOfMemChannels value="1"/>
-    <NumberOfDevicesOnDIMM value = "8" />
-    <CheckTLM2Protocol value = "0" />
-    <AddressOffset value = "0" />
-    <ECCControllerMode value = "Disabled" />
-    <ErrorChipSeed value="42" />
-    <ErrorCSVFile value="" />
-    <!-- Modes:
-	- NoStorage,
-	- Store (store data without errormodel),
-	- ErrorModel (store data with errormodel)
-    -->
-    <StoreMode value="NoStorage" />
-    <!-- Gem5 Related Configuration:
-    In the memory controller file the storage mode should be set to Store
-    E.g. the DRAM is located at 0x80000000 for gem5
-    <AddressOffset value = "2147483648" />
-    -->
-    <UseMalloc value="0" />
-</simconfig>

DRAMSys/tests/DDR3/configs/thermalsim/config.xml

@@ -1,14 +0,0 @@
-<!-- Temperature Simulator Configuration (used for all simulation setups) -->
-<thermalsimconfig>
-    <TemperatureScale value="Celsius" />
-    <StaticTemperatureDefaultValue value="89" />
-    <ThermalSimPeriod value="100" />
-    <ThermalSimUnit value="us" />
-    <PowerInfoFile value="powerInfo.xml"/>
-    <IceServerIp value="127.0.0.1" />
-    <IceServerPort value="11880" />
-    <SimPeriodAdjustFactor value="10" />
-    <NPowStableCyclesToIncreasePeriod value="5" />
-    <GenerateTemperatureMap value="1" />
-    <GeneratePowerMap value="1" />
-</thermalsimconfig>

DRAMSys/tests/DDR3/configs/thermalsim/powerInfo.xml

@@ -1,8 +0,0 @@
-<powerInfo>
-    <!-- Power information must be provided for all floor plan elements -->
-    <dram_die_channel0 init_pow="0" threshold="1.0" />
-    <dram_die_channel1 init_pow="0" threshold="1.0" />
-    <dram_die_channel2 init_pow="0" threshold="1.0" />
-    <dram_die_channel3 init_pow="0" threshold="1.0" />
-</powerInfo>
-

DRAMSys/tests/DDR3/simulations/ddr3-example.xml

@@ -1,25 +0,0 @@
-<simulation>
-    <!-- Simulation file identifier -->
-    <simulationid id="ddr3-example"></simulationid>
-    <!-- Configuration for the DRAMSys Simulator -->
-    <simconfig src="ddr3.xml" />
-    <!-- Temperature Simulator Configuration -->
-    <thermalconfig src="config.xml" />
-    <!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
-    <memspec src="MICRON_1Gb_DDR3-1600_8bit_G.xml"></memspec>
-    <!-- Addressmapping Configuration of the Memory Controller -->
-    <addressmapping src="am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml"></addressmapping>
-    <!-- Memory Controller Configuration: -->
-    <mcconfig src="fifoStrict.xml"/>
-    <!--
-    The following trace setup is only used in standalone mode.
-    In library mode e.g. in Platform Architect the trace setup is ignored.
-    -->
-    <tracesetup>
-        <!--
-        This device mimics an image processing application
-        running on an FPGA with 200 Mhz.
-        -->
-        <device clkMhz="200">ddr3_example.stl</device>
-    </tracesetup>
-</simulation>

DRAMSys/tests/DDR3/simulations/ddr3-fr_fcfs.xml

@@ -1,25 +0,0 @@
-<simulation>
-    <!-- Simulation file identifier -->
-    <simulationid id="ddr3-fr_fcfs"></simulationid>
-    <!-- Configuration for the DRAMSys Simulator -->
-    <simconfig src="ddr3.xml" />
-    <!-- Temperature Simulator Configuration -->
-    <thermalconfig src="config.xml" />
-    <!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
-    <memspec src="MICRON_1Gb_DDR3-1600_8bit_G.xml"></memspec>
-    <!-- Addressmapping Configuration of the Memory Controller -->
-    <addressmapping src="am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml"></addressmapping>
-    <!-- Memory Controller Configuration: -->
-    <mcconfig src="fr_fcfs.xml"/>
-    <!--
-    The following trace setup is only used in standalone mode.
-    In library mode e.g. in Platform Architect the trace setup is ignored.
-    -->
-    <tracesetup>
-        <!--
-        This device mimics an image processing application
-        running on an FPGA with 200 Mhz.
-        -->
-        <device clkMhz="200">ddr3_example.stl</device>
-    </tracesetup>
-</simulation>

DRAMSys/tests/DDR3/simulations/ddr3-protocol_checker.xml

@@ -1,25 +0,0 @@
-<simulation>
-    <!-- Simulation file identifier -->
-    <simulationid id="ddr3-protocol_checker"></simulationid>
-    <!-- Configuration for the DRAMSys Simulator -->
-    <simconfig src="ddr3-protocol_checker.xml" />
-    <!-- Temperature Simulator Configuration -->
-    <thermalconfig src="config.xml" />
-    <!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
-    <memspec src="MICRON_1Gb_DDR3-1600_8bit_G.xml"></memspec>
-    <!-- Addressmapping Configuration of the Memory Controller -->
-    <addressmapping src="am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml"></addressmapping>
-    <!-- Memory Controller Configuration: -->
-    <mcconfig src="fifoStrict.xml"/>
-    <!--
-    The following trace setup is only used in standalone mode.
-    In library mode e.g. in Platform Architect the trace setup is ignored.
-    -->
-    <tracesetup>
-        <!--
-        This device mimics an image processing application
-        running on an FPGA with 200 Mhz.
-        -->
-        <device clkMhz="200">ddr3_example.stl</device>
-    </tracesetup>
-</simulation>

DRAMSys/tests/DDR4/ci.yml

@@ -0,0 +1,29 @@
+# DDR4 with 4 bank groups, flexible rankwise refresh and FrFcfs scheduler:
+example_ddr4:
+    stage: DDR4
+    script:
+        - export GCOV_PREFIX=$(pwd)
+        - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}')
+        - cd build/simulator
+        - ./DRAMSys ../../DRAMSys/tests/DDR4/simulations/ddr4-example.json ../../DRAMSys/tests/DDR4/
+        - ls -lah
+        - ls -lah ../../DRAMSys/tests/DDR4/expected/
+        - sqldiff ../../DRAMSys/tests/DDR4/expected/ddr4-bankgrp_ddr4_ch0.tdb ddr4-bankgrp_ddr4_ch0.tdb
+        - perl -e 'if(`sqldiff ../../DRAMSys/tests/DDR4/expected/ddr4-bankgrp_ddr4_ch0.tdb ddr4-bankgrp_ddr4_ch0.tdb` eq "") {exit(0)} else {exit(-1)}'
+        #- cd ../traceAnalyzer
+        #- python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/ddr4-bankgrp_ddr4_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi
+        # Run Code Coverage
+        - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out
+ 
+    cache:
+        key: build
+        paths:
+            - build/
+        policy: pull
+
+    artifacts:
+        paths:
+          - build/simulator/ddr4-bankgrp_ddr4_ch0.tdb
+          - coverage/${CI_JOB_NAME}.out
+        expire_in: 2 days
+