diff --git a/.gitignore b/.gitignore index 99b20805..118c019c 100644 --- a/.gitignore +++ b/.gitignore @@ -5,6 +5,7 @@ /dram/build *.user *.tdb +!/DRAMSys/tests/*/expected/*.tdb *.tdb-journal *.out /build-simulation diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 9011e4ab..5540c9c6 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -6,9 +6,10 @@ variables: stages: - build - - dramsys-gem5-build - - WIDEIO + - LPDDR4 - DDR3 + - DDR4 + - HBM2 - Coverage build: @@ -19,12 +20,14 @@ build: - rm -rf build - mkdir -p build - cd build + - export COVERAGE=true - cmake ../DRAMSys - - make -j16 + - make -j 16 - find . -name "*.o" -type f -delete - rm -rf ${CI_PROJECT_DIR}/coverage - mkdir -p ${CI_PROJECT_DIR}/coverage - + + cache: key: build paths: @@ -34,7 +37,7 @@ build: artifacts: paths: - coverage/ - + coverage: stage: Coverage coverage: '/Total:\|(\d+\.?\d+\%)/' @@ -42,15 +45,18 @@ coverage: # delete all empty files since they produce errors - find coverage -size 0 -type f -delete - ls coverage/ -lah - - lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final.out - - lcov --list coverage/final.out - + - lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final.out + - lcov --remove coverage/final.out '*/systemc*/include/*' '*/traceAnalyzer/*' '*/gcc*/include/*' '/usr/include/*' '*/third_party/*' -o coverage/final_dramsys.out + - lcov --list coverage/final_dramsys.out + artifacts: paths: - coverage/final.out - + - coverage/final_dramsys.out include: - - '/DRAMSys/tests/DDR3/ci.yml' - - '/DRAMSys/tests/WIDEIO/ci.yml' - #- '/DRAMSys/tests/dramsys-gem5/ci.yml' # Should be activated again when a new gitlab runner with right dependencies is used + - '/DRAMSys/tests/lpddr4/ci.yml' + - '/DRAMSys/tests/ddr3_multirank/ci.yml' + - '/DRAMSys/tests/DDR4/ci.yml' + - '/DRAMSys/tests/HBM2/ci.yml' + #- '/DRAMSys/tests/dramsys-gem5/ci.yml' # Should be activated again when a new gitlab runner with right dependencies is used diff --git a/DRAMSys/CMakeLists.txt b/DRAMSys/CMakeLists.txt index 6a50c48c..ccb2df9f 100644 --- a/DRAMSys/CMakeLists.txt +++ b/DRAMSys/CMakeLists.txt @@ -38,6 +38,13 @@ project(DRAMSys) # Configuration: set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version") set(DCMAKE_SH "CMAKE_SH-NOTFOUND" CACHE STRING "Ignore sh.exe error on Windows") +if(DEFINED ENV{COVERAGE}) + set(GCC_COVERAGE_COMPILE_FLAGS "-g -O0 -coverage -fprofile-arcs -ftest-coverage") + set(GCC_COVERAGE_LINK_FLAGS "-coverage -lgcov") + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}") + set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${GCC_COVERAGE_LINK_FLAGS}") + message("-- Coverage check enabled") +endif() # Add DRAMSysLibrary: add_subdirectory(library) @@ -54,3 +61,4 @@ add_subdirectory(simulator) if(DEFINED ENV{GEM5}) add_subdirectory(gem5) endif() + diff --git a/DRAMSys/library/CMakeLists.txt b/DRAMSys/library/CMakeLists.txt index 0b828857..a84e0f29 100644 --- a/DRAMSys/library/CMakeLists.txt +++ b/DRAMSys/library/CMakeLists.txt @@ -38,6 +38,12 @@ project(DRAMSysLibrary) # Configuration: set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version") set(DCMAKE_SH="CMAKE_SH-NOTFOUND") +if(DEFINED ENV{COVERAGE}) + set(GCC_COVERAGE_COMPILE_FLAGS "-g -O0 -coverage -fprofile-arcs -ftest-coverage") + set(GCC_COVERAGE_LINK_FLAGS "-coverage -lgcov") + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}") + set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${GCC_COVERAGE_LINK_FLAGS}") +endif() # Add DRAMPower: add_subdirectory(src/common/third_party/DRAMPower) @@ -172,6 +178,7 @@ add_library(DRAMSysLibrary resources/simulations/lpddr4-example.json resources/simulations/ranktest.json resources/simulations/wideio-example.json + resources/simulations/wideio-thermal.json # Address Mapping Config Files resources/configs/amconfigs/am_ddr3_1Gbx8_p1KB_brc.json @@ -266,9 +273,11 @@ add_library(DRAMSysLibrary resources/configs/simulator/hbm2.json resources/configs/simulator/lpddr4.json resources/configs/simulator/wideio.json + resources/configs/simulator/wideio_thermal.json # Thermal Simulation Config Files resources/configs/thermalsim/config.json + resources/configs/thermalsim/powerInfo.json # Trace Files resources/traces/test_ecc.stl diff --git a/DRAMSys/library/resources/configs/memspecs/HBM2.json b/DRAMSys/library/resources/configs/memspecs/HBM2.json index efa8ee9e..0f60243d 100644 --- a/DRAMSys/library/resources/configs/memspecs/HBM2.json +++ b/DRAMSys/library/resources/configs/memspecs/HBM2.json @@ -8,7 +8,8 @@ "nbrOfColumns": 128, "nbrOfRanks": 2, "nbrOfRows": 32768, - "width": 64 + "width": 64, + "nbrOfChannels": 1 }, "memoryId": "https://www.computerbase.de/2019-05/amd-memory-tweak-vram-oc/#bilder", "memoryType": "HBM2", @@ -43,4 +44,4 @@ "clkMhz": 1000 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json index 64256e3c..114a76fb 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json @@ -7,7 +7,8 @@ "nbrOfColumns": 128, "nbrOfRanks": 1, "nbrOfRows": 4096, - "width": 128 + "width": 128, + "nbrOfChannels": 4 }, "memoryId": "JEDEC_256Mb_WIDEIO_SDR-200_128bit", "memoryType": "WIDEIO_SDR", @@ -62,4 +63,4 @@ "clkMhz": 200 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json index c2d60cd9..8ef5ffe8 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json @@ -7,7 +7,8 @@ "nbrOfColumns": 128, "nbrOfRanks": 1, "nbrOfRows": 4096, - "width": 128 + "width": 128, + "nbrOfChannels": 4 }, "memoryId": "JEDEC_256Mb_WIDEIO_SDR-266_128bit", "memoryType": "WIDEIO_SDR", @@ -62,4 +63,4 @@ "clkMhz": 266 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json index c7c0e7a0..8343c6f8 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json @@ -8,7 +8,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A", "memoryType": "DDR4", @@ -65,4 +67,4 @@ "clkMhz": 933 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json index 51ac9635..1e16ea82 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json @@ -8,7 +8,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_4Gb_DDR4-2400_8bit_A", "memoryType": "DDR4", @@ -65,4 +67,4 @@ "clkMhz": 1200 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json index 65be78a0..04886e6b 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json @@ -7,7 +7,8 @@ "nbrOfColumns": 512, "nbrOfRanks": 1, "nbrOfRows": 8192, - "width": 64 + "width": 64, + "nbrOfChannels": 4 }, "memoryId": "JEDEC_4x64_2Gb_WIDEIO2-400_64bit", "memoryType": "WIDEIO2", @@ -39,4 +40,4 @@ "clkMhz": 400 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json index a01fedb0..fc6aab68 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json @@ -7,7 +7,8 @@ "nbrOfColumns": 512, "nbrOfRanks": 1, "nbrOfRows": 8192, - "width": 64 + "width": 64, + "nbrOfChannels": 4 }, "memoryId": "JEDEC_4x64_2Gb_WIDEIO2-533_64bit", "memoryType": "WIDEIO2", @@ -39,4 +40,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json index c41d427f..03008970 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json @@ -7,7 +7,8 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 65536, - "width": 16 + "width": 16, + "nbrOfChannels": 1 }, "memoryId": "JEDEC_8Gb_LPDDR4-3200_16bit", "memoryType": "LPDDR4", @@ -93,4 +94,4 @@ "clkMhz": 1600 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json index aaecf874..0554838d 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 8192, - "width": 16 + "width": 16, + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR2-1066_16bit_H", "memoryType": "DDR2", @@ -52,4 +54,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json index 33f80da5..d54ddb75 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 8192, - "width": 16 + "width": 16, + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR2-800_16bit_H", "memoryType": "DDR2", @@ -52,4 +54,4 @@ "clkMhz": 400 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json index 467c599b..06f79649 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 8192, - "width": 16 + "width": 16, + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json index 6ff10023..dfd064bf 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 8192, - "width": 16 + "width": 16, + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G_2s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json index 9b4a0ad8..8a40d4d0 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 8192, - "width": 16 + "width": 16, + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G_3s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json index 9459ab49..989c7697 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 8192, - "width": 16 + "width": 16, + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G_mu", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json index 5dd17ce0..5a96131d 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json index 8f7e730b..4ef0bc5b 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G_2s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json index 315c3fce..c28ed4b3 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G_3s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json index ae39db63..16d6d572 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G_mu", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json index 3020b53b..9d4d682c 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json index 6867118b..379cd55d 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G_2s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json index 2988bf90..e3a00e86 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G_3s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json index c6dabf1d..fd672487 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json index 9aaa2c4c..061219e6 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G_mu", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json index 0aef9bf9..ceace84b 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-800_8bit_G", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 400 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json index b8cd6ba9..947f6aa4 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 2, "nbrOfRows": 16384, - "width": 64 + "width": 64, + "nbrOfDevicesOnDIMM": 1, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json index d19953e5..4a249d45 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 2, "nbrOfRows": 16384, - "width": 64 + "width": 64, + "nbrOfDevicesOnDIMM": 1, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2GB_DDR3-1066_64bit_G_UDIMM", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json index 2b954795..c9927028 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 2, "nbrOfRows": 16384, - "width": 64 + "width": 64, + "nbrOfDevicesOnDIMM": 1, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2GB_DDR3-1333_64bit_D_SODIMM", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 666 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json index ef9a59b8..cfca2ccd 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 2, "nbrOfRows": 16384, - "width": 64 + "width": 64, + "nbrOfDevicesOnDIMM": 1, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2GB_DDR3-1600_64bit_G_UDIMM", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json index f135a2e6..bb451167 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json index 0cd99819..7ac094bc 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D_2s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json index 647e8938..f16c8d27 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D_3s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json index 1273f6e2..e962654a 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D_mu", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json index a6a5a43a..d404eba9 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 16 + "width": 16, + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json index 768b1cae..949cd56e 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 16 + "width": 16, + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D_2s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json index a5b3a676..2da4909c 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 16 + "width": 16, + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D_3s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json index a6b86516..dfc21103 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 16 + "width": 16, + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D_mu", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json index a75ff24b..f7c989f9 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json @@ -7,7 +7,8 @@ "nbrOfColumns": 2048, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 16 + "width": 16, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_LPDDR-266_16bit_A", "memoryType": "LPDDR", @@ -51,4 +52,4 @@ "clkMhz": 133 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json index 8b17dc3f..2e271810 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json @@ -7,7 +7,8 @@ "nbrOfColumns": 2048, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 16 + "width": 16, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_LPDDR-333_16bit_A", "memoryType": "LPDDR", @@ -51,4 +52,4 @@ "clkMhz": 166 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json index 8aadde0a..638afb58 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json @@ -7,7 +7,8 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 16 + "width": 16, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_LPDDR2-1066-S4_16bit_A", "memoryType": "LPDDR2", @@ -64,4 +65,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json index ebe11f7a..fa1a357c 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json @@ -7,7 +7,8 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 16 + "width": 16, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_LPDDR2-800-S4_16bit_A", "memoryType": "LPDDR2", @@ -64,4 +65,4 @@ "clkMhz": 400 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json index 11700aaf..7afe6d81 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json @@ -8,7 +8,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A", "memoryType": "DDR4", @@ -63,4 +65,4 @@ "clkMhz": 933 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json index ed4906cd..0406d803 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json @@ -8,7 +8,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_4Gb_DDR4-2400_8bit_A", "memoryType": "DDR4", @@ -63,4 +65,4 @@ "clkMhz": 1200 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json index 35e1fe35..9bee9f8b 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json @@ -7,7 +7,8 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 32 + "width": 32, + "nbrOfChannels": 1 }, "memoryId": "MICRON_4Gb_LPDDR3-1333_32bit_A", "memoryType": "LPDDR3", @@ -64,4 +65,4 @@ "clkMhz": 667 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json index 60d40c43..87f5047e 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json @@ -7,7 +7,8 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 32 + "width": 32, + "nbrOfChannels": 1 }, "memoryId": "MICRON_4Gb_LPDDR3-1600_32bit_A", "memoryType": "LPDDR3", @@ -64,4 +65,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json index 17638bb1..1d61ae45 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json @@ -7,7 +7,8 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 49152, - "width": 16 + "width": 16, + "nbrOfChannels": 1 }, "memoryId": "MICRON_6Gb_LPDDR3-3200_16bit_A", "memoryType": "LPDDR4", @@ -92,4 +93,4 @@ "clkMhz": 1600 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json b/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json index 41f5cef2..2706f93d 100644 --- a/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json +++ b/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 8192, - "width": 16 + "width": 16, + "nbrOfChannels": 1, + "nbrOfDevicesOnDIMM": 1, }, "memoryId": "SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json b/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json index ca86b2d5..a58d953a 100644 --- a/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json +++ b/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 16 + "width": 16, + "nbrOfDevicesOnDIMM": 1, + "nbrOfChannels": 1 }, "memoryId": "SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.json b/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.json index 88044fdd..3faa3399 100644 --- a/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.json +++ b/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.json @@ -7,7 +7,8 @@ "nbrOfColumns": 1024, "nbrOfRanks": 4, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G", "memoryType": "DDR3", @@ -56,4 +57,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/ddr3-single-device.json b/DRAMSys/library/resources/configs/simulator/ddr3-single-device.json index a1621422..de1a1bec 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr3-single-device.json +++ b/DRAMSys/library/resources/configs/simulator/ddr3-single-device.json @@ -8,8 +8,6 @@ "EnableWindowing": true, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1, "PowerAnalysis": true, "SimulationName": "ddr3_single_dev", "SimulationProgressBar": true, @@ -18,4 +16,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/ddr3.json b/DRAMSys/library/resources/configs/simulator/ddr3.json index 4e9faadc..99ccdb45 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr3.json +++ b/DRAMSys/library/resources/configs/simulator/ddr3.json @@ -8,8 +8,6 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, "PowerAnalysis": false, "SimulationName": "ddr3", "SimulationProgressBar": true, diff --git a/DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.json b/DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.json index fd35bdee..d885c677 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.json +++ b/DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.json @@ -8,8 +8,6 @@ "EnableWindowing": true, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, "PowerAnalysis": true, "SimulationName": "ddr3", "SimulationProgressBar": true, @@ -18,4 +16,4 @@ "UseMalloc": true, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/ddr3_ecc.json b/DRAMSys/library/resources/configs/simulator/ddr3_ecc.json index 2b813f99..e148c3aa 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr3_ecc.json +++ b/DRAMSys/library/resources/configs/simulator/ddr3_ecc.json @@ -8,8 +8,6 @@ "EnableWindowing": true, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, "PowerAnalysis": true, "SimulationName": "ddr3", "SimulationProgressBar": true, @@ -18,4 +16,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.json b/DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.json index 72ebcf9b..c0b12f97 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.json +++ b/DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.json @@ -8,8 +8,6 @@ "EnableWindowing": true, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, "PowerAnalysis": true, "SimulationName": "ddr3", "SimulationProgressBar": true, @@ -18,4 +16,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/ddr4.json b/DRAMSys/library/resources/configs/simulator/ddr4.json index 8e62e680..05cd86e2 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr4.json +++ b/DRAMSys/library/resources/configs/simulator/ddr4.json @@ -8,8 +8,6 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, "PowerAnalysis": false, "SimulationName": "ddr4", "SimulationProgressBar": true, @@ -18,4 +16,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/hbm2.json b/DRAMSys/library/resources/configs/simulator/hbm2.json index 9589611f..608aec41 100644 --- a/DRAMSys/library/resources/configs/simulator/hbm2.json +++ b/DRAMSys/library/resources/configs/simulator/hbm2.json @@ -8,8 +8,6 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1, "PowerAnalysis": false, "SimulationName": "hbm2", "SimulationProgressBar": true, @@ -18,4 +16,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/lpddr4.json b/DRAMSys/library/resources/configs/simulator/lpddr4.json index fd8fe855..ee38bd66 100644 --- a/DRAMSys/library/resources/configs/simulator/lpddr4.json +++ b/DRAMSys/library/resources/configs/simulator/lpddr4.json @@ -8,7 +8,6 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, "NumberOfMemChannels": 1, "PowerAnalysis": false, "SimulationName": "lpddr4", @@ -18,4 +17,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/wideio.json b/DRAMSys/library/resources/configs/simulator/wideio.json index 4a0bd0ee..0c285f79 100644 --- a/DRAMSys/library/resources/configs/simulator/wideio.json +++ b/DRAMSys/library/resources/configs/simulator/wideio.json @@ -7,8 +7,6 @@ "EnableWindowing": true, "ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 4, "PowerAnalysis": true, "SimulationName": "wideio", "SimulationProgressBar": true, @@ -17,4 +15,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/wideio_ecc.json b/DRAMSys/library/resources/configs/simulator/wideio_ecc.json index 216d3623..80acc3be 100644 --- a/DRAMSys/library/resources/configs/simulator/wideio_ecc.json +++ b/DRAMSys/library/resources/configs/simulator/wideio_ecc.json @@ -7,8 +7,6 @@ "EnableWindowing": true, "ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1, "PowerAnalysis": true, "SimulationName": "wideio_ecc", "SimulationProgressBar": true, @@ -17,4 +15,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/wideio_thermal.json b/DRAMSys/library/resources/configs/simulator/wideio_thermal.json index 6a47ff5b..b37cda4f 100644 --- a/DRAMSys/library/resources/configs/simulator/wideio_thermal.json +++ b/DRAMSys/library/resources/configs/simulator/wideio_thermal.json @@ -7,8 +7,6 @@ "EnableWindowing": true, "ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 4, "PowerAnalysis": true, "SimulationName": "wideio", "SimulationProgressBar": true, @@ -17,4 +15,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/src/common/AddressDecoder.cpp b/DRAMSys/library/src/common/AddressDecoder.cpp index b454cec6..33e920c9 100644 --- a/DRAMSys/library/src/common/AddressDecoder.cpp +++ b/DRAMSys/library/src/common/AddressDecoder.cpp @@ -143,10 +143,10 @@ AddressDecoder::AddressDecoder(std::string pathToAddressMapping) Configuration &config = Configuration::getInstance(); MemSpec *memSpec = config.memSpec; - if (config.numberOfMemChannels != channels || memSpec->numberOfRanks != ranks + if (memSpec->numberOfChannels != channels || memSpec->numberOfRanks != ranks || memSpec->numberOfBankGroups != bankgroups || memSpec->numberOfBanks != banks || memSpec->numberOfRows != rows || memSpec->numberOfColumns != columns - || config.numberOfDevicesOnDIMM * memSpec->bitWidth != bytes * 8) + || memSpec->numberOfDevicesOnDIMM * memSpec->bitWidth != bytes * 8) SC_REPORT_FATAL("AddressDecoder", "Memspec and address mapping do not match"); } diff --git a/DRAMSys/library/src/configuration/Configuration.cpp b/DRAMSys/library/src/configuration/Configuration.cpp index 3f8462ba..921c8c5c 100644 --- a/DRAMSys/library/src/configuration/Configuration.cpp +++ b/DRAMSys/library/src/configuration/Configuration.cpp @@ -121,20 +121,10 @@ void Configuration::setParameter(std::string name, nlohmann::json value) } else if (name == "Debug") debug = value; - else if (name == "NumberOfMemChannels") - numberOfMemChannels = value; else if (name == "ThermalSimulation") thermalSimulation = value; else if (name == "SimulationProgressBar") simulationProgressBar = value; - else if (name == "NumberOfDevicesOnDIMM") - { - numberOfDevicesOnDIMM = value; - if (numberOfDevicesOnDIMM == 0) - SC_REPORT_FATAL("Configuration", - ("Invalid value for parameter " + name + - ". This parameter must be at least one.").c_str()); - } else if (name == "AddressOffset") { #ifdef DRAMSYS_GEM5 @@ -209,12 +199,13 @@ std::uint64_t Configuration::getSimMemSizeInBytes() std::uint64_t rows = memSpec->numberOfRows; std::uint64_t columns = memSpec->numberOfColumns; std::uint64_t bitWidth = memSpec->bitWidth; + std::uint64_t devicesOnDIMM = memSpec->numberOfDevicesOnDIMM; // 2. Calculate size of one DRAM chip in bits std::uint64_t chipBitSize = banks * rows * columns * bitWidth; // 3. Calculate size of one DRAM chip in bytes std::uint64_t chipSize = chipBitSize / 8; // 4. Total memory size in Bytes of one DIMM (with only support of 1 rank on a DIMM) - std::uint64_t memorySize = chipSize * numberOfDevicesOnDIMM; + std::uint64_t memorySize = chipSize * memSpec->numberOfDevicesOnDIMM; std::cout << headline << std::endl; std::cout << "Per Channel Configuration:" << std::endl << std::endl; @@ -228,7 +219,7 @@ std::uint64_t Configuration::getSimMemSizeInBytes() std::cout << " Chip data bus width: " << bitWidth << std::endl; std::cout << " Chip size in bits: " << chipBitSize << std::endl; std::cout << " Chip Size in bytes: " << chipSize << std::endl; - std::cout << " Devices/Chips on DIMM: " << numberOfDevicesOnDIMM << std::endl; + std::cout << " Devices/Chips on DIMM: " << devicesOnDIMM << std::endl; std::cout << std::endl; assert(memorySize > 0); @@ -241,7 +232,7 @@ std::uint64_t Configuration::getSimMemSizeInBytes() // The bus width is given in bits, e.g., 64-bit data bus, 128-bit data bus, etc. unsigned int Configuration::getDataBusWidth() { - return memSpec->bitWidth * numberOfDevicesOnDIMM; + return memSpec->bitWidth * memSpec->numberOfDevicesOnDIMM; } // Returns the number of bytes transfered in a burst diff --git a/DRAMSys/library/src/configuration/Configuration.h b/DRAMSys/library/src/configuration/Configuration.h index af0ffff9..0f850baa 100644 --- a/DRAMSys/library/src/configuration/Configuration.h +++ b/DRAMSys/library/src/configuration/Configuration.h @@ -88,10 +88,8 @@ public: bool enableWindowing = false; unsigned int windowSize = 1000; bool debug = false; - unsigned int numberOfMemChannels = 1; bool thermalSimulation = false; bool simulationProgressBar = false; - unsigned int numberOfDevicesOnDIMM = 8; bool checkTLM2Protocol = false; std::string ECCMode = "Disabled"; ECCBaseClass *pECC = nullptr; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp index 3022440c..4cae3c73 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp @@ -43,15 +43,19 @@ using namespace tlm; using json = nlohmann::json; -MemSpec::MemSpec(json &memspec, unsigned numberOfRanks, unsigned banksPerRank, +MemSpec::MemSpec(json &memspec, unsigned numberOfChannels, + unsigned numberOfRanks, unsigned banksPerRank, unsigned groupsPerRank, unsigned banksPerGroup, - unsigned numberOfBanks, unsigned numberOfBankGroups) - : numberOfRanks(numberOfRanks), + unsigned numberOfBanks, unsigned numberOfBankGroups, + unsigned numberOfDevicesOnDIMM) + : numberOfChannels(numberOfChannels), + numberOfRanks(numberOfRanks), banksPerRank(banksPerRank), groupsPerRank(groupsPerRank), banksPerGroup(banksPerGroup), numberOfBanks(numberOfBanks), numberOfBankGroups(numberOfBankGroups), + numberOfDevicesOnDIMM(numberOfDevicesOnDIMM), numberOfRows(parseUint(memspec["memarchitecturespec"]["nbrOfRows"],"nbrOfRows")), numberOfColumns(parseUint(memspec["memarchitecturespec"]["nbrOfColumns"],"nbrOfColumns")), burstLength(parseUint(memspec["memarchitecturespec"]["burstLength"],"burstLength")), @@ -59,9 +63,9 @@ MemSpec::MemSpec(json &memspec, unsigned numberOfRanks, unsigned banksPerRank, bitWidth(parseUint(memspec["memarchitecturespec"]["width"],"width")), fCKMHz(parseUdouble(memspec["memtimingspec"]["clkMhz"], "clkMhz")), tCK(sc_time(1.0 / fCKMHz, SC_US)), - burstDuration(tCK * (burstLength / dataRate)), memoryId(parseString(memspec["memoryId"], "memoryId")), - memoryType(parseString(memspec["memoryType"], "memoryType")) + memoryType(parseString(memspec["memoryType"], "memoryType")), + burstDuration(tCK * (burstLength / dataRate)) { commandLengthInCycles = std::vector(numberOfCommands(), 1); } diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h index 37185107..785e52d7 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -48,12 +48,14 @@ class MemSpec { public: + unsigned numberOfChannels; unsigned numberOfRanks; unsigned banksPerRank; unsigned groupsPerRank; unsigned banksPerGroup; unsigned numberOfBanks; unsigned numberOfBankGroups; + unsigned numberOfDevicesOnDIMM; unsigned numberOfRows; unsigned numberOfColumns; unsigned burstLength; @@ -78,9 +80,11 @@ public: sc_time getCommandLength(Command) const; protected: - MemSpec(nlohmann::json &memspec, unsigned numberOfRanks, unsigned banksPerRank, + MemSpec(nlohmann::json &memspec, unsigned numberOfChannels, + unsigned numberOfRanks, unsigned banksPerRank, unsigned groupsPerRank, unsigned banksPerGroup, - unsigned numberOfBanks, unsigned numberOfBankGroups); + unsigned numberOfBanks, unsigned numberOfBankGroups, + unsigned numberOfDevicesOnDIMM); // Command lengths in cycles on bus, usually one clock cycle std::vector commandLengthInCycles; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp index 387ec6be..52fed95d 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp @@ -40,13 +40,15 @@ using json = nlohmann::json; MemSpecDDR3::MemSpecDDR3(json &memspec) : MemSpec(memspec, + parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"), parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), 1, parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), + parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), + parseUint(memspec["memarchitecturespec"]["nbrOfDevicesOnDIMM"],"nbrOfDevicesOnDIMM")), tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")), tPD (tCKE), tCKESR (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp index 5078ca0e..9e38241e 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp @@ -41,6 +41,7 @@ using json = nlohmann::json; MemSpecDDR4::MemSpecDDR4(json &memspec) : MemSpec(memspec, + parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"), parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"), @@ -49,7 +50,8 @@ MemSpecDDR4::MemSpecDDR4(json &memspec) parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), + * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), + parseUint(memspec["memarchitecturespec"]["nbrOfDevicesOnDIMM"],"nbrOfDevicesOnDIMM")), tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")), tPD (tCKE), tCKESR (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp index 66bd7f7c..0572099a 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp @@ -40,6 +40,7 @@ using json = nlohmann::json; MemSpecGDDR5::MemSpecGDDR5(json &memspec) : MemSpec(memspec, + parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"), parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"), @@ -48,7 +49,8 @@ MemSpecGDDR5::MemSpecGDDR5(json &memspec) parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), + * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), + 1), tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")), tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")), tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp index a2897967..90908bd9 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp @@ -40,6 +40,7 @@ using json = nlohmann::json; MemSpecGDDR5X::MemSpecGDDR5X(json &memspec) : MemSpec(memspec, + parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"), parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"), @@ -48,7 +49,8 @@ MemSpecGDDR5X::MemSpecGDDR5X(json &memspec) parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), + * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), + 1), tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")), tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")), tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp index 636a3351..b9a70d10 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp @@ -40,6 +40,7 @@ using json = nlohmann::json; MemSpecGDDR6::MemSpecGDDR6(json &memspec) : MemSpec(memspec, + parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"), parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"), @@ -48,7 +49,8 @@ MemSpecGDDR6::MemSpecGDDR6(json &memspec) parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), + * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), + 1), tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")), tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")), tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp index c8afaa93..da1d77b1 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp @@ -40,6 +40,7 @@ using json = nlohmann::json; MemSpecHBM2::MemSpecHBM2(json &memspec) : MemSpec(memspec, + parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"), parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"), @@ -48,7 +49,8 @@ MemSpecHBM2::MemSpecHBM2(json &memspec) parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), + * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), + 1), tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")), tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")), tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp index c16f9b50..6716744f 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp @@ -40,13 +40,15 @@ using json = nlohmann::json; MemSpecLPDDR4::MemSpecLPDDR4(json &memspec) : MemSpec(memspec, + parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"), parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), 1, parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), + parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), + 1), tREFI (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")), tREFIpb (tCK * parseUint(memspec["memtimingspec"]["REFIPB"], "REFIPB")), tRFCab (tCK * parseUint(memspec["memtimingspec"]["RFCAB"], "RFCAB")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp index ecbcb202..e4ccfadb 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp @@ -40,13 +40,15 @@ using json = nlohmann::json; MemSpecWideIO::MemSpecWideIO(json &memspec) : MemSpec(memspec, + parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"), parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), 1, parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), + parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), + 1), tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")), tCKESR (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")), tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp index 91e27078..2f07fdcd 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp @@ -40,13 +40,15 @@ using json = nlohmann::json; MemSpecWideIO2::MemSpecWideIO2(json &memspec) : MemSpec(memspec, + parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"), parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), 1, parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), + parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), + 1), tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")), tDQSS (tCK * parseUint(memspec["memtimingspec"]["DQSS"], "DQSS")), tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")), diff --git a/DRAMSys/library/src/controller/ControllerIF.h b/DRAMSys/library/src/controller/ControllerIF.h index fbcf969f..965697c2 100644 --- a/DRAMSys/library/src/controller/ControllerIF.h +++ b/DRAMSys/library/src/controller/ControllerIF.h @@ -35,7 +35,7 @@ public: // BusWidth e.g. 8 or 64 * Configuration::getInstance().memSpec->bitWidth // Number of devices on a DIMM e.g. 8 - * Configuration::getInstance().numberOfDevicesOnDIMM ) / ( 1024 ); + * Configuration::getInstance().memSpec->numberOfDevicesOnDIMM ) / ( 1024 ); std::cout << name() << std::string(" Total Time: ") << sc_time_stamp().to_string() diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp index 09adc6d1..98e304fc 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp @@ -164,7 +164,7 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, Bank } else if (command == Command::ACT) { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][rank.ID()]; + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCpb); diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp index 349bef14..84429e4c 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp @@ -91,14 +91,17 @@ sc_time RefreshManagerBankwise::start() bool forcedRefresh = (flexibilityCounter == maxPostponed); bool allBanksBusy = true; - for (auto it = remainingBankMachines.begin(); it != remainingBankMachines.end(); it++) + if (!skipSelection) { - if ((*it)->isIdle()) + for (auto it = remainingBankMachines.begin(); it != remainingBankMachines.end(); it++) { - currentIterator = it; - currentBankMachine = *it; - allBanksBusy = false; - break; + if ((*it)->isIdle()) + { + currentIterator = it; + currentBankMachine = *it; + allBanksBusy = false; + break; + } } } @@ -113,7 +116,16 @@ sc_time RefreshManagerBankwise::start() if (currentBankMachine->getState() == BmState::Activated) nextCommand = Command::PRE; else + { nextCommand = Command::REFB; + + if (forcedRefresh) + { + currentBankMachine->block(); + skipSelection = true; + } + } + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, currentBankMachine->getBankGroup(), currentBankMachine->getBank()); return timeToSchedule; @@ -161,6 +173,7 @@ void RefreshManagerBankwise::updateState(Command command, tlm_generic_payload *p switch (command) { case Command::REFB: + skipSelection = false; remainingBankMachines.erase(currentIterator); if (remainingBankMachines.empty()) remainingBankMachines = allBankMachines; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h index 285329b5..252a4b9e 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h @@ -74,6 +74,7 @@ private: int maxPulledin = 0; bool sleeping = false; + bool skipSelection = false; }; #endif // REFRESHMANAGERBANKWISE_H diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp index 098c6013..6a74396d 100644 --- a/DRAMSys/library/src/simulation/Arbiter.cpp +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -49,7 +49,7 @@ Arbiter::Arbiter(sc_module_name name, std::string pathToAddressMapping) : // Anytime an transaction comes from a memory unity to the arbiter the "bw" callback is called. iSocket.register_nb_transport_bw(this, &Arbiter::nb_transport_bw); - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; ++i) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; ++i) { channelIsFree.push_back(true); pendingRequests.push_back(std::queue()); @@ -130,7 +130,7 @@ void Arbiter::peqCallback(tlm_generic_payload &payload, const tlm_phase &phase) // Check the valid range of thread ID and channel Id // TODO: thread ID not checked - assert(channelId < Configuration::getInstance().numberOfMemChannels); + assert(channelId < Configuration::getInstance().memSpec->numberOfChannels); // Phases initiated by the intiator side from arbiter's point of view (devices performing memory requests to the arbiter) if (phase == BEGIN_REQ) diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index b210438d..5991560b 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -192,7 +192,7 @@ void DRAMSys::instantiateModules(const std::string &pathToResources, // Create controllers and DRAMs std::string memoryType = Configuration::getInstance().memSpec->memoryType; - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++) { std::string str = "controller" + std::to_string(i); @@ -251,7 +251,7 @@ void DRAMSys::bindSockets() if (Configuration::getInstance().checkTLM2Protocol) { - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++) { arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket); controllersTlmCheckers[i]->initiator_socket.bind(controllers[i]->tSocket); @@ -260,7 +260,7 @@ void DRAMSys::bindSockets() } else { - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++) { arbiter->iSocket.bind(controllers[i]->tSocket); controllers[i]->iSocket.bind(drams[i]->tSocket); diff --git a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp index 60e4dbd9..c799d8c1 100644 --- a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp +++ b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp @@ -91,7 +91,7 @@ void DRAMSysRecordable::setupTlmRecorders(const std::string &traceName, const std::string &pathToResources) { // Create TLM Recorders, one per channel. - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++) { std::string sqlScriptURI = pathToResources + std::string("scripts/createTraceDB.sql"); @@ -140,7 +140,7 @@ void DRAMSysRecordable::instantiateModules(const std::string &traceName, // Create controllers and DRAMs std::string memoryType = Configuration::getInstance().memSpec->memoryType; - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++) { std::string str = "controller" + std::to_string(i); @@ -199,7 +199,7 @@ void DRAMSysRecordable::bindSockets() if (Configuration::getInstance().checkTLM2Protocol) { - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++) { arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket); controllersTlmCheckers[i]->initiator_socket.bind(controllers[i]->tSocket); @@ -208,7 +208,7 @@ void DRAMSysRecordable::bindSockets() } else { - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++) { arbiter->iSocket.bind(controllers[i]->tSocket); controllers[i]->iSocket.bind(drams[i]->tSocket); diff --git a/DRAMSys/library/src/simulation/dram/Dram.cpp b/DRAMSys/library/src/simulation/dram/Dram.cpp index 16a76f98..845cbfbe 100644 --- a/DRAMSys/library/src/simulation/dram/Dram.cpp +++ b/DRAMSys/library/src/simulation/dram/Dram.cpp @@ -129,14 +129,14 @@ void Dram::reportPower() std::cout << name() << std::string(" Total Energy: ") << std::fixed << std::setprecision( 2 ) << DRAMPower->getEnergy().total_energy - * Configuration::getInstance().numberOfDevicesOnDIMM + * Configuration::getInstance().memSpec->numberOfDevicesOnDIMM << std::string(" pJ") << std::endl; std::cout << name() << std::string(" Average Power: ") << std::fixed << std::setprecision( 2 ) << DRAMPower->getPower().average_power - * Configuration::getInstance().numberOfDevicesOnDIMM + * Configuration::getInstance().memSpec->numberOfDevicesOnDIMM << std::string(" mW") << std::endl; } } diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp index c2319ddb..96f2ddc2 100644 --- a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp @@ -67,7 +67,7 @@ void DramRecordable::reportPower() BaseDram::reportPower(); tlmRecorder->recordPower(sc_time_stamp().to_seconds(), this->DRAMPower->getPower().window_average_power - * Configuration::getInstance().numberOfDevicesOnDIMM); + * Configuration::getInstance().memSpec->numberOfDevicesOnDIMM); } template @@ -132,15 +132,15 @@ void DramRecordable::powerWindow() // Store the time (in seconds) and the current average power (in mW) into the database tlmRecorder->recordPower(sc_time_stamp().to_seconds(), this->DRAMPower->getPower().window_average_power - * Configuration::getInstance().numberOfDevicesOnDIMM); + * Configuration::getInstance().memSpec->numberOfDevicesOnDIMM); // Here considering that DRAMPower provides the energy in pJ and the power in mW PRINTDEBUGMESSAGE(this->name(), std::string("\tWindow Energy: \t") + std::to_string( this->DRAMPower->getEnergy().window_energy * - Configuration::getInstance().numberOfDevicesOnDIMM) + std::string("\t[pJ]")); + Configuration::getInstance().memSpec->numberOfDevicesOnDIMM) + std::string("\t[pJ]")); PRINTDEBUGMESSAGE(this->name(), std::string("\tWindow Average Power: \t") + std::to_string( this->DRAMPower->getPower().window_average_power * - Configuration::getInstance().numberOfDevicesOnDIMM) + std::string("\t[mW]")); + Configuration::getInstance().memSpec->numberOfDevicesOnDIMM) + std::string("\t[mW]")); } while (true); } diff --git a/DRAMSys/simulator/CMakeLists.txt b/DRAMSys/simulator/CMakeLists.txt index 23c68f3a..3018a14f 100644 --- a/DRAMSys/simulator/CMakeLists.txt +++ b/DRAMSys/simulator/CMakeLists.txt @@ -38,6 +38,12 @@ project(DRAMSysSimulator) # Configuration: set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version") set(DCMAKE_SH="CMAKE_SH-NOTFOUND") +if(DEFINED ENV{COVERAGE}) + set(GCC_COVERAGE_COMPILE_FLAGS "-g -O0 -coverage -fprofile-arcs -ftest-coverage") + set(GCC_COVERAGE_LINK_FLAGS "-coverage -lgcov") + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}") + set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${GCC_COVERAGE_LINK_FLAGS}") +endif() if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/../library/src/simulation/DRAMSysRecordable.cpp) add_definitions(-DRECORDING) diff --git a/DRAMSys/tests/DDR3/ci.yml b/DRAMSys/tests/DDR3/ci.yml deleted file mode 100644 index a5afa603..00000000 --- a/DRAMSys/tests/DDR3/ci.yml +++ /dev/null @@ -1,83 +0,0 @@ -# Standard DDR3 Test: -example_ddr3: - stage: DDR3 - script: - - export GCOV_PREFIX=$(pwd) - - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') - - cd build/simulator - - ./DRAMSys ../../DRAMSys/tests/DDR3/simulations/ddr3-example.xml ../../DRAMSys/tests/DDR3/ - - ls -lah - - ls -lah ../../DRAMSys/tests/DDR3/expected/ - - sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-example_ddr3_ch0.tdb ddr3-example_ddr3_ch0.tdb - - perl -e 'if(`sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-example_ddr3_ch0.tdb ddr3-example_ddr3_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' - - cd ../traceAnalyzer - - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/ddr3-example_ddr3_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi - # Run Code Coverage - - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out - - cache: - key: build - paths: - - build/ - policy: pull - - artifacts: - paths: - - build/simulator/ddr3-example_ddr3_ch0.tdb - - coverage/${CI_JOB_NAME}.out - expire_in: 2 days - -# Testing Reordering with FR_FCFS Scheduling Algorithm: -fr_fcfs: - stage: DDR3 - script: - - export GCOV_PREFIX=$(pwd) - - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') - - cd build/simulator - - ./DRAMSys ../../DRAMSys/tests/DDR3/simulations/ddr3-fr_fcfs.xml ../../DRAMSys/tests/DDR3/ - - ls -lah - - ls -lah ../../DRAMSys/tests/DDR3/expected/ - - sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-fr_fcfs_ddr3_ch0.tdb ddr3-fr_fcfs_ddr3_ch0.tdb - - perl -e 'if(`sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-fr_fcfs_ddr3_ch0.tdb ddr3-fr_fcfs_ddr3_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' - - cd ../traceAnalyzer - - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/ddr3-fr_fcfs_ddr3_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi - # Run Code Coverage - - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out - - cache: - key: build - paths: - - build/ - policy: pull - - allow_failure: true # TODO should be removed after first tests - - artifacts: - paths: - - build/simulator/ddr3-fr_fcfs_ddr3_ch0.tdb - - coverage/${CI_JOB_NAME}.out - expire_in: 2 days - -# Testing with TLM Protocol Checker -protocol_checker: - stage: DDR3 - script: - - export GCOV_PREFIX=$(pwd) - - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') - - cd build/simulator - - ./DRAMSys ../../DRAMSys/tests/DDR3/simulations/ddr3-protocol_checker.xml ../../DRAMSys/tests/DDR3/ > output.txt - - echo "TODO" - - ls -lah - # Run Code Coverage - - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out - - cache: - key: build - paths: - - build/ - policy: pull - - artifacts: - paths: - - coverage/${CI_JOB_NAME}.out - expire_in: 2 days diff --git a/DRAMSys/tests/DDR3/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml b/DRAMSys/tests/DDR3/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml deleted file mode 100644 index b2c3af48..00000000 --- a/DRAMSys/tests/DDR3/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml +++ /dev/null @@ -1,34 +0,0 @@ - - - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 16 - 17 - 18 - 19 - 20 - 21 - 22 - 23 - 24 - 25 - 26 - 27 - 28 - 29 - - \ No newline at end of file diff --git a/DRAMSys/tests/DDR3/configs/mcconfigs/fifoStrict.xml b/DRAMSys/tests/DDR3/configs/mcconfigs/fifoStrict.xml deleted file mode 100644 index 44bf294e..00000000 --- a/DRAMSys/tests/DDR3/configs/mcconfigs/fifoStrict.xml +++ /dev/null @@ -1,20 +0,0 @@ - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml b/DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml deleted file mode 100644 index 7240485d..00000000 --- a/DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml +++ /dev/null @@ -1,20 +0,0 @@ - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/DDR3/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml b/DRAMSys/tests/DDR3/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml deleted file mode 100644 index 052f6773..00000000 --- a/DRAMSys/tests/DDR3/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml +++ /dev/null @@ -1,55 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/DDR3/configs/simulator/ddr3-protocol_checker.xml b/DRAMSys/tests/DDR3/configs/simulator/ddr3-protocol_checker.xml deleted file mode 100644 index 3efbabe7..00000000 --- a/DRAMSys/tests/DDR3/configs/simulator/ddr3-protocol_checker.xml +++ /dev/null @@ -1,29 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/DDR3/configs/simulator/ddr3.xml b/DRAMSys/tests/DDR3/configs/simulator/ddr3.xml deleted file mode 100644 index 1613737f..00000000 --- a/DRAMSys/tests/DDR3/configs/simulator/ddr3.xml +++ /dev/null @@ -1,29 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/DDR3/configs/thermalsim/config.xml b/DRAMSys/tests/DDR3/configs/thermalsim/config.xml deleted file mode 100644 index 4d32315e..00000000 --- a/DRAMSys/tests/DDR3/configs/thermalsim/config.xml +++ /dev/null @@ -1,14 +0,0 @@ - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/DDR3/configs/thermalsim/powerInfo.xml b/DRAMSys/tests/DDR3/configs/thermalsim/powerInfo.xml deleted file mode 100644 index 192cb4ea..00000000 --- a/DRAMSys/tests/DDR3/configs/thermalsim/powerInfo.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/DRAMSys/tests/DDR3/simulations/ddr3-example.xml b/DRAMSys/tests/DDR3/simulations/ddr3-example.xml deleted file mode 100644 index c6140385..00000000 --- a/DRAMSys/tests/DDR3/simulations/ddr3-example.xml +++ /dev/null @@ -1,25 +0,0 @@ - - - - - - - - - - - - - - - - - ddr3_example.stl - - diff --git a/DRAMSys/tests/DDR3/simulations/ddr3-fr_fcfs.xml b/DRAMSys/tests/DDR3/simulations/ddr3-fr_fcfs.xml deleted file mode 100644 index a432321b..00000000 --- a/DRAMSys/tests/DDR3/simulations/ddr3-fr_fcfs.xml +++ /dev/null @@ -1,25 +0,0 @@ - - - - - - - - - - - - - - - - - ddr3_example.stl - - diff --git a/DRAMSys/tests/DDR3/simulations/ddr3-protocol_checker.xml b/DRAMSys/tests/DDR3/simulations/ddr3-protocol_checker.xml deleted file mode 100644 index ececf822..00000000 --- a/DRAMSys/tests/DDR3/simulations/ddr3-protocol_checker.xml +++ /dev/null @@ -1,25 +0,0 @@ - - - - - - - - - - - - - - - - - ddr3_example.stl - - diff --git a/DRAMSys/tests/DDR4/ci.yml b/DRAMSys/tests/DDR4/ci.yml new file mode 100644 index 00000000..94dc5d4c --- /dev/null +++ b/DRAMSys/tests/DDR4/ci.yml @@ -0,0 +1,29 @@ +# DDR4 with 4 bank groups, flexible rankwise refresh and FrFcfs scheduler: +example_ddr4: + stage: DDR4 + script: + - export GCOV_PREFIX=$(pwd) + - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') + - cd build/simulator + - ./DRAMSys ../../DRAMSys/tests/DDR4/simulations/ddr4-example.json ../../DRAMSys/tests/DDR4/ + - ls -lah + - ls -lah ../../DRAMSys/tests/DDR4/expected/ + - sqldiff ../../DRAMSys/tests/DDR4/expected/ddr4-bankgrp_ddr4_ch0.tdb ddr4-bankgrp_ddr4_ch0.tdb + - perl -e 'if(`sqldiff ../../DRAMSys/tests/DDR4/expected/ddr4-bankgrp_ddr4_ch0.tdb ddr4-bankgrp_ddr4_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' + #- cd ../traceAnalyzer + #- python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/ddr4-bankgrp_ddr4_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi + # Run Code Coverage + - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out + + cache: + key: build + paths: + - build/ + policy: pull + + artifacts: + paths: + - build/simulator/ddr4-bankgrp_ddr4_ch0.tdb + - coverage/${CI_JOB_NAME}.out + expire_in: 2 days + diff --git a/DRAMSys/tests/DDR4/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json b/DRAMSys/tests/DDR4/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json new file mode 100644 index 00000000..be30b98f --- /dev/null +++ b/DRAMSys/tests/DDR4/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json @@ -0,0 +1,46 @@ +{ + "CONGEN": { + "BANKGROUP_BIT":[ + 30, + 31 + ], + "BANK_BIT": [ + 28, + 29 + ], + "BYTE_BIT": [ + 0, + 1, + 2 + ], + "COLUMN_BIT": [ + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12 + ], + "ROW_BIT": [ + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27 + ] + } +} diff --git a/DRAMSys/tests/DDR4/configs/mcconfigs/fr_fcfs.json b/DRAMSys/tests/DDR4/configs/mcconfigs/fr_fcfs.json new file mode 100644 index 00000000..01603197 --- /dev/null +++ b/DRAMSys/tests/DDR4/configs/mcconfigs/fr_fcfs.json @@ -0,0 +1,12 @@ +{"mcconfig": { + "PagePolicy": "ClosedAdaptive", + "Scheduler": "FrFcfs", + "RequestBufferSize": 8, + "CmdMux": "Oldest", + "RespQueue": "Fifo", + "RefreshPolicy": "Rankwise", + "RefreshMode": 1, + "RefreshMaxPostponed": 8, + "RefreshMaxPulledin": 8, + "PowerDownPolicy": "NoPowerDown", + "PowerDownTimeout": 100}} diff --git a/DRAMSys/tests/DDR4/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json b/DRAMSys/tests/DDR4/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json new file mode 100644 index 00000000..38a5701a --- /dev/null +++ b/DRAMSys/tests/DDR4/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json @@ -0,0 +1,68 @@ +{ + "memspec": { + "memarchitecturespec": { + "burstLength": 8, + "dataRate": 2, + "nbrOfBankGroups": 4, + "nbrOfBanks": 16, + "nbrOfColumns": 1024, + "nbrOfRanks": 1, + "nbrOfChannels": 1, + "nbrOfRows": 32768, + "width": 8, + "nbrOfDevicesOnDIMM": 8 + }, + "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A", + "memoryType": "DDR4", + "mempowerspec": { + "idd0": 56.25, + "idd02": 4.05, + "idd2n": 33.75, + "idd2p0": 17.0, + "idd2p1": 17.0, + "idd3n": 39.5, + "idd3p0": 22.5, + "idd3p1": 22.5, + "idd4r": 157.5, + "idd4w": 135.0, + "idd5": 118.0, + "idd6": 20.25, + "idd62": 2.6, + "vdd": 1.2, + "vdd2": 2.5 + }, + "memtimingspec": { + "AL": 0, + "CCD_L": 5, + "CCD_S": 4, + "CKE": 6, + "CKESR": 7, + "CL": 13, + "DQSCK": 2, + "FAW": 22, + "RAS": 32, + "RC": 45, + "RCD": 13, + "REFI": 3644, + "RFC": 243, + "RL": 13, + "RP": 13, + "RRD_L": 5, + "RRD_S": 4, + "RTP": 8, + "WL": 12, + "WR": 14, + "WTR_L": 7, + "WTR_S": 3, + "XP": 8, + "XPDLL": 255, + "XS": 252, + "XSDLL": 512, + "ACTPDEN": 1, + "PRPDEN": 1, + "REFPDEN": 1, + "RTRS": 1, + "clkMhz": 933 + } + } +} diff --git a/DRAMSys/tests/DDR4/configs/simulator/ddr4.json b/DRAMSys/tests/DDR4/configs/simulator/ddr4.json new file mode 100644 index 00000000..c88964d3 --- /dev/null +++ b/DRAMSys/tests/DDR4/configs/simulator/ddr4.json @@ -0,0 +1,19 @@ +{ + "simconfig": { + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, + "ECCControllerMode": "Disabled", + "EnableWindowing": false, + "ErrorCSVFile": "", + "ErrorChipSeed": 42, + "PowerAnalysis": true, + "SimulationName": "ddr4", + "SimulationProgressBar": true, + "StoreMode": "NoStorage", + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 + } +} diff --git a/DRAMSys/tests/DDR4/configs/thermalsim/config.json b/DRAMSys/tests/DDR4/configs/thermalsim/config.json new file mode 100644 index 00000000..b88ed84c --- /dev/null +++ b/DRAMSys/tests/DDR4/configs/thermalsim/config.json @@ -0,0 +1,15 @@ +{ + "thermalsimconfig": { + "TemperatureScale": "Celsius", + "StaticTemperatureDefaultValue": 89, + "ThermalSimPeriod":100, + "ThermalSimUnit":"us", + "PowerInfoFile": "powerInfo.json", + "IceServerIp": "127.0.0.1", + "IceServerPort": 11880, + "SimPeriodAdjustFactor" : 10, + "NPowStableCyclesToIncreasePeriod": 5, + "GenerateTemperatureMap": true, + "GeneratePowerMap": true + } +} diff --git a/DRAMSys/tests/DDR3/configs/thermalsim/core.flp b/DRAMSys/tests/DDR4/configs/thermalsim/core.flp similarity index 100% rename from DRAMSys/tests/DDR3/configs/thermalsim/core.flp rename to DRAMSys/tests/DDR4/configs/thermalsim/core.flp diff --git a/DRAMSys/tests/DDR3/configs/thermalsim/mem.flp b/DRAMSys/tests/DDR4/configs/thermalsim/mem.flp similarity index 100% rename from DRAMSys/tests/DDR3/configs/thermalsim/mem.flp rename to DRAMSys/tests/DDR4/configs/thermalsim/mem.flp diff --git a/DRAMSys/tests/DDR4/configs/thermalsim/powerInfo.json b/DRAMSys/tests/DDR4/configs/thermalsim/powerInfo.json new file mode 100644 index 00000000..524f690f --- /dev/null +++ b/DRAMSys/tests/DDR4/configs/thermalsim/powerInfo.json @@ -0,0 +1,20 @@ +{ + "powerInfo": { + "dram_die_channel0": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel1": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel2": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel3": { + "init_pow": 0, + "threshold": 1.0 + } + } +} diff --git a/DRAMSys/tests/DDR3/configs/thermalsim/stack.stk b/DRAMSys/tests/DDR4/configs/thermalsim/stack.stk similarity index 100% rename from DRAMSys/tests/DDR3/configs/thermalsim/stack.stk rename to DRAMSys/tests/DDR4/configs/thermalsim/stack.stk diff --git a/DRAMSys/tests/DDR3/scripts/createTraceDB.sql b/DRAMSys/tests/DDR4/scripts/createTraceDB.sql similarity index 100% rename from DRAMSys/tests/DDR3/scripts/createTraceDB.sql rename to DRAMSys/tests/DDR4/scripts/createTraceDB.sql diff --git a/DRAMSys/tests/DDR4/simulations/ddr4-example.json b/DRAMSys/tests/DDR4/simulations/ddr4-example.json new file mode 100644 index 00000000..d97481d9 --- /dev/null +++ b/DRAMSys/tests/DDR4/simulations/ddr4-example.json @@ -0,0 +1,16 @@ +{ + "simulation": { + "addressmapping": "am_ddr4_8x4Gbx8_dimm_p1KB_brc.json", + "mcconfig": "fr_fcfs.json", + "memspec": "MICRON_4Gb_DDR4-1866_8bit_A.json", + "simconfig": "ddr4.json", + "simulationid": "ddr4-bankgrp", + "thermalconfig": "config.json", + "tracesetup": [ + { + "clkMhz": 933, + "name": "trace_test3.stl" + } + ] + } +} diff --git a/DRAMSys/tests/HBM2/ci.yml b/DRAMSys/tests/HBM2/ci.yml new file mode 100644 index 00000000..1f34b6d1 --- /dev/null +++ b/DRAMSys/tests/HBM2/ci.yml @@ -0,0 +1,25 @@ +example_HBM2: + artifacts: + expire_in: "2 days" + paths: + - build/simulator/hbm2-example_hbm2_ch0.tdb + - "coverage/${CI_JOB_NAME}.out" + cache: + key: build + paths: + - build/ + policy: pull + script: + - "export GCOV_PREFIX=$(pwd)" + - "export GCOV_PREFIX_STRIP=$(pwd | awk -F\"/\" '{print NF-1}')" + - "cd build/simulator" + - "./DRAMSys ../../DRAMSys/tests/HBM2/simulations/hbm2-example.json ../../DRAMSys/tests/HBM2/" + - "ls -lah" + - "ls -lah ../../DRAMSys/tests/HBM2/expected/" + - "sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch0.tdb hbm2-example_hbm2_ch0.tdb" + - "perl -e 'if(`sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch0.tdb hbm2-example_hbm2_ch0.tdb` eq \"\") {exit(0)} else {exit(-1)}'" + - "sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch1.tdb hbm2-example_hbm2_ch1.tdb" + - "perl -e 'if(`sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch1.tdb hbm2-example_hbm2_ch1.tdb` eq \"\") {exit(0)} else {exit(-1)}'" + - "lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out" + stage: HBM2 + diff --git a/DRAMSys/tests/HBM2/configs/amconfigs/am_hbm2_8Gb_pc_brc.json b/DRAMSys/tests/HBM2/configs/amconfigs/am_hbm2_8Gb_pc_brc.json new file mode 100644 index 00000000..c9362ea4 --- /dev/null +++ b/DRAMSys/tests/HBM2/configs/amconfigs/am_hbm2_8Gb_pc_brc.json @@ -0,0 +1,47 @@ +{ + "CONGEN": { + "CHANNEL_BIT":[ + 30 + ], + "BANKGROUP_BIT":[ + 28, + 29 + ], + "BANK_BIT": [ + 26, + 27 + ], + "BYTE_BIT": [ + 0, + 1, + 2, + 3 + ], + "COLUMN_BIT": [ + 4, + 5, + 6, + 7, + 8, + 9, + 10 + ], + "ROW_BIT": [ + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25 + ] + } +} diff --git a/DRAMSys/tests/HBM2/configs/mcconfigs/fifoStrict.json b/DRAMSys/tests/HBM2/configs/mcconfigs/fifoStrict.json new file mode 100644 index 00000000..3546377c --- /dev/null +++ b/DRAMSys/tests/HBM2/configs/mcconfigs/fifoStrict.json @@ -0,0 +1,11 @@ +{"mcconfig": {"PagePolicy": "Closed", +"Scheduler": "Fifo", +"RequestBufferSize": 8, +"CmdMux": "Strict", +"RespQueue": "Fifo", +"RefreshPolicy": "Rankwise", +"RefreshMode": 1, +"RefreshMaxPostponed": 0, +"RefreshMaxPulledin": 0, +"PowerDownPolicy": "NoPowerDown", +"PowerDownTimeout": 100}} diff --git a/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json b/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json new file mode 100644 index 00000000..c10d1242 --- /dev/null +++ b/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json @@ -0,0 +1,47 @@ +{ + "memspec": { + "memarchitecturespec": { + "burstLength": 4, + "dataRate": 2, + "nbrOfBankGroups": 4, + "nbrOfBanks": 16, + "nbrOfColumns": 128, + "nbrOfRanks": 1, + "nbrOfChannels": 2, + "nbrOfRows": 32768, + "width": 128 + }, + "memoryId": "https://www.computerbase.de/2019-05/amd-memory-tweak-vram-oc/#bilder", + "memoryType": "HBM2", + "memtimingspec": { + "CCDL": 3, + "CCDS": 2, + "CKE": 8, + "DQSCK": 1, + "FAW": 16, + "PL": 0, + "RAS": 28, + "RC": 42, + "RCDRD": 12, + "RCDWR": 6, + "REFI": 3900, + "REFISB": 244, + "RFC": 220, + "RFCSB": 96, + "RL": 17, + "RP": 14, + "RRDL": 6, + "RRDS": 4, + "RREFD": 8, + "RTP": 5, + "RTW": 18, + "WL": 7, + "WR": 14, + "WTRL": 9, + "WTRS": 4, + "XP": 8, + "XS": 216, + "clkMhz": 1000 + } + } +} diff --git a/DRAMSys/tests/HBM2/configs/simulator/hbm2.json b/DRAMSys/tests/HBM2/configs/simulator/hbm2.json new file mode 100644 index 00000000..608aec41 --- /dev/null +++ b/DRAMSys/tests/HBM2/configs/simulator/hbm2.json @@ -0,0 +1,19 @@ +{ + "simconfig": { + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, + "ECCControllerMode": "Disabled", + "EnableWindowing": false, + "ErrorCSVFile": "", + "ErrorChipSeed": 42, + "PowerAnalysis": false, + "SimulationName": "hbm2", + "SimulationProgressBar": true, + "StoreMode": "NoStorage", + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 + } +} diff --git a/DRAMSys/tests/HBM2/configs/thermalsim/config.json b/DRAMSys/tests/HBM2/configs/thermalsim/config.json new file mode 100644 index 00000000..b88ed84c --- /dev/null +++ b/DRAMSys/tests/HBM2/configs/thermalsim/config.json @@ -0,0 +1,15 @@ +{ + "thermalsimconfig": { + "TemperatureScale": "Celsius", + "StaticTemperatureDefaultValue": 89, + "ThermalSimPeriod":100, + "ThermalSimUnit":"us", + "PowerInfoFile": "powerInfo.json", + "IceServerIp": "127.0.0.1", + "IceServerPort": 11880, + "SimPeriodAdjustFactor" : 10, + "NPowStableCyclesToIncreasePeriod": 5, + "GenerateTemperatureMap": true, + "GeneratePowerMap": true + } +} diff --git a/DRAMSys/tests/WIDEIO/configs/thermalsim/core.flp b/DRAMSys/tests/HBM2/configs/thermalsim/core.flp similarity index 100% rename from DRAMSys/tests/WIDEIO/configs/thermalsim/core.flp rename to DRAMSys/tests/HBM2/configs/thermalsim/core.flp diff --git a/DRAMSys/tests/WIDEIO/configs/thermalsim/mem.flp b/DRAMSys/tests/HBM2/configs/thermalsim/mem.flp similarity index 100% rename from DRAMSys/tests/WIDEIO/configs/thermalsim/mem.flp rename to DRAMSys/tests/HBM2/configs/thermalsim/mem.flp diff --git a/DRAMSys/tests/HBM2/configs/thermalsim/powerInfo.json b/DRAMSys/tests/HBM2/configs/thermalsim/powerInfo.json new file mode 100644 index 00000000..524f690f --- /dev/null +++ b/DRAMSys/tests/HBM2/configs/thermalsim/powerInfo.json @@ -0,0 +1,20 @@ +{ + "powerInfo": { + "dram_die_channel0": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel1": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel2": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel3": { + "init_pow": 0, + "threshold": 1.0 + } + } +} diff --git a/DRAMSys/tests/WIDEIO/configs/thermalsim/stack.stk b/DRAMSys/tests/HBM2/configs/thermalsim/stack.stk similarity index 100% rename from DRAMSys/tests/WIDEIO/configs/thermalsim/stack.stk rename to DRAMSys/tests/HBM2/configs/thermalsim/stack.stk diff --git a/DRAMSys/tests/WIDEIO/scripts/createTraceDB.sql b/DRAMSys/tests/HBM2/scripts/createTraceDB.sql similarity index 100% rename from DRAMSys/tests/WIDEIO/scripts/createTraceDB.sql rename to DRAMSys/tests/HBM2/scripts/createTraceDB.sql diff --git a/DRAMSys/tests/HBM2/simulations/hbm2-example.json b/DRAMSys/tests/HBM2/simulations/hbm2-example.json new file mode 100644 index 00000000..6fd5f064 --- /dev/null +++ b/DRAMSys/tests/HBM2/simulations/hbm2-example.json @@ -0,0 +1,20 @@ +{ + "simulation": { + "addressmapping": "am_hbm2_8Gb_pc_brc.json", + "mcconfig": "fifoStrict.json", + "memspec": "HBM2.json", + "simconfig": "hbm2.json", + "simulationid": "hbm2-example", + "thermalconfig": "config.json", + "tracesetup": [ + { + "clkMhz": 1000, + "name": "trace1_test4.stl" + }, + { + "clkMhz": 1000, + "name": "trace2_test4.stl" + } + ] + } +} diff --git a/DRAMSys/tests/WIDEIO/ci.yml b/DRAMSys/tests/WIDEIO/ci.yml deleted file mode 100644 index e04215e0..00000000 --- a/DRAMSys/tests/WIDEIO/ci.yml +++ /dev/null @@ -1,40 +0,0 @@ -# vim: set ts=4 sw=4 expandtab: -example_wideio: - stage: WIDEIO - script: - - export GCOV_PREFIX=$(pwd) - - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') - # Generate specific traces for WIDEIO: - - cd DRAMSys/tests/WIDEIO/traces/ - - perl generator.pl - - cd - - # Run DRAMSys - - cd build/simulator - - ./DRAMSys ../../DRAMSys/tests/WIDEIO/simulations/wideio-example.xml ../../DRAMSys/tests/WIDEIO/ - - ls - # Run Traceanalyzer testing scripts: - - cd ../traceAnalyzer - - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/wideio-example_wideio_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi - - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/wideio-example_wideio_ch1.tdb | if ! grep "failed"; then exit 0; else exit 1; fi - - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/wideio-example_wideio_ch2.tdb | if ! grep "failed"; then exit 0; else exit 1; fi - - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/wideio-example_wideio_ch3.tdb | if ! grep "failed"; then exit 0; else exit 1; fi - # Run Code Coverage - - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out - - cache: - key: build - paths: - - build/ - policy: pull - - allow_failure: true # TODO: should be removed once the problems are fixed! - - artifacts: - paths: - - build/simulator/wideio-example_wideio_ch0.tdb - - build/simulator/wideio-example_wideio_ch1.tdb - - build/simulator/wideio-example_wideio_ch2.tdb - - build/simulator/wideio-example_wideio_ch3.tdb - - coverage/${CI_JOB_NAME}.out - expire_in: 2 days - diff --git a/DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_brc.xml b/DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_brc.xml deleted file mode 100755 index c6a33e71..00000000 --- a/DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_brc.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_rbc.xml b/DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_rbc.xml deleted file mode 100755 index 511a7f0a..00000000 --- a/DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_rbc.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/DRAMSys/tests/WIDEIO/configs/mcconfigs/fifoStrict.xml b/DRAMSys/tests/WIDEIO/configs/mcconfigs/fifoStrict.xml deleted file mode 100644 index ed869b57..00000000 --- a/DRAMSys/tests/WIDEIO/configs/mcconfigs/fifoStrict.xml +++ /dev/null @@ -1,50 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/WIDEIO/configs/memspecs/wideio.xml b/DRAMSys/tests/WIDEIO/configs/memspecs/wideio.xml deleted file mode 100644 index fbe252d6..00000000 --- a/DRAMSys/tests/WIDEIO/configs/memspecs/wideio.xml +++ /dev/null @@ -1,61 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/WIDEIO/configs/simulator/wideio.xml b/DRAMSys/tests/WIDEIO/configs/simulator/wideio.xml deleted file mode 100644 index acd95599..00000000 --- a/DRAMSys/tests/WIDEIO/configs/simulator/wideio.xml +++ /dev/null @@ -1,24 +0,0 @@ - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/WIDEIO/configs/thermalsim/config.xml b/DRAMSys/tests/WIDEIO/configs/thermalsim/config.xml deleted file mode 100644 index 4d32315e..00000000 --- a/DRAMSys/tests/WIDEIO/configs/thermalsim/config.xml +++ /dev/null @@ -1,14 +0,0 @@ - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/WIDEIO/configs/thermalsim/powerInfo.xml b/DRAMSys/tests/WIDEIO/configs/thermalsim/powerInfo.xml deleted file mode 100644 index 192cb4ea..00000000 --- a/DRAMSys/tests/WIDEIO/configs/thermalsim/powerInfo.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/DRAMSys/tests/WIDEIO/simulations/wideio-example.xml b/DRAMSys/tests/WIDEIO/simulations/wideio-example.xml deleted file mode 100644 index fea1f568..00000000 --- a/DRAMSys/tests/WIDEIO/simulations/wideio-example.xml +++ /dev/null @@ -1,24 +0,0 @@ - - - - - - - - - - - - - - - - - wideio.stl - - diff --git a/DRAMSys/tests/WIDEIO/traces/generator.pl b/DRAMSys/tests/WIDEIO/traces/generator.pl deleted file mode 100644 index 173a0248..00000000 --- a/DRAMSys/tests/WIDEIO/traces/generator.pl +++ /dev/null @@ -1,75 +0,0 @@ -#!/usr/bin/perl -w -use warnings; -use strict; - -# Width: 128 bit -# -# Mapping: -# 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 -# H | H B B B | R R R R | R R R R | R R R R | R C C C | C C C C | Y Y Y Y - - -open(OUT, "> wideio.stl"); - -my $length = 100000; -my $size = 0x10; -my $channelOffset = 0x8000000; -my $state = 0; -# state 0: reads only linear -# state 1: reads only random -# state 2: read and writes linear - -for(my $i=0; $i < $length; $i += 4) -{ - my $r = 0; - - if($state == 0) - { - print OUT ($i+0).": read ".sprintf("0x%x",($size*$i)+0*$channelOffset)."\n"; - print OUT ($i+1).": read ".sprintf("0x%x",($size*$i)+1*$channelOffset)."\n"; - print OUT ($i+2).": read ".sprintf("0x%x",($size*$i)+2*$channelOffset)."\n"; - print OUT ($i+3).": read ".sprintf("0x%x",($size*$i)+3*$channelOffset)."\n"; - } - elsif($state == 1) - { - $r = int(rand($channelOffset)); - print OUT ($i+0).": read ".sprintf("0x%x",($size*$r)+0*$channelOffset)."\n"; - $r = int(rand($channelOffset)); - print OUT ($i+1).": read ".sprintf("0x%x",($size*$r)+1*$channelOffset)."\n"; - $r = int(rand($channelOffset)); - print OUT ($i+2).": read ".sprintf("0x%x",($size*$r)+2*$channelOffset)."\n"; - $r = int(rand($channelOffset)); - print OUT ($i+3).": read ".sprintf("0x%x",($size*$r)+3*$channelOffset)."\n"; - } - elsif($state == 2) - { - my $rw = int(rand(2))%2; - if($rw == 0) - { - print OUT "$i: read ".sprintf("0x%x",($size*$i)+0*$channelOffset)."\n"; - print OUT "$i: read ".sprintf("0x%x",($size*$i)+1*$channelOffset)."\n"; - print OUT "$i: read ".sprintf("0x%x",($size*$i)+2*$channelOffset)."\n"; - print OUT "$i: read ".sprintf("0x%x",($size*$i)+3*$channelOffset)."\n"; - } - else - { - print OUT "$i: write ".sprintf("0x%x",($size*$i)+0*$channelOffset)."\n"; - print OUT "$i: write ".sprintf("0x%x",($size*$i)+1*$channelOffset)."\n"; - print OUT "$i: write ".sprintf("0x%x",($size*$i)+2*$channelOffset)."\n"; - print OUT "$i: write ".sprintf("0x%x",($size*$i)+3*$channelOffset)."\n"; - } - } - else - { - print "Error generating traces (".$state.")"; - exit(-1); - } - - if(($i != 0) && (($i % 1000) == 0)) - { - # GOTO next state every 1000st request: - $state = ($state + 1) % 3; - } -} - -close(OUT); diff --git a/DRAMSys/tests/ddr3_multirank/ci.yml b/DRAMSys/tests/ddr3_multirank/ci.yml new file mode 100644 index 00000000..254c0e62 --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/ci.yml @@ -0,0 +1,29 @@ +# DDR3 Dual Rank Test with Staggered Power Down Policy and Scheduler FrFcfsGrp +example_ddr3: + stage: DDR3 + script: + - export GCOV_PREFIX=$(pwd) + - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') + - cd build/simulator + - ./DRAMSys ../../DRAMSys/tests/ddr3_multirank/simulations/ddr3-example.json ../../DRAMSys/tests/ddr3_multirank/ + - ls -lah + - ls -lah ../../DRAMSys/tests/ddr3_multirank/expected/ + - sqldiff ../../DRAMSys/tests/ddr3_multirank/expected/ddr3-dual-rank_ddr3_ch0.tdb ddr3-dual-rank_ddr3_ch0.tdb + - perl -e 'if(`sqldiff ../../DRAMSys/tests/ddr3_multirank/expected/ddr3-dual-rank_ddr3_ch0.tdb ddr3-dual-rank_ddr3_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' + #- cd ../traceAnalyzer + #- python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/ddr3_multirank_ddr3_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi + # Run Code Coverage + - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out + + cache: + key: build + paths: + - build/ + policy: pull + + artifacts: + paths: + - build/simulator/ddr3-dual-rank_ddr3_ch0.tdb + - coverage/${CI_JOB_NAME}.out + expire_in: 2 days + diff --git a/DRAMSys/tests/ddr3_multirank/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json b/DRAMSys/tests/ddr3_multirank/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json new file mode 100644 index 00000000..c82926c9 --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json @@ -0,0 +1,51 @@ +{ + "CONGEN": { + "XOR":[ + { + "FIRST":13, + "SECOND":16 + } + ], + "BANK_BIT": [ + 13, + 14, + 15 + ], + "BYTE_BIT": [ + 0, + 1, + 2 + ], + "COLUMN_BIT": [ + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12 + ], + "ROW_BIT": [ + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29 + ], + "RANK_BIT": [ + 30 + ] + } +} diff --git a/DRAMSys/tests/ddr3_multirank/configs/mcconfigs/fr_fcfs_grp.json b/DRAMSys/tests/ddr3_multirank/configs/mcconfigs/fr_fcfs_grp.json new file mode 100644 index 00000000..4ac02e30 --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/configs/mcconfigs/fr_fcfs_grp.json @@ -0,0 +1,12 @@ +{"mcconfig": + {"PagePolicy": "Open", + "Scheduler": "FrFcfsGrp", + "RequestBufferSize": 8, + "CmdMux": "Oldest", + "RespQueue": "Fifo", + "RefreshPolicy": "Rankwise", + "RefreshMode": 1, + "RefreshMaxPostponed": 0, + "RefreshMaxPulledin": 0, + "PowerDownPolicy": "Staggered", + "PowerDownTimeout": 100}} diff --git a/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json b/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json new file mode 100644 index 00000000..0c90c3ca --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json @@ -0,0 +1,61 @@ +{ + "memspec": { + "memarchitecturespec": { + "burstLength": 8, + "dataRate": 2, + "nbrOfBanks": 8, + "nbrOfColumns": 1024, + "nbrOfRanks": 2, + "nbrOfChannels": 1, + "nbrOfRows": 16384, + "width": 64, + "nbrOfDevicesOnDIMM": 1 + }, + "memoryId": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM", + "memoryType": "DDR3", + "mempowerspec": { + "idd0": 720.0, + "idd2n": 400.0, + "idd2p0": 80.0, + "idd2p1": 200.0, + "idd3n": 440.0, + "idd3p0": 240.0, + "idd3p1": 240.0, + "idd4r": 1200.0, + "idd4w": 1200.0, + "idd5": 1760.0, + "idd6": 48.0, + "vdd": 1.5 + }, + "memtimingspec": { + "AL": 0, + "CCD": 4, + "CKE": 3, + "CKESR": 4, + "CL": 7, + "DQSCK": 0, + "FAW": 20, + "RAS": 20, + "RC": 27, + "RCD": 7, + "REFI": 4160, + "RFC": 59, + "RL": 7, + "RP": 7, + "RRD": 4, + "RTP": 4, + "WL": 6, + "WR": 8, + "WTR": 4, + "XP": 4, + "XPDLL": 13, + "XS": 64, + "XSDLL": 512, + "ACTPDEN": 1, + "PRPDEN": 1, + "REFPDEN": 1, + "RTRS": 1, + "clkMhz": 533 + } + } +} diff --git a/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json b/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json new file mode 100644 index 00000000..1ade5aea --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json @@ -0,0 +1,19 @@ +{ + "simconfig": { + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, + "ECCControllerMode": "Disabled", + "EnableWindowing": false, + "ErrorCSVFile": "", + "ErrorChipSeed": 42, + "PowerAnalysis": true, + "SimulationName": "ddr3", + "SimulationProgressBar": true, + "StoreMode": "NoStorage", + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 + } +} diff --git a/DRAMSys/tests/ddr3_multirank/configs/thermalsim/config.json b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/config.json new file mode 100644 index 00000000..b88ed84c --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/config.json @@ -0,0 +1,15 @@ +{ + "thermalsimconfig": { + "TemperatureScale": "Celsius", + "StaticTemperatureDefaultValue": 89, + "ThermalSimPeriod":100, + "ThermalSimUnit":"us", + "PowerInfoFile": "powerInfo.json", + "IceServerIp": "127.0.0.1", + "IceServerPort": 11880, + "SimPeriodAdjustFactor" : 10, + "NPowStableCyclesToIncreasePeriod": 5, + "GenerateTemperatureMap": true, + "GeneratePowerMap": true + } +} diff --git a/DRAMSys/tests/ddr3_multirank/configs/thermalsim/core.flp b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/core.flp new file mode 100755 index 00000000..e85e6801 --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/core.flp @@ -0,0 +1,45 @@ +CPUs : + + position 0, 0 ; + dimension 2750, 4300 ; + +GPU : + + position 3350, 0 ; + dimension 2750, 4000 ; + +BASEBAND1 : + + position 4250, 4000 ; + dimension 1850, 3300 ; + +BASEBAND2 : + + position 3350, 7300 ; + dimension 2750, 3300 ; + +LLCACHE : + + position 0, 4300 ; + dimension 1900, 3000 ; + +DRAMCTRL1 : + + position 1900, 4300 ; + dimension 850, 3000 ; + +DRAMCTRL2 : + + position 3350, 4000 ; + dimension 900, 3300 ; + +TSVS : + + position 2750, 2300 ; + dimension 600, 6000 ; + +ACELLERATORS : + + position 0, 7300 ; + dimension 2750, 3300 ; + diff --git a/DRAMSys/tests/ddr3_multirank/configs/thermalsim/mem.flp b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/mem.flp new file mode 100755 index 00000000..29d02254 --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/mem.flp @@ -0,0 +1,16 @@ +channel0 : + position 150, 100 ; + dimension 2600, 5200 ; + +channel1 : + position 3350, 100 ; + dimension 2600, 5200 ; + +channel2 : + position 150, 5300 ; + dimension 2600, 5200 ; + +channel3 : + position 3350, 5300 ; + dimension 2600, 5200 ; + diff --git a/DRAMSys/tests/ddr3_multirank/configs/thermalsim/powerInfo.json b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/powerInfo.json new file mode 100644 index 00000000..524f690f --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/powerInfo.json @@ -0,0 +1,20 @@ +{ + "powerInfo": { + "dram_die_channel0": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel1": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel2": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel3": { + "init_pow": 0, + "threshold": 1.0 + } + } +} diff --git a/DRAMSys/tests/ddr3_multirank/configs/thermalsim/stack.stk b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/stack.stk new file mode 100755 index 00000000..ec74f020 --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/stack.stk @@ -0,0 +1,49 @@ +material SILICON : + thermal conductivity 1.30e-4 ; + volumetric heat capacity 1.628e-12 ; + +material BEOL : + thermal conductivity 2.25e-6 ; + volumetric heat capacity 2.175e-12 ; + +material COPPER : + thermal conductivity 4.01e-04 ; + volumetric heat capacity 3.37e-12 ; + +top heat sink : + //sink height 1e03, area 100e06, material COPPER ; + //spreader height 0.5e03, area 70e06, material SILICON ; + heat transfer coefficient 1.3e-09 ; + temperature 318.15 ; +dimensions : + chip length 6100, width 10600 ; + cell length 100, width 100 ; + + +layer PCB : + height 10 ; + material BEOL ; + +die DRAM : + layer 58.5 SILICON ; + source 2 SILICON ; + layer 1.5 BEOL ; + layer 58.5 SILICON ; + + +stack: + die DRAM_DIE DRAM floorplan "./mem.flp" ; + layer CONN_TO_PCB PCB ; + +solver: + transient step 0.01, slot 0.05 ; + initial temperature 300.0 ; + +output: + Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot ); + Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot ); + Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot ); + Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot ); + Tmap (DRAM_DIE, "output1.txt", slot) ; + Pmap (DRAM_DIE, "output2.txt", slot) ; + diff --git a/DRAMSys/tests/ddr3_multirank/scripts/createTraceDB.sql b/DRAMSys/tests/ddr3_multirank/scripts/createTraceDB.sql new file mode 100644 index 00000000..7a127fac --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/scripts/createTraceDB.sql @@ -0,0 +1,94 @@ +DROP TABLE IF EXISTS Phases; +DROP TABLE IF EXISTS GeneralInfo; +DROP TABLE IF EXISTS CommandLengths; +DROP TABLE IF EXISTS Comments; +DROP TABLE IF EXISTS ranges; +DROP TABLE IF EXISTS Transactions; +DROP TABLE IF EXISTS DebugMessages; +DROP TABLE IF EXISTS Power; + +CREATE TABLE Phases( + ID INTEGER PRIMARY KEY, + PhaseName TEXT, + PhaseBegin INTEGER, + PhaseEnd INTEGER, + Transact INTEGER +); + +CREATE TABLE GeneralInfo( + NumberOfTransactions INTEGER, + TraceEnd INTEGER, + NumberOfRanks INTEGER, + NumberOfBanks INTEGER, + clk INTEGER, + UnitOfTime TEXT, + MCconfig TEXT, + Memspec TEXT, + Traces TEXT, + WindowSize INTEGER, + FlexibleRefresh INTEGER, + MaxRefBurst INTEGER, + ControllerThread INTEGER +); + +CREATE TABLE CommandLengths( + ACT INTEGER, + PRE INTEGER, + PREA INTEGER, + RD INTEGER, + RDA INTEGER, + WR INTEGER, + WRA INTEGER, + REFA INTEGER, + REFB INTEGER, + PDEA INTEGER, + PDXA INTEGER, + PDEP INTEGER, + PDXP INTEGER, + SREFEN INTEGER, + SREFEX INTEGER +); + +CREATE TABLE Power( + time DOUBLE, + AveragePower DOUBLE +); + + +CREATE TABLE Comments( + Time INTEGER, + Text TEXT +); + +CREATE TABLE DebugMessages( + Time INTEGER, + Message TEXT +); + +-- use SQLITE R* TREE Module to make queries on timespans effecient (see http://www.sqlite.org/rtree.html) +CREATE VIRTUAL TABLE ranges USING rtree( + id, + begin, end +); + +CREATE TABLE Transactions( + ID INTEGER, + Range INTEGER, + Address INTEGER, + Burstlength INTEGER, + TThread INTEGER, + TChannel INTEGER, + TRank INTEGER, + TBankgroup INTEGER, + TBank INTEGER, + TRow INTEGER, + TColumn INTEGER, + DataStrobeBegin INTEGER, + DataStrobeEnd INTEGER, + TimeOfGeneration INTEGER, + Command TEXT + ); + +CREATE INDEX ranges_index ON Transactions(Range); +CREATE INDEX "phasesTransactions" ON "Phases" ("Transact" ASC); +CREATE INDEX "messageTimes" ON "DebugMessages" ("Time" ASC); diff --git a/DRAMSys/tests/ddr3_multirank/simulations/ddr3-example.json b/DRAMSys/tests/ddr3_multirank/simulations/ddr3-example.json new file mode 100644 index 00000000..b924da62 --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/simulations/ddr3-example.json @@ -0,0 +1,16 @@ +{ + "simulation": { + "addressmapping": "am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json", + "mcconfig": "fr_fcfs_grp.json", + "memspec": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json", + "simconfig": "ddr3.json", + "simulationid": "ddr3-dual-rank", + "thermalconfig": "config.json", + "tracesetup": [ + { + "clkMhz": 533, + "name": "trace_test2.stl" + } + ] + } +} diff --git a/DRAMSys/tests/lpddr4/ci.yml b/DRAMSys/tests/lpddr4/ci.yml new file mode 100644 index 00000000..ff811142 --- /dev/null +++ b/DRAMSys/tests/lpddr4/ci.yml @@ -0,0 +1,28 @@ +# LPDDR4 with Bankwise Flexible Refresh and FIFO Scheduler: +example_lpddr4: + stage: LPDDR4 + script: + - export GCOV_PREFIX=$(pwd) + - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') + - cd build/simulator + - ./DRAMSys ../../DRAMSys/tests/lpddr4/simulations/lpddr4-example.json ../../DRAMSys/tests/lpddr4/ + - ls -lah + - ls -lah ../../DRAMSys/tests/lpddr4/expected/ + - sqldiff ../../DRAMSys/tests/lpddr4/expected/lpddr4-example_lpddr4_ch0.tdb lpddr4-example_lpddr4_ch0.tdb + - perl -e 'if(`sqldiff ../../DRAMSys/tests/lpddr4/expected/lpddr4-example_lpddr4_ch0.tdb lpddr4-example_lpddr4_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' + #- cd ../traceAnalyzer + #- python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/lpddr4-example_lpddr4_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi + # Run Code Coverage + - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out + + cache: + key: build + paths: + - build/ + policy: pull + + artifacts: + paths: + - build/simulator/lpddr4-example_lpddr4_ch0.tdb + - coverage/${CI_JOB_NAME}.out + expire_in: 2 days diff --git a/DRAMSys/tests/lpddr4/configs/amconfigs/am_lpddr4_8Gbx16_brc.json b/DRAMSys/tests/lpddr4/configs/amconfigs/am_lpddr4_8Gbx16_brc.json new file mode 100644 index 00000000..e9b3ac9f --- /dev/null +++ b/DRAMSys/tests/lpddr4/configs/amconfigs/am_lpddr4_8Gbx16_brc.json @@ -0,0 +1,42 @@ +{ + "CONGEN": { + "BANK_BIT": [ + 27, + 28, + 29 + ], + "BYTE_BIT": [ + 0 + ], + "COLUMN_BIT": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10 + ], + "ROW_BIT": [ + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26 + ] + } +} \ No newline at end of file diff --git a/DRAMSys/tests/lpddr4/configs/mcconfigs/fifo.json b/DRAMSys/tests/lpddr4/configs/mcconfigs/fifo.json new file mode 100644 index 00000000..59b55965 --- /dev/null +++ b/DRAMSys/tests/lpddr4/configs/mcconfigs/fifo.json @@ -0,0 +1,11 @@ +{"mcconfig": {"PagePolicy": "OpenAdaptive", +"Scheduler": "Fifo", +"RequestBufferSize": 8, +"CmdMux": "Oldest", +"RespQueue": "Fifo", +"RefreshPolicy": "Bankwise", +"RefreshMode": 1, +"RefreshMaxPostponed": 8, +"RefreshMaxPulledin": 8, +"PowerDownPolicy": "NoPowerDown", +"PowerDownTimeout": 100}} diff --git a/DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json b/DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json new file mode 100644 index 00000000..223f064d --- /dev/null +++ b/DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json @@ -0,0 +1,50 @@ +{ + "memspec": { + "memarchitecturespec": { + "burstLength": 16, + "dataRate": 2, + "nbrOfBanks": 8, + "nbrOfColumns": 1024, + "nbrOfRanks": 1, + "nbrOfChannels": 1, + "nbrOfRows": 65536, + "width": 16 + }, + "memoryId": "JEDEC_8Gb_LPDDR4-3200_16bit", + "memoryType": "LPDDR4", + "memtimingspec": { + "CCD": 8, + "CKE": 12, + "CMDCKE": 3, + "DQS2DQ": 2, + "DQSCK": 6, + "DQSS": 1, + "ESCKE": 3, + "FAW": 64, + "PPD": 4, + "RAS": 68, + "RCD": 29, + "REFI": 6246, + "REFIPB": 780, + "RFCAB": 448, + "RFCPB": 224, + "RL": 28, + "RPAB": 34, + "RPPB": 29, + "RCAB": 102, + "RCPB": 97, + "RPST": 0, + "RRD": 16, + "RTP": 12, + "SR": 24, + "WL": 14, + "WPRE": 2, + "WR": 29, + "WTR": 16, + "XP": 12, + "XSR": 460, + "RTRS": 1, + "clkMhz": 1600 + } + } +} \ No newline at end of file diff --git a/DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json b/DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json new file mode 100644 index 00000000..6ea5b1bd --- /dev/null +++ b/DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json @@ -0,0 +1,19 @@ +{ + "simconfig": { + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, + "ECCControllerMode": "Disabled", + "EnableWindowing": false, + "ErrorCSVFile": "", + "ErrorChipSeed": 42, + "PowerAnalysis": false, + "SimulationName": "lpddr4", + "SimulationProgressBar": true, + "StoreMode": "NoStorage", + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 + } +} diff --git a/DRAMSys/tests/lpddr4/configs/thermalsim/config.json b/DRAMSys/tests/lpddr4/configs/thermalsim/config.json new file mode 100644 index 00000000..b88ed84c --- /dev/null +++ b/DRAMSys/tests/lpddr4/configs/thermalsim/config.json @@ -0,0 +1,15 @@ +{ + "thermalsimconfig": { + "TemperatureScale": "Celsius", + "StaticTemperatureDefaultValue": 89, + "ThermalSimPeriod":100, + "ThermalSimUnit":"us", + "PowerInfoFile": "powerInfo.json", + "IceServerIp": "127.0.0.1", + "IceServerPort": 11880, + "SimPeriodAdjustFactor" : 10, + "NPowStableCyclesToIncreasePeriod": 5, + "GenerateTemperatureMap": true, + "GeneratePowerMap": true + } +} diff --git a/DRAMSys/tests/lpddr4/configs/thermalsim/core.flp b/DRAMSys/tests/lpddr4/configs/thermalsim/core.flp new file mode 100755 index 00000000..e85e6801 --- /dev/null +++ b/DRAMSys/tests/lpddr4/configs/thermalsim/core.flp @@ -0,0 +1,45 @@ +CPUs : + + position 0, 0 ; + dimension 2750, 4300 ; + +GPU : + + position 3350, 0 ; + dimension 2750, 4000 ; + +BASEBAND1 : + + position 4250, 4000 ; + dimension 1850, 3300 ; + +BASEBAND2 : + + position 3350, 7300 ; + dimension 2750, 3300 ; + +LLCACHE : + + position 0, 4300 ; + dimension 1900, 3000 ; + +DRAMCTRL1 : + + position 1900, 4300 ; + dimension 850, 3000 ; + +DRAMCTRL2 : + + position 3350, 4000 ; + dimension 900, 3300 ; + +TSVS : + + position 2750, 2300 ; + dimension 600, 6000 ; + +ACELLERATORS : + + position 0, 7300 ; + dimension 2750, 3300 ; + diff --git a/DRAMSys/tests/lpddr4/configs/thermalsim/mem.flp b/DRAMSys/tests/lpddr4/configs/thermalsim/mem.flp new file mode 100755 index 00000000..29d02254 --- /dev/null +++ b/DRAMSys/tests/lpddr4/configs/thermalsim/mem.flp @@ -0,0 +1,16 @@ +channel0 : + position 150, 100 ; + dimension 2600, 5200 ; + +channel1 : + position 3350, 100 ; + dimension 2600, 5200 ; + +channel2 : + position 150, 5300 ; + dimension 2600, 5200 ; + +channel3 : + position 3350, 5300 ; + dimension 2600, 5200 ; + diff --git a/DRAMSys/tests/lpddr4/configs/thermalsim/powerInfo.json b/DRAMSys/tests/lpddr4/configs/thermalsim/powerInfo.json new file mode 100644 index 00000000..524f690f --- /dev/null +++ b/DRAMSys/tests/lpddr4/configs/thermalsim/powerInfo.json @@ -0,0 +1,20 @@ +{ + "powerInfo": { + "dram_die_channel0": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel1": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel2": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel3": { + "init_pow": 0, + "threshold": 1.0 + } + } +} diff --git a/DRAMSys/tests/lpddr4/configs/thermalsim/stack.stk b/DRAMSys/tests/lpddr4/configs/thermalsim/stack.stk new file mode 100755 index 00000000..ec74f020 --- /dev/null +++ b/DRAMSys/tests/lpddr4/configs/thermalsim/stack.stk @@ -0,0 +1,49 @@ +material SILICON : + thermal conductivity 1.30e-4 ; + volumetric heat capacity 1.628e-12 ; + +material BEOL : + thermal conductivity 2.25e-6 ; + volumetric heat capacity 2.175e-12 ; + +material COPPER : + thermal conductivity 4.01e-04 ; + volumetric heat capacity 3.37e-12 ; + +top heat sink : + //sink height 1e03, area 100e06, material COPPER ; + //spreader height 0.5e03, area 70e06, material SILICON ; + heat transfer coefficient 1.3e-09 ; + temperature 318.15 ; +dimensions : + chip length 6100, width 10600 ; + cell length 100, width 100 ; + + +layer PCB : + height 10 ; + material BEOL ; + +die DRAM : + layer 58.5 SILICON ; + source 2 SILICON ; + layer 1.5 BEOL ; + layer 58.5 SILICON ; + + +stack: + die DRAM_DIE DRAM floorplan "./mem.flp" ; + layer CONN_TO_PCB PCB ; + +solver: + transient step 0.01, slot 0.05 ; + initial temperature 300.0 ; + +output: + Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot ); + Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot ); + Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot ); + Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot ); + Tmap (DRAM_DIE, "output1.txt", slot) ; + Pmap (DRAM_DIE, "output2.txt", slot) ; + diff --git a/DRAMSys/tests/lpddr4/scripts/createTraceDB.sql b/DRAMSys/tests/lpddr4/scripts/createTraceDB.sql new file mode 100644 index 00000000..7a127fac --- /dev/null +++ b/DRAMSys/tests/lpddr4/scripts/createTraceDB.sql @@ -0,0 +1,94 @@ +DROP TABLE IF EXISTS Phases; +DROP TABLE IF EXISTS GeneralInfo; +DROP TABLE IF EXISTS CommandLengths; +DROP TABLE IF EXISTS Comments; +DROP TABLE IF EXISTS ranges; +DROP TABLE IF EXISTS Transactions; +DROP TABLE IF EXISTS DebugMessages; +DROP TABLE IF EXISTS Power; + +CREATE TABLE Phases( + ID INTEGER PRIMARY KEY, + PhaseName TEXT, + PhaseBegin INTEGER, + PhaseEnd INTEGER, + Transact INTEGER +); + +CREATE TABLE GeneralInfo( + NumberOfTransactions INTEGER, + TraceEnd INTEGER, + NumberOfRanks INTEGER, + NumberOfBanks INTEGER, + clk INTEGER, + UnitOfTime TEXT, + MCconfig TEXT, + Memspec TEXT, + Traces TEXT, + WindowSize INTEGER, + FlexibleRefresh INTEGER, + MaxRefBurst INTEGER, + ControllerThread INTEGER +); + +CREATE TABLE CommandLengths( + ACT INTEGER, + PRE INTEGER, + PREA INTEGER, + RD INTEGER, + RDA INTEGER, + WR INTEGER, + WRA INTEGER, + REFA INTEGER, + REFB INTEGER, + PDEA INTEGER, + PDXA INTEGER, + PDEP INTEGER, + PDXP INTEGER, + SREFEN INTEGER, + SREFEX INTEGER +); + +CREATE TABLE Power( + time DOUBLE, + AveragePower DOUBLE +); + + +CREATE TABLE Comments( + Time INTEGER, + Text TEXT +); + +CREATE TABLE DebugMessages( + Time INTEGER, + Message TEXT +); + +-- use SQLITE R* TREE Module to make queries on timespans effecient (see http://www.sqlite.org/rtree.html) +CREATE VIRTUAL TABLE ranges USING rtree( + id, + begin, end +); + +CREATE TABLE Transactions( + ID INTEGER, + Range INTEGER, + Address INTEGER, + Burstlength INTEGER, + TThread INTEGER, + TChannel INTEGER, + TRank INTEGER, + TBankgroup INTEGER, + TBank INTEGER, + TRow INTEGER, + TColumn INTEGER, + DataStrobeBegin INTEGER, + DataStrobeEnd INTEGER, + TimeOfGeneration INTEGER, + Command TEXT + ); + +CREATE INDEX ranges_index ON Transactions(Range); +CREATE INDEX "phasesTransactions" ON "Phases" ("Transact" ASC); +CREATE INDEX "messageTimes" ON "DebugMessages" ("Time" ASC); diff --git a/DRAMSys/tests/lpddr4/simulations/lpddr4-example.json b/DRAMSys/tests/lpddr4/simulations/lpddr4-example.json new file mode 100644 index 00000000..30211e69 --- /dev/null +++ b/DRAMSys/tests/lpddr4/simulations/lpddr4-example.json @@ -0,0 +1,16 @@ +{ + "simulation": { + "addressmapping": "am_lpddr4_8Gbx16_brc.json", + "mcconfig": "fifo.json", + "memspec": "JEDEC_8Gb_LPDDR4-3200_16bit.json", + "simconfig": "lpddr4.json", + "simulationid": "lpddr4-example", + "thermalconfig": "config.json", + "tracesetup": [ + { + "clkMhz": 1600, + "name": "trace_lpddr4.stl" + } + ] + } +}