From 3f8f12358bb7415fa2813b7b995ad855f7b79483 Mon Sep 17 00:00:00 2001 From: scorrea Date: Wed, 10 Jun 2020 12:32:20 +0200 Subject: [PATCH 01/34] new test files --- .../configs/amconfigs/am_hbm2_8Gb_pc_brc.json | 46 +++++++++ .../HBM2/configs/mcconfigs/fifoStrict.json | 11 +++ DRAMSys/tests/HBM2/configs/memspecs/HBM2.json | 46 +++++++++ .../tests/HBM2/configs/simulator/hbm2.json | 21 +++++ .../tests/HBM2/configs/thermalsim/config.json | 15 +++ .../tests/HBM2/configs/thermalsim/core.flp | 45 +++++++++ DRAMSys/tests/HBM2/configs/thermalsim/mem.flp | 16 ++++ .../HBM2/configs/thermalsim/powerInfo.json | 20 ++++ .../tests/HBM2/configs/thermalsim/stack.stk | 49 ++++++++++ DRAMSys/tests/HBM2/scripts/createTraceDB.sql | 94 +++++++++++++++++++ .../tests/HBM2/simulations/hbm2-example.json | 20 ++++ ..._ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json | 51 ++++++++++ .../configs/mcconfigs/fr_fcfs_grp.json | 12 +++ .../MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json | 55 +++++++++++ .../configs/simulator/ddr3.json | 21 +++++ .../configs/thermalsim/config.json | 15 +++ .../configs/thermalsim/core.flp | 45 +++++++++ .../ddr3_multirank/configs/thermalsim/mem.flp | 16 ++++ .../configs/thermalsim/powerInfo.json | 20 ++++ .../configs/thermalsim/stack.stk | 49 ++++++++++ .../ddr3_multirank/scripts/createTraceDB.sql | 94 +++++++++++++++++++ .../simulations/ddr3-example.json | 16 ++++ .../am_ddr4_8x4Gbx8_dimm_p1KB_brc.json | 46 +++++++++ .../configs/mcconfigs/fr_fcfs.json | 12 +++ .../memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json | 66 +++++++++++++ .../configs/simulator/ddr4.json | 21 +++++ .../configs/thermalsim/config.json | 15 +++ .../configs/thermalsim/core.flp | 45 +++++++++ .../configs/thermalsim/mem.flp | 16 ++++ .../configs/thermalsim/powerInfo.json | 20 ++++ .../configs/thermalsim/stack.stk | 49 ++++++++++ .../ddr4_bankgroups/scripts/createTraceDB.sql | 94 +++++++++++++++++++ .../simulations/ddr4-example.json | 16 ++++ .../amconfigs/am_lpddr4_8Gbx16_brc.json | 42 +++++++++ .../tests/lpddr4/configs/mcconfigs/fifo.json | 11 +++ .../memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json | 46 +++++++++ .../lpddr4/configs/simulator/lpddr4.json | 21 +++++ .../lpddr4/configs/thermalsim/config.json | 15 +++ .../tests/lpddr4/configs/thermalsim/core.flp | 45 +++++++++ .../tests/lpddr4/configs/thermalsim/mem.flp | 16 ++++ .../lpddr4/configs/thermalsim/powerInfo.json | 20 ++++ .../tests/lpddr4/configs/thermalsim/stack.stk | 49 ++++++++++ .../tests/lpddr4/scripts/createTraceDB.sql | 94 +++++++++++++++++++ .../lpddr4/simulations/lpddr4-example.json | 16 ++++ 44 files changed, 1552 insertions(+) create mode 100644 DRAMSys/tests/HBM2/configs/amconfigs/am_hbm2_8Gb_pc_brc.json create mode 100644 DRAMSys/tests/HBM2/configs/mcconfigs/fifoStrict.json create mode 100644 DRAMSys/tests/HBM2/configs/memspecs/HBM2.json create mode 100644 DRAMSys/tests/HBM2/configs/simulator/hbm2.json create mode 100644 DRAMSys/tests/HBM2/configs/thermalsim/config.json create mode 100755 DRAMSys/tests/HBM2/configs/thermalsim/core.flp create mode 100755 DRAMSys/tests/HBM2/configs/thermalsim/mem.flp create mode 100644 DRAMSys/tests/HBM2/configs/thermalsim/powerInfo.json create mode 100755 DRAMSys/tests/HBM2/configs/thermalsim/stack.stk create mode 100644 DRAMSys/tests/HBM2/scripts/createTraceDB.sql create mode 100644 DRAMSys/tests/HBM2/simulations/hbm2-example.json create mode 100644 DRAMSys/tests/ddr3_multirank/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json create mode 100644 DRAMSys/tests/ddr3_multirank/configs/mcconfigs/fr_fcfs_grp.json create mode 100644 DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json create mode 100644 DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json create mode 100644 DRAMSys/tests/ddr3_multirank/configs/thermalsim/config.json create mode 100755 DRAMSys/tests/ddr3_multirank/configs/thermalsim/core.flp create mode 100755 DRAMSys/tests/ddr3_multirank/configs/thermalsim/mem.flp create mode 100644 DRAMSys/tests/ddr3_multirank/configs/thermalsim/powerInfo.json create mode 100755 DRAMSys/tests/ddr3_multirank/configs/thermalsim/stack.stk create mode 100644 DRAMSys/tests/ddr3_multirank/scripts/createTraceDB.sql create mode 100644 DRAMSys/tests/ddr3_multirank/simulations/ddr3-example.json create mode 100644 DRAMSys/tests/ddr4_bankgroups/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json create mode 100644 DRAMSys/tests/ddr4_bankgroups/configs/mcconfigs/fr_fcfs.json create mode 100644 DRAMSys/tests/ddr4_bankgroups/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json create mode 100644 DRAMSys/tests/ddr4_bankgroups/configs/simulator/ddr4.json create mode 100644 DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/config.json create mode 100755 DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/core.flp create mode 100755 DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/mem.flp create mode 100644 DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/powerInfo.json create mode 100755 DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/stack.stk create mode 100644 DRAMSys/tests/ddr4_bankgroups/scripts/createTraceDB.sql create mode 100644 DRAMSys/tests/ddr4_bankgroups/simulations/ddr4-example.json create mode 100644 DRAMSys/tests/lpddr4/configs/amconfigs/am_lpddr4_8Gbx16_brc.json create mode 100644 DRAMSys/tests/lpddr4/configs/mcconfigs/fifo.json create mode 100644 DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json create mode 100644 DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json create mode 100644 DRAMSys/tests/lpddr4/configs/thermalsim/config.json create mode 100755 DRAMSys/tests/lpddr4/configs/thermalsim/core.flp create mode 100755 DRAMSys/tests/lpddr4/configs/thermalsim/mem.flp create mode 100644 DRAMSys/tests/lpddr4/configs/thermalsim/powerInfo.json create mode 100755 DRAMSys/tests/lpddr4/configs/thermalsim/stack.stk create mode 100644 DRAMSys/tests/lpddr4/scripts/createTraceDB.sql create mode 100644 DRAMSys/tests/lpddr4/simulations/lpddr4-example.json diff --git a/DRAMSys/tests/HBM2/configs/amconfigs/am_hbm2_8Gb_pc_brc.json b/DRAMSys/tests/HBM2/configs/amconfigs/am_hbm2_8Gb_pc_brc.json new file mode 100644 index 00000000..354217a5 --- /dev/null +++ b/DRAMSys/tests/HBM2/configs/amconfigs/am_hbm2_8Gb_pc_brc.json @@ -0,0 +1,46 @@ +{ + "CONGEN": { + "RANK_BIT":[ + 29 + ], + "BANKGROUP_BIT":[ + 27, + 28 + ], + "BANK_BIT": [ + 25, + 26 + ], + "BYTE_BIT": [ + 0, + 1, + 2 + ], + "COLUMN_BIT": [ + 3, + 4, + 5, + 6, + 7, + 8, + 9 + ], + "ROW_BIT": [ + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24 + ] + } +} diff --git a/DRAMSys/tests/HBM2/configs/mcconfigs/fifoStrict.json b/DRAMSys/tests/HBM2/configs/mcconfigs/fifoStrict.json new file mode 100644 index 00000000..3546377c --- /dev/null +++ b/DRAMSys/tests/HBM2/configs/mcconfigs/fifoStrict.json @@ -0,0 +1,11 @@ +{"mcconfig": {"PagePolicy": "Closed", +"Scheduler": "Fifo", +"RequestBufferSize": 8, +"CmdMux": "Strict", +"RespQueue": "Fifo", +"RefreshPolicy": "Rankwise", +"RefreshMode": 1, +"RefreshMaxPostponed": 0, +"RefreshMaxPulledin": 0, +"PowerDownPolicy": "NoPowerDown", +"PowerDownTimeout": 100}} diff --git a/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json b/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json new file mode 100644 index 00000000..efa8ee9e --- /dev/null +++ b/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json @@ -0,0 +1,46 @@ +{ + "memspec": { + "memarchitecturespec": { + "burstLength": 4, + "dataRate": 2, + "nbrOfBankGroups": 4, + "nbrOfBanks": 16, + "nbrOfColumns": 128, + "nbrOfRanks": 2, + "nbrOfRows": 32768, + "width": 64 + }, + "memoryId": "https://www.computerbase.de/2019-05/amd-memory-tweak-vram-oc/#bilder", + "memoryType": "HBM2", + "memtimingspec": { + "CCDL": 3, + "CCDS": 2, + "CKE": 8, + "DQSCK": 1, + "FAW": 16, + "PL": 0, + "RAS": 28, + "RC": 42, + "RCDRD": 12, + "RCDWR": 6, + "REFI": 3900, + "REFISB": 244, + "RFC": 220, + "RFCSB": 96, + "RL": 17, + "RP": 14, + "RRDL": 6, + "RRDS": 4, + "RREFD": 8, + "RTP": 5, + "RTW": 18, + "WL": 7, + "WR": 14, + "WTRL": 9, + "WTRS": 4, + "XP": 8, + "XS": 216, + "clkMhz": 1000 + } + } +} \ No newline at end of file diff --git a/DRAMSys/tests/HBM2/configs/simulator/hbm2.json b/DRAMSys/tests/HBM2/configs/simulator/hbm2.json new file mode 100644 index 00000000..9589611f --- /dev/null +++ b/DRAMSys/tests/HBM2/configs/simulator/hbm2.json @@ -0,0 +1,21 @@ +{ + "simconfig": { + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, + "ECCControllerMode": "Disabled", + "EnableWindowing": false, + "ErrorCSVFile": "", + "ErrorChipSeed": 42, + "NumberOfDevicesOnDIMM": 1, + "NumberOfMemChannels": 1, + "PowerAnalysis": false, + "SimulationName": "hbm2", + "SimulationProgressBar": true, + "StoreMode": "NoStorage", + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 + } +} \ No newline at end of file diff --git a/DRAMSys/tests/HBM2/configs/thermalsim/config.json b/DRAMSys/tests/HBM2/configs/thermalsim/config.json new file mode 100644 index 00000000..b88ed84c --- /dev/null +++ b/DRAMSys/tests/HBM2/configs/thermalsim/config.json @@ -0,0 +1,15 @@ +{ + "thermalsimconfig": { + "TemperatureScale": "Celsius", + "StaticTemperatureDefaultValue": 89, + "ThermalSimPeriod":100, + "ThermalSimUnit":"us", + "PowerInfoFile": "powerInfo.json", + "IceServerIp": "127.0.0.1", + "IceServerPort": 11880, + "SimPeriodAdjustFactor" : 10, + "NPowStableCyclesToIncreasePeriod": 5, + "GenerateTemperatureMap": true, + "GeneratePowerMap": true + } +} diff --git a/DRAMSys/tests/HBM2/configs/thermalsim/core.flp b/DRAMSys/tests/HBM2/configs/thermalsim/core.flp new file mode 100755 index 00000000..e85e6801 --- /dev/null +++ b/DRAMSys/tests/HBM2/configs/thermalsim/core.flp @@ -0,0 +1,45 @@ +CPUs : + + position 0, 0 ; + dimension 2750, 4300 ; + +GPU : + + position 3350, 0 ; + dimension 2750, 4000 ; + +BASEBAND1 : + + position 4250, 4000 ; + dimension 1850, 3300 ; + +BASEBAND2 : + + position 3350, 7300 ; + dimension 2750, 3300 ; + +LLCACHE : + + position 0, 4300 ; + dimension 1900, 3000 ; + +DRAMCTRL1 : + + position 1900, 4300 ; + dimension 850, 3000 ; + +DRAMCTRL2 : + + position 3350, 4000 ; + dimension 900, 3300 ; + +TSVS : + + position 2750, 2300 ; + dimension 600, 6000 ; + +ACELLERATORS : + + position 0, 7300 ; + dimension 2750, 3300 ; + diff --git a/DRAMSys/tests/HBM2/configs/thermalsim/mem.flp b/DRAMSys/tests/HBM2/configs/thermalsim/mem.flp new file mode 100755 index 00000000..29d02254 --- /dev/null +++ b/DRAMSys/tests/HBM2/configs/thermalsim/mem.flp @@ -0,0 +1,16 @@ +channel0 : + position 150, 100 ; + dimension 2600, 5200 ; + +channel1 : + position 3350, 100 ; + dimension 2600, 5200 ; + +channel2 : + position 150, 5300 ; + dimension 2600, 5200 ; + +channel3 : + position 3350, 5300 ; + dimension 2600, 5200 ; + diff --git a/DRAMSys/tests/HBM2/configs/thermalsim/powerInfo.json b/DRAMSys/tests/HBM2/configs/thermalsim/powerInfo.json new file mode 100644 index 00000000..524f690f --- /dev/null +++ b/DRAMSys/tests/HBM2/configs/thermalsim/powerInfo.json @@ -0,0 +1,20 @@ +{ + "powerInfo": { + "dram_die_channel0": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel1": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel2": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel3": { + "init_pow": 0, + "threshold": 1.0 + } + } +} diff --git a/DRAMSys/tests/HBM2/configs/thermalsim/stack.stk b/DRAMSys/tests/HBM2/configs/thermalsim/stack.stk new file mode 100755 index 00000000..ec74f020 --- /dev/null +++ b/DRAMSys/tests/HBM2/configs/thermalsim/stack.stk @@ -0,0 +1,49 @@ +material SILICON : + thermal conductivity 1.30e-4 ; + volumetric heat capacity 1.628e-12 ; + +material BEOL : + thermal conductivity 2.25e-6 ; + volumetric heat capacity 2.175e-12 ; + +material COPPER : + thermal conductivity 4.01e-04 ; + volumetric heat capacity 3.37e-12 ; + +top heat sink : + //sink height 1e03, area 100e06, material COPPER ; + //spreader height 0.5e03, area 70e06, material SILICON ; + heat transfer coefficient 1.3e-09 ; + temperature 318.15 ; +dimensions : + chip length 6100, width 10600 ; + cell length 100, width 100 ; + + +layer PCB : + height 10 ; + material BEOL ; + +die DRAM : + layer 58.5 SILICON ; + source 2 SILICON ; + layer 1.5 BEOL ; + layer 58.5 SILICON ; + + +stack: + die DRAM_DIE DRAM floorplan "./mem.flp" ; + layer CONN_TO_PCB PCB ; + +solver: + transient step 0.01, slot 0.05 ; + initial temperature 300.0 ; + +output: + Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot ); + Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot ); + Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot ); + Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot ); + Tmap (DRAM_DIE, "output1.txt", slot) ; + Pmap (DRAM_DIE, "output2.txt", slot) ; + diff --git a/DRAMSys/tests/HBM2/scripts/createTraceDB.sql b/DRAMSys/tests/HBM2/scripts/createTraceDB.sql new file mode 100644 index 00000000..7a127fac --- /dev/null +++ b/DRAMSys/tests/HBM2/scripts/createTraceDB.sql @@ -0,0 +1,94 @@ +DROP TABLE IF EXISTS Phases; +DROP TABLE IF EXISTS GeneralInfo; +DROP TABLE IF EXISTS CommandLengths; +DROP TABLE IF EXISTS Comments; +DROP TABLE IF EXISTS ranges; +DROP TABLE IF EXISTS Transactions; +DROP TABLE IF EXISTS DebugMessages; +DROP TABLE IF EXISTS Power; + +CREATE TABLE Phases( + ID INTEGER PRIMARY KEY, + PhaseName TEXT, + PhaseBegin INTEGER, + PhaseEnd INTEGER, + Transact INTEGER +); + +CREATE TABLE GeneralInfo( + NumberOfTransactions INTEGER, + TraceEnd INTEGER, + NumberOfRanks INTEGER, + NumberOfBanks INTEGER, + clk INTEGER, + UnitOfTime TEXT, + MCconfig TEXT, + Memspec TEXT, + Traces TEXT, + WindowSize INTEGER, + FlexibleRefresh INTEGER, + MaxRefBurst INTEGER, + ControllerThread INTEGER +); + +CREATE TABLE CommandLengths( + ACT INTEGER, + PRE INTEGER, + PREA INTEGER, + RD INTEGER, + RDA INTEGER, + WR INTEGER, + WRA INTEGER, + REFA INTEGER, + REFB INTEGER, + PDEA INTEGER, + PDXA INTEGER, + PDEP INTEGER, + PDXP INTEGER, + SREFEN INTEGER, + SREFEX INTEGER +); + +CREATE TABLE Power( + time DOUBLE, + AveragePower DOUBLE +); + + +CREATE TABLE Comments( + Time INTEGER, + Text TEXT +); + +CREATE TABLE DebugMessages( + Time INTEGER, + Message TEXT +); + +-- use SQLITE R* TREE Module to make queries on timespans effecient (see http://www.sqlite.org/rtree.html) +CREATE VIRTUAL TABLE ranges USING rtree( + id, + begin, end +); + +CREATE TABLE Transactions( + ID INTEGER, + Range INTEGER, + Address INTEGER, + Burstlength INTEGER, + TThread INTEGER, + TChannel INTEGER, + TRank INTEGER, + TBankgroup INTEGER, + TBank INTEGER, + TRow INTEGER, + TColumn INTEGER, + DataStrobeBegin INTEGER, + DataStrobeEnd INTEGER, + TimeOfGeneration INTEGER, + Command TEXT + ); + +CREATE INDEX ranges_index ON Transactions(Range); +CREATE INDEX "phasesTransactions" ON "Phases" ("Transact" ASC); +CREATE INDEX "messageTimes" ON "DebugMessages" ("Time" ASC); diff --git a/DRAMSys/tests/HBM2/simulations/hbm2-example.json b/DRAMSys/tests/HBM2/simulations/hbm2-example.json new file mode 100644 index 00000000..6fd5f064 --- /dev/null +++ b/DRAMSys/tests/HBM2/simulations/hbm2-example.json @@ -0,0 +1,20 @@ +{ + "simulation": { + "addressmapping": "am_hbm2_8Gb_pc_brc.json", + "mcconfig": "fifoStrict.json", + "memspec": "HBM2.json", + "simconfig": "hbm2.json", + "simulationid": "hbm2-example", + "thermalconfig": "config.json", + "tracesetup": [ + { + "clkMhz": 1000, + "name": "trace1_test4.stl" + }, + { + "clkMhz": 1000, + "name": "trace2_test4.stl" + } + ] + } +} diff --git a/DRAMSys/tests/ddr3_multirank/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json b/DRAMSys/tests/ddr3_multirank/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json new file mode 100644 index 00000000..c82926c9 --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json @@ -0,0 +1,51 @@ +{ + "CONGEN": { + "XOR":[ + { + "FIRST":13, + "SECOND":16 + } + ], + "BANK_BIT": [ + 13, + 14, + 15 + ], + "BYTE_BIT": [ + 0, + 1, + 2 + ], + "COLUMN_BIT": [ + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12 + ], + "ROW_BIT": [ + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29 + ], + "RANK_BIT": [ + 30 + ] + } +} diff --git a/DRAMSys/tests/ddr3_multirank/configs/mcconfigs/fr_fcfs_grp.json b/DRAMSys/tests/ddr3_multirank/configs/mcconfigs/fr_fcfs_grp.json new file mode 100644 index 00000000..4ac02e30 --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/configs/mcconfigs/fr_fcfs_grp.json @@ -0,0 +1,12 @@ +{"mcconfig": + {"PagePolicy": "Open", + "Scheduler": "FrFcfsGrp", + "RequestBufferSize": 8, + "CmdMux": "Oldest", + "RespQueue": "Fifo", + "RefreshPolicy": "Rankwise", + "RefreshMode": 1, + "RefreshMaxPostponed": 0, + "RefreshMaxPulledin": 0, + "PowerDownPolicy": "Staggered", + "PowerDownTimeout": 100}} diff --git a/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json b/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json new file mode 100644 index 00000000..13d9fef5 --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json @@ -0,0 +1,55 @@ +{ + "memspec": { + "memarchitecturespec": { + "burstLength": 8, + "dataRate": 2, + "nbrOfBanks": 8, + "nbrOfColumns": 1024, + "nbrOfRanks": 2, + "nbrOfRows": 16384, + "width": 8 + }, + "memoryId": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM", + "memoryType": "DDR3", + "mempowerspec": { + "idd0": 720.0, + "idd2n": 400.0, + "idd2p0": 80.0, + "idd2p1": 200.0, + "idd3n": 440.0, + "idd3p0": 240.0, + "idd3p1": 240.0, + "idd4r": 1200.0, + "idd4w": 1200.0, + "idd5": 1760.0, + "idd6": 48.0, + "vdd": 1.5 + }, + "memtimingspec": { + "AL": 0, + "CCD": 4, + "CKE": 3, + "CKESR": 4, + "CL": 7, + "DQSCK": 0, + "FAW": 20, + "RAS": 20, + "RC": 27, + "RCD": 7, + "REFI": 4160, + "RFC": 59, + "RL": 7, + "RP": 7, + "RRD": 4, + "RTP": 4, + "WL": 6, + "WR": 8, + "WTR": 4, + "XP": 4, + "XPDLL": 13, + "XS": 64, + "XSDLL": 512, + "clkMhz": 533 + } + } +} diff --git a/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json b/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json new file mode 100644 index 00000000..4e9faadc --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json @@ -0,0 +1,21 @@ +{ + "simconfig": { + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, + "ECCControllerMode": "Disabled", + "EnableWindowing": false, + "ErrorCSVFile": "", + "ErrorChipSeed": 42, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1, + "PowerAnalysis": false, + "SimulationName": "ddr3", + "SimulationProgressBar": true, + "StoreMode": "NoStorage", + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 + } +} diff --git a/DRAMSys/tests/ddr3_multirank/configs/thermalsim/config.json b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/config.json new file mode 100644 index 00000000..b88ed84c --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/config.json @@ -0,0 +1,15 @@ +{ + "thermalsimconfig": { + "TemperatureScale": "Celsius", + "StaticTemperatureDefaultValue": 89, + "ThermalSimPeriod":100, + "ThermalSimUnit":"us", + "PowerInfoFile": "powerInfo.json", + "IceServerIp": "127.0.0.1", + "IceServerPort": 11880, + "SimPeriodAdjustFactor" : 10, + "NPowStableCyclesToIncreasePeriod": 5, + "GenerateTemperatureMap": true, + "GeneratePowerMap": true + } +} diff --git a/DRAMSys/tests/ddr3_multirank/configs/thermalsim/core.flp b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/core.flp new file mode 100755 index 00000000..e85e6801 --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/core.flp @@ -0,0 +1,45 @@ +CPUs : + + position 0, 0 ; + dimension 2750, 4300 ; + +GPU : + + position 3350, 0 ; + dimension 2750, 4000 ; + +BASEBAND1 : + + position 4250, 4000 ; + dimension 1850, 3300 ; + +BASEBAND2 : + + position 3350, 7300 ; + dimension 2750, 3300 ; + +LLCACHE : + + position 0, 4300 ; + dimension 1900, 3000 ; + +DRAMCTRL1 : + + position 1900, 4300 ; + dimension 850, 3000 ; + +DRAMCTRL2 : + + position 3350, 4000 ; + dimension 900, 3300 ; + +TSVS : + + position 2750, 2300 ; + dimension 600, 6000 ; + +ACELLERATORS : + + position 0, 7300 ; + dimension 2750, 3300 ; + diff --git a/DRAMSys/tests/ddr3_multirank/configs/thermalsim/mem.flp b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/mem.flp new file mode 100755 index 00000000..29d02254 --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/mem.flp @@ -0,0 +1,16 @@ +channel0 : + position 150, 100 ; + dimension 2600, 5200 ; + +channel1 : + position 3350, 100 ; + dimension 2600, 5200 ; + +channel2 : + position 150, 5300 ; + dimension 2600, 5200 ; + +channel3 : + position 3350, 5300 ; + dimension 2600, 5200 ; + diff --git a/DRAMSys/tests/ddr3_multirank/configs/thermalsim/powerInfo.json b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/powerInfo.json new file mode 100644 index 00000000..524f690f --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/powerInfo.json @@ -0,0 +1,20 @@ +{ + "powerInfo": { + "dram_die_channel0": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel1": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel2": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel3": { + "init_pow": 0, + "threshold": 1.0 + } + } +} diff --git a/DRAMSys/tests/ddr3_multirank/configs/thermalsim/stack.stk b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/stack.stk new file mode 100755 index 00000000..ec74f020 --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/configs/thermalsim/stack.stk @@ -0,0 +1,49 @@ +material SILICON : + thermal conductivity 1.30e-4 ; + volumetric heat capacity 1.628e-12 ; + +material BEOL : + thermal conductivity 2.25e-6 ; + volumetric heat capacity 2.175e-12 ; + +material COPPER : + thermal conductivity 4.01e-04 ; + volumetric heat capacity 3.37e-12 ; + +top heat sink : + //sink height 1e03, area 100e06, material COPPER ; + //spreader height 0.5e03, area 70e06, material SILICON ; + heat transfer coefficient 1.3e-09 ; + temperature 318.15 ; +dimensions : + chip length 6100, width 10600 ; + cell length 100, width 100 ; + + +layer PCB : + height 10 ; + material BEOL ; + +die DRAM : + layer 58.5 SILICON ; + source 2 SILICON ; + layer 1.5 BEOL ; + layer 58.5 SILICON ; + + +stack: + die DRAM_DIE DRAM floorplan "./mem.flp" ; + layer CONN_TO_PCB PCB ; + +solver: + transient step 0.01, slot 0.05 ; + initial temperature 300.0 ; + +output: + Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot ); + Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot ); + Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot ); + Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot ); + Tmap (DRAM_DIE, "output1.txt", slot) ; + Pmap (DRAM_DIE, "output2.txt", slot) ; + diff --git a/DRAMSys/tests/ddr3_multirank/scripts/createTraceDB.sql b/DRAMSys/tests/ddr3_multirank/scripts/createTraceDB.sql new file mode 100644 index 00000000..7a127fac --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/scripts/createTraceDB.sql @@ -0,0 +1,94 @@ +DROP TABLE IF EXISTS Phases; +DROP TABLE IF EXISTS GeneralInfo; +DROP TABLE IF EXISTS CommandLengths; +DROP TABLE IF EXISTS Comments; +DROP TABLE IF EXISTS ranges; +DROP TABLE IF EXISTS Transactions; +DROP TABLE IF EXISTS DebugMessages; +DROP TABLE IF EXISTS Power; + +CREATE TABLE Phases( + ID INTEGER PRIMARY KEY, + PhaseName TEXT, + PhaseBegin INTEGER, + PhaseEnd INTEGER, + Transact INTEGER +); + +CREATE TABLE GeneralInfo( + NumberOfTransactions INTEGER, + TraceEnd INTEGER, + NumberOfRanks INTEGER, + NumberOfBanks INTEGER, + clk INTEGER, + UnitOfTime TEXT, + MCconfig TEXT, + Memspec TEXT, + Traces TEXT, + WindowSize INTEGER, + FlexibleRefresh INTEGER, + MaxRefBurst INTEGER, + ControllerThread INTEGER +); + +CREATE TABLE CommandLengths( + ACT INTEGER, + PRE INTEGER, + PREA INTEGER, + RD INTEGER, + RDA INTEGER, + WR INTEGER, + WRA INTEGER, + REFA INTEGER, + REFB INTEGER, + PDEA INTEGER, + PDXA INTEGER, + PDEP INTEGER, + PDXP INTEGER, + SREFEN INTEGER, + SREFEX INTEGER +); + +CREATE TABLE Power( + time DOUBLE, + AveragePower DOUBLE +); + + +CREATE TABLE Comments( + Time INTEGER, + Text TEXT +); + +CREATE TABLE DebugMessages( + Time INTEGER, + Message TEXT +); + +-- use SQLITE R* TREE Module to make queries on timespans effecient (see http://www.sqlite.org/rtree.html) +CREATE VIRTUAL TABLE ranges USING rtree( + id, + begin, end +); + +CREATE TABLE Transactions( + ID INTEGER, + Range INTEGER, + Address INTEGER, + Burstlength INTEGER, + TThread INTEGER, + TChannel INTEGER, + TRank INTEGER, + TBankgroup INTEGER, + TBank INTEGER, + TRow INTEGER, + TColumn INTEGER, + DataStrobeBegin INTEGER, + DataStrobeEnd INTEGER, + TimeOfGeneration INTEGER, + Command TEXT + ); + +CREATE INDEX ranges_index ON Transactions(Range); +CREATE INDEX "phasesTransactions" ON "Phases" ("Transact" ASC); +CREATE INDEX "messageTimes" ON "DebugMessages" ("Time" ASC); diff --git a/DRAMSys/tests/ddr3_multirank/simulations/ddr3-example.json b/DRAMSys/tests/ddr3_multirank/simulations/ddr3-example.json new file mode 100644 index 00000000..e3d4a4c3 --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/simulations/ddr3-example.json @@ -0,0 +1,16 @@ +{ + "simulation": { + "addressmapping": "am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json", + "mcconfig": "fr_fcfs_grp.json", + "memspec": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json", + "simconfig": "ddr3.json", + "simulationid": "ddr3-example-dual-rank-json", + "thermalconfig": "config.json", + "tracesetup": [ + { + "clkMhz": 533, + "name": "trace_test2.stl" + } + ] + } +} diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json b/DRAMSys/tests/ddr4_bankgroups/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json new file mode 100644 index 00000000..be30b98f --- /dev/null +++ b/DRAMSys/tests/ddr4_bankgroups/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json @@ -0,0 +1,46 @@ +{ + "CONGEN": { + "BANKGROUP_BIT":[ + 30, + 31 + ], + "BANK_BIT": [ + 28, + 29 + ], + "BYTE_BIT": [ + 0, + 1, + 2 + ], + "COLUMN_BIT": [ + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12 + ], + "ROW_BIT": [ + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27 + ] + } +} diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/mcconfigs/fr_fcfs.json b/DRAMSys/tests/ddr4_bankgroups/configs/mcconfigs/fr_fcfs.json new file mode 100644 index 00000000..2da01ceb --- /dev/null +++ b/DRAMSys/tests/ddr4_bankgroups/configs/mcconfigs/fr_fcfs.json @@ -0,0 +1,12 @@ +{"mcconfig": { + "PagePolicy": "Open", + "Scheduler": "FrFcfs", + "RequestBufferSize": 8, + "CmdMux": "Oldest", + "RespQueue": "Fifo", + "RefreshPolicy": "Rankwise", + "RefreshMode": 1, + "RefreshMaxPostponed": 128, + "RefreshMaxPulledin": 128, + "PowerDownPolicy": "NoPowerDown", + "PowerDownTimeout": 100}} diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json b/DRAMSys/tests/ddr4_bankgroups/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json new file mode 100644 index 00000000..11700aaf --- /dev/null +++ b/DRAMSys/tests/ddr4_bankgroups/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json @@ -0,0 +1,66 @@ +{ + "memspec": { + "memarchitecturespec": { + "burstLength": 8, + "dataRate": 2, + "nbrOfBankGroups": 4, + "nbrOfBanks": 16, + "nbrOfColumns": 1024, + "nbrOfRanks": 1, + "nbrOfRows": 32768, + "width": 8 + }, + "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A", + "memoryType": "DDR4", + "mempowerspec": { + "idd0": 56.25, + "idd02": 4.05, + "idd2n": 33.75, + "idd2p0": 17.0, + "idd2p1": 17.0, + "idd3n": 39.5, + "idd3p0": 22.5, + "idd3p1": 22.5, + "idd4r": 157.5, + "idd4w": 135.0, + "idd5": 118.0, + "idd6": 20.25, + "idd62": 2.6, + "vdd": 1.2, + "vdd2": 2.5 + }, + "memtimingspec": { + "AL": 0, + "CCD_L": 5, + "CCD_S": 4, + "CKE": 6, + "CKESR": 7, + "CL": 13, + "DQSCK": 2, + "FAW": 22, + "RAS": 32, + "RC": 45, + "RCD": 13, + "REFI": 3644, + "RFC": 243, + "RL": 13, + "RP": 13, + "RRD_L": 5, + "RRD_S": 4, + "RTP": 8, + "WL": 12, + "WR": 14, + "WTR_L": 7, + "WTR_S": 3, + "XP": 8, + "XPDLL": 255, + "XS": 252, + "XSDLL": 512, + "ACTPDEN": 1, + "PRPDEN": 1, + "REFPDEN": 1, + "RTRS": 1, + "clkMhz": 933 + } + } +} \ No newline at end of file diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/simulator/ddr4.json b/DRAMSys/tests/ddr4_bankgroups/configs/simulator/ddr4.json new file mode 100644 index 00000000..8e62e680 --- /dev/null +++ b/DRAMSys/tests/ddr4_bankgroups/configs/simulator/ddr4.json @@ -0,0 +1,21 @@ +{ + "simconfig": { + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, + "ECCControllerMode": "Disabled", + "EnableWindowing": false, + "ErrorCSVFile": "", + "ErrorChipSeed": 42, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1, + "PowerAnalysis": false, + "SimulationName": "ddr4", + "SimulationProgressBar": true, + "StoreMode": "NoStorage", + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 + } +} \ No newline at end of file diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/config.json b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/config.json new file mode 100644 index 00000000..b88ed84c --- /dev/null +++ b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/config.json @@ -0,0 +1,15 @@ +{ + "thermalsimconfig": { + "TemperatureScale": "Celsius", + "StaticTemperatureDefaultValue": 89, + "ThermalSimPeriod":100, + "ThermalSimUnit":"us", + "PowerInfoFile": "powerInfo.json", + "IceServerIp": "127.0.0.1", + "IceServerPort": 11880, + "SimPeriodAdjustFactor" : 10, + "NPowStableCyclesToIncreasePeriod": 5, + "GenerateTemperatureMap": true, + "GeneratePowerMap": true + } +} diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/core.flp b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/core.flp new file mode 100755 index 00000000..e85e6801 --- /dev/null +++ b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/core.flp @@ -0,0 +1,45 @@ +CPUs : + + position 0, 0 ; + dimension 2750, 4300 ; + +GPU : + + position 3350, 0 ; + dimension 2750, 4000 ; + +BASEBAND1 : + + position 4250, 4000 ; + dimension 1850, 3300 ; + +BASEBAND2 : + + position 3350, 7300 ; + dimension 2750, 3300 ; + +LLCACHE : + + position 0, 4300 ; + dimension 1900, 3000 ; + +DRAMCTRL1 : + + position 1900, 4300 ; + dimension 850, 3000 ; + +DRAMCTRL2 : + + position 3350, 4000 ; + dimension 900, 3300 ; + +TSVS : + + position 2750, 2300 ; + dimension 600, 6000 ; + +ACELLERATORS : + + position 0, 7300 ; + dimension 2750, 3300 ; + diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/mem.flp b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/mem.flp new file mode 100755 index 00000000..29d02254 --- /dev/null +++ b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/mem.flp @@ -0,0 +1,16 @@ +channel0 : + position 150, 100 ; + dimension 2600, 5200 ; + +channel1 : + position 3350, 100 ; + dimension 2600, 5200 ; + +channel2 : + position 150, 5300 ; + dimension 2600, 5200 ; + +channel3 : + position 3350, 5300 ; + dimension 2600, 5200 ; + diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/powerInfo.json b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/powerInfo.json new file mode 100644 index 00000000..524f690f --- /dev/null +++ b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/powerInfo.json @@ -0,0 +1,20 @@ +{ + "powerInfo": { + "dram_die_channel0": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel1": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel2": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel3": { + "init_pow": 0, + "threshold": 1.0 + } + } +} diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/stack.stk b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/stack.stk new file mode 100755 index 00000000..ec74f020 --- /dev/null +++ b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/stack.stk @@ -0,0 +1,49 @@ +material SILICON : + thermal conductivity 1.30e-4 ; + volumetric heat capacity 1.628e-12 ; + +material BEOL : + thermal conductivity 2.25e-6 ; + volumetric heat capacity 2.175e-12 ; + +material COPPER : + thermal conductivity 4.01e-04 ; + volumetric heat capacity 3.37e-12 ; + +top heat sink : + //sink height 1e03, area 100e06, material COPPER ; + //spreader height 0.5e03, area 70e06, material SILICON ; + heat transfer coefficient 1.3e-09 ; + temperature 318.15 ; +dimensions : + chip length 6100, width 10600 ; + cell length 100, width 100 ; + + +layer PCB : + height 10 ; + material BEOL ; + +die DRAM : + layer 58.5 SILICON ; + source 2 SILICON ; + layer 1.5 BEOL ; + layer 58.5 SILICON ; + + +stack: + die DRAM_DIE DRAM floorplan "./mem.flp" ; + layer CONN_TO_PCB PCB ; + +solver: + transient step 0.01, slot 0.05 ; + initial temperature 300.0 ; + +output: + Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot ); + Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot ); + Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot ); + Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot ); + Tmap (DRAM_DIE, "output1.txt", slot) ; + Pmap (DRAM_DIE, "output2.txt", slot) ; + diff --git a/DRAMSys/tests/ddr4_bankgroups/scripts/createTraceDB.sql b/DRAMSys/tests/ddr4_bankgroups/scripts/createTraceDB.sql new file mode 100644 index 00000000..7a127fac --- /dev/null +++ b/DRAMSys/tests/ddr4_bankgroups/scripts/createTraceDB.sql @@ -0,0 +1,94 @@ +DROP TABLE IF EXISTS Phases; +DROP TABLE IF EXISTS GeneralInfo; +DROP TABLE IF EXISTS CommandLengths; +DROP TABLE IF EXISTS Comments; +DROP TABLE IF EXISTS ranges; +DROP TABLE IF EXISTS Transactions; +DROP TABLE IF EXISTS DebugMessages; +DROP TABLE IF EXISTS Power; + +CREATE TABLE Phases( + ID INTEGER PRIMARY KEY, + PhaseName TEXT, + PhaseBegin INTEGER, + PhaseEnd INTEGER, + Transact INTEGER +); + +CREATE TABLE GeneralInfo( + NumberOfTransactions INTEGER, + TraceEnd INTEGER, + NumberOfRanks INTEGER, + NumberOfBanks INTEGER, + clk INTEGER, + UnitOfTime TEXT, + MCconfig TEXT, + Memspec TEXT, + Traces TEXT, + WindowSize INTEGER, + FlexibleRefresh INTEGER, + MaxRefBurst INTEGER, + ControllerThread INTEGER +); + +CREATE TABLE CommandLengths( + ACT INTEGER, + PRE INTEGER, + PREA INTEGER, + RD INTEGER, + RDA INTEGER, + WR INTEGER, + WRA INTEGER, + REFA INTEGER, + REFB INTEGER, + PDEA INTEGER, + PDXA INTEGER, + PDEP INTEGER, + PDXP INTEGER, + SREFEN INTEGER, + SREFEX INTEGER +); + +CREATE TABLE Power( + time DOUBLE, + AveragePower DOUBLE +); + + +CREATE TABLE Comments( + Time INTEGER, + Text TEXT +); + +CREATE TABLE DebugMessages( + Time INTEGER, + Message TEXT +); + +-- use SQLITE R* TREE Module to make queries on timespans effecient (see http://www.sqlite.org/rtree.html) +CREATE VIRTUAL TABLE ranges USING rtree( + id, + begin, end +); + +CREATE TABLE Transactions( + ID INTEGER, + Range INTEGER, + Address INTEGER, + Burstlength INTEGER, + TThread INTEGER, + TChannel INTEGER, + TRank INTEGER, + TBankgroup INTEGER, + TBank INTEGER, + TRow INTEGER, + TColumn INTEGER, + DataStrobeBegin INTEGER, + DataStrobeEnd INTEGER, + TimeOfGeneration INTEGER, + Command TEXT + ); + +CREATE INDEX ranges_index ON Transactions(Range); +CREATE INDEX "phasesTransactions" ON "Phases" ("Transact" ASC); +CREATE INDEX "messageTimes" ON "DebugMessages" ("Time" ASC); diff --git a/DRAMSys/tests/ddr4_bankgroups/simulations/ddr4-example.json b/DRAMSys/tests/ddr4_bankgroups/simulations/ddr4-example.json new file mode 100644 index 00000000..d97481d9 --- /dev/null +++ b/DRAMSys/tests/ddr4_bankgroups/simulations/ddr4-example.json @@ -0,0 +1,16 @@ +{ + "simulation": { + "addressmapping": "am_ddr4_8x4Gbx8_dimm_p1KB_brc.json", + "mcconfig": "fr_fcfs.json", + "memspec": "MICRON_4Gb_DDR4-1866_8bit_A.json", + "simconfig": "ddr4.json", + "simulationid": "ddr4-bankgrp", + "thermalconfig": "config.json", + "tracesetup": [ + { + "clkMhz": 933, + "name": "trace_test3.stl" + } + ] + } +} diff --git a/DRAMSys/tests/lpddr4/configs/amconfigs/am_lpddr4_8Gbx16_brc.json b/DRAMSys/tests/lpddr4/configs/amconfigs/am_lpddr4_8Gbx16_brc.json new file mode 100644 index 00000000..e9b3ac9f --- /dev/null +++ b/DRAMSys/tests/lpddr4/configs/amconfigs/am_lpddr4_8Gbx16_brc.json @@ -0,0 +1,42 @@ +{ + "CONGEN": { + "BANK_BIT": [ + 27, + 28, + 29 + ], + "BYTE_BIT": [ + 0 + ], + "COLUMN_BIT": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10 + ], + "ROW_BIT": [ + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26 + ] + } +} \ No newline at end of file diff --git a/DRAMSys/tests/lpddr4/configs/mcconfigs/fifo.json b/DRAMSys/tests/lpddr4/configs/mcconfigs/fifo.json new file mode 100644 index 00000000..712e1c96 --- /dev/null +++ b/DRAMSys/tests/lpddr4/configs/mcconfigs/fifo.json @@ -0,0 +1,11 @@ +{"mcconfig": {"PagePolicy": "Open", +"Scheduler": "Fifo", +"RequestBufferSize": 8, +"CmdMux": "Oldest", +"RespQueue": "Fifo", +"RefreshPolicy": "Bankwise", +"RefreshMode": 1, +"RefreshMaxPostponed": 8, +"RefreshMaxPulledin": 8, +"PowerDownPolicy": "NoPowerDown", +"PowerDownTimeout": 100}} diff --git a/DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json b/DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json new file mode 100644 index 00000000..97a8cc3e --- /dev/null +++ b/DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json @@ -0,0 +1,46 @@ +{ + "memspec": { + "memarchitecturespec": { + "burstLength": 16, + "dataRate": 2, + "nbrOfBanks": 8, + "nbrOfColumns": 1024, + "nbrOfRanks": 1, + "nbrOfRows": 65536, + "width": 16 + }, + "memoryId": "JEDEC_8Gb_LPDDR4-3200_16bit", + "memoryType": "LPDDR4", + "memtimingspec": { + "CCD": 8, + "CKE": 12, + "CMDCKE": 3, + "DQS2DQ": 2, + "DQSCK": 6, + "DQSS": 1, + "ESCKE": 3, + "FAW": 64, + "PPD": 4, + "RAS": 68, + "RCD": 29, + "REFI": 6246, + "REFIPB": 780, + "RFCAB": 448, + "RFCPB": 224, + "RL": 28, + "RPAB": 34, + "RPPB": 29, + "RPST": 0, + "RRD": 16, + "RTP": 12, + "SR": 24, + "WL": 14, + "WPRE": 2, + "WR": 29, + "WTR": 16, + "XP": 12, + "XSR": 460, + "clkMhz": 1600 + } + } +} \ No newline at end of file diff --git a/DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json b/DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json new file mode 100644 index 00000000..fd8fe855 --- /dev/null +++ b/DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json @@ -0,0 +1,21 @@ +{ + "simconfig": { + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, + "ECCControllerMode": "Disabled", + "EnableWindowing": false, + "ErrorCSVFile": "", + "ErrorChipSeed": 42, + "NumberOfDevicesOnDIMM": 1, + "NumberOfMemChannels": 1, + "PowerAnalysis": false, + "SimulationName": "lpddr4", + "SimulationProgressBar": true, + "StoreMode": "NoStorage", + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 + } +} \ No newline at end of file diff --git a/DRAMSys/tests/lpddr4/configs/thermalsim/config.json b/DRAMSys/tests/lpddr4/configs/thermalsim/config.json new file mode 100644 index 00000000..b88ed84c --- /dev/null +++ b/DRAMSys/tests/lpddr4/configs/thermalsim/config.json @@ -0,0 +1,15 @@ +{ + "thermalsimconfig": { + "TemperatureScale": "Celsius", + "StaticTemperatureDefaultValue": 89, + "ThermalSimPeriod":100, + "ThermalSimUnit":"us", + "PowerInfoFile": "powerInfo.json", + "IceServerIp": "127.0.0.1", + "IceServerPort": 11880, + "SimPeriodAdjustFactor" : 10, + "NPowStableCyclesToIncreasePeriod": 5, + "GenerateTemperatureMap": true, + "GeneratePowerMap": true + } +} diff --git a/DRAMSys/tests/lpddr4/configs/thermalsim/core.flp b/DRAMSys/tests/lpddr4/configs/thermalsim/core.flp new file mode 100755 index 00000000..e85e6801 --- /dev/null +++ b/DRAMSys/tests/lpddr4/configs/thermalsim/core.flp @@ -0,0 +1,45 @@ +CPUs : + + position 0, 0 ; + dimension 2750, 4300 ; + +GPU : + + position 3350, 0 ; + dimension 2750, 4000 ; + +BASEBAND1 : + + position 4250, 4000 ; + dimension 1850, 3300 ; + +BASEBAND2 : + + position 3350, 7300 ; + dimension 2750, 3300 ; + +LLCACHE : + + position 0, 4300 ; + dimension 1900, 3000 ; + +DRAMCTRL1 : + + position 1900, 4300 ; + dimension 850, 3000 ; + +DRAMCTRL2 : + + position 3350, 4000 ; + dimension 900, 3300 ; + +TSVS : + + position 2750, 2300 ; + dimension 600, 6000 ; + +ACELLERATORS : + + position 0, 7300 ; + dimension 2750, 3300 ; + diff --git a/DRAMSys/tests/lpddr4/configs/thermalsim/mem.flp b/DRAMSys/tests/lpddr4/configs/thermalsim/mem.flp new file mode 100755 index 00000000..29d02254 --- /dev/null +++ b/DRAMSys/tests/lpddr4/configs/thermalsim/mem.flp @@ -0,0 +1,16 @@ +channel0 : + position 150, 100 ; + dimension 2600, 5200 ; + +channel1 : + position 3350, 100 ; + dimension 2600, 5200 ; + +channel2 : + position 150, 5300 ; + dimension 2600, 5200 ; + +channel3 : + position 3350, 5300 ; + dimension 2600, 5200 ; + diff --git a/DRAMSys/tests/lpddr4/configs/thermalsim/powerInfo.json b/DRAMSys/tests/lpddr4/configs/thermalsim/powerInfo.json new file mode 100644 index 00000000..524f690f --- /dev/null +++ b/DRAMSys/tests/lpddr4/configs/thermalsim/powerInfo.json @@ -0,0 +1,20 @@ +{ + "powerInfo": { + "dram_die_channel0": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel1": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel2": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel3": { + "init_pow": 0, + "threshold": 1.0 + } + } +} diff --git a/DRAMSys/tests/lpddr4/configs/thermalsim/stack.stk b/DRAMSys/tests/lpddr4/configs/thermalsim/stack.stk new file mode 100755 index 00000000..ec74f020 --- /dev/null +++ b/DRAMSys/tests/lpddr4/configs/thermalsim/stack.stk @@ -0,0 +1,49 @@ +material SILICON : + thermal conductivity 1.30e-4 ; + volumetric heat capacity 1.628e-12 ; + +material BEOL : + thermal conductivity 2.25e-6 ; + volumetric heat capacity 2.175e-12 ; + +material COPPER : + thermal conductivity 4.01e-04 ; + volumetric heat capacity 3.37e-12 ; + +top heat sink : + //sink height 1e03, area 100e06, material COPPER ; + //spreader height 0.5e03, area 70e06, material SILICON ; + heat transfer coefficient 1.3e-09 ; + temperature 318.15 ; +dimensions : + chip length 6100, width 10600 ; + cell length 100, width 100 ; + + +layer PCB : + height 10 ; + material BEOL ; + +die DRAM : + layer 58.5 SILICON ; + source 2 SILICON ; + layer 1.5 BEOL ; + layer 58.5 SILICON ; + + +stack: + die DRAM_DIE DRAM floorplan "./mem.flp" ; + layer CONN_TO_PCB PCB ; + +solver: + transient step 0.01, slot 0.05 ; + initial temperature 300.0 ; + +output: + Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot ); + Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot ); + Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot ); + Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot ); + Tmap (DRAM_DIE, "output1.txt", slot) ; + Pmap (DRAM_DIE, "output2.txt", slot) ; + diff --git a/DRAMSys/tests/lpddr4/scripts/createTraceDB.sql b/DRAMSys/tests/lpddr4/scripts/createTraceDB.sql new file mode 100644 index 00000000..7a127fac --- /dev/null +++ b/DRAMSys/tests/lpddr4/scripts/createTraceDB.sql @@ -0,0 +1,94 @@ +DROP TABLE IF EXISTS Phases; +DROP TABLE IF EXISTS GeneralInfo; +DROP TABLE IF EXISTS CommandLengths; +DROP TABLE IF EXISTS Comments; +DROP TABLE IF EXISTS ranges; +DROP TABLE IF EXISTS Transactions; +DROP TABLE IF EXISTS DebugMessages; +DROP TABLE IF EXISTS Power; + +CREATE TABLE Phases( + ID INTEGER PRIMARY KEY, + PhaseName TEXT, + PhaseBegin INTEGER, + PhaseEnd INTEGER, + Transact INTEGER +); + +CREATE TABLE GeneralInfo( + NumberOfTransactions INTEGER, + TraceEnd INTEGER, + NumberOfRanks INTEGER, + NumberOfBanks INTEGER, + clk INTEGER, + UnitOfTime TEXT, + MCconfig TEXT, + Memspec TEXT, + Traces TEXT, + WindowSize INTEGER, + FlexibleRefresh INTEGER, + MaxRefBurst INTEGER, + ControllerThread INTEGER +); + +CREATE TABLE CommandLengths( + ACT INTEGER, + PRE INTEGER, + PREA INTEGER, + RD INTEGER, + RDA INTEGER, + WR INTEGER, + WRA INTEGER, + REFA INTEGER, + REFB INTEGER, + PDEA INTEGER, + PDXA INTEGER, + PDEP INTEGER, + PDXP INTEGER, + SREFEN INTEGER, + SREFEX INTEGER +); + +CREATE TABLE Power( + time DOUBLE, + AveragePower DOUBLE +); + + +CREATE TABLE Comments( + Time INTEGER, + Text TEXT +); + +CREATE TABLE DebugMessages( + Time INTEGER, + Message TEXT +); + +-- use SQLITE R* TREE Module to make queries on timespans effecient (see http://www.sqlite.org/rtree.html) +CREATE VIRTUAL TABLE ranges USING rtree( + id, + begin, end +); + +CREATE TABLE Transactions( + ID INTEGER, + Range INTEGER, + Address INTEGER, + Burstlength INTEGER, + TThread INTEGER, + TChannel INTEGER, + TRank INTEGER, + TBankgroup INTEGER, + TBank INTEGER, + TRow INTEGER, + TColumn INTEGER, + DataStrobeBegin INTEGER, + DataStrobeEnd INTEGER, + TimeOfGeneration INTEGER, + Command TEXT + ); + +CREATE INDEX ranges_index ON Transactions(Range); +CREATE INDEX "phasesTransactions" ON "Phases" ("Transact" ASC); +CREATE INDEX "messageTimes" ON "DebugMessages" ("Time" ASC); diff --git a/DRAMSys/tests/lpddr4/simulations/lpddr4-example.json b/DRAMSys/tests/lpddr4/simulations/lpddr4-example.json new file mode 100644 index 00000000..30211e69 --- /dev/null +++ b/DRAMSys/tests/lpddr4/simulations/lpddr4-example.json @@ -0,0 +1,16 @@ +{ + "simulation": { + "addressmapping": "am_lpddr4_8Gbx16_brc.json", + "mcconfig": "fifo.json", + "memspec": "JEDEC_8Gb_LPDDR4-3200_16bit.json", + "simconfig": "lpddr4.json", + "simulationid": "lpddr4-example", + "thermalconfig": "config.json", + "tracesetup": [ + { + "clkMhz": 1600, + "name": "trace_lpddr4.stl" + } + ] + } +} From a3592e15ba6646c4c149c758505d59f771033650 Mon Sep 17 00:00:00 2001 From: scorrea Date: Mon, 15 Jun 2020 18:24:16 +0200 Subject: [PATCH 02/34] Nr of channel and devices per DIMM at memspec file --- DRAMSys/library/src/common/AddressDecoder.cpp | 4 +- .../src/configuration/Configuration.cpp | 17 +--- .../library/src/configuration/Configuration.h | 2 - .../src/configuration/memspec/MemSpec.cpp | 4 + .../src/configuration/memspec/MemSpec.h | 2 + DRAMSys/library/src/controller/ControllerIF.h | 2 +- DRAMSys/library/src/simulation/Arbiter.cpp | 4 +- DRAMSys/library/src/simulation/DRAMSys.cpp | 6 +- .../src/simulation/DRAMSysRecordable.cpp | 8 +- DRAMSys/library/src/simulation/dram/Dram.cpp | 4 +- .../src/simulation/dram/DramRecordable.cpp | 8 +- ..._ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json | 51 ++++++++++ .../configs/mcconfigs/fr_fcfs_grp.json | 12 +++ .../MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json | 62 ++++++++++++ .../configs/simulator/ddr3.json | 19 ++++ .../configs/thermalsim/config.json | 15 +++ .../configs/thermalsim/core.flp | 45 +++++++++ .../configs/thermalsim/mem.flp | 16 ++++ .../configs/thermalsim/powerInfo.json | 20 ++++ .../configs/thermalsim/stack.stk | 49 ++++++++++ .../scripts/createTraceDB.sql | 94 +++++++++++++++++++ .../simulations/ddr3-example.json | 16 ++++ 22 files changed, 427 insertions(+), 33 deletions(-) create mode 100644 DRAMSys/tests/ddr3_parametersAtMemspec/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json create mode 100644 DRAMSys/tests/ddr3_parametersAtMemspec/configs/mcconfigs/fr_fcfs_grp.json create mode 100644 DRAMSys/tests/ddr3_parametersAtMemspec/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json create mode 100644 DRAMSys/tests/ddr3_parametersAtMemspec/configs/simulator/ddr3.json create mode 100644 DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/config.json create mode 100755 DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/core.flp create mode 100755 DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/mem.flp create mode 100644 DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/powerInfo.json create mode 100755 DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/stack.stk create mode 100644 DRAMSys/tests/ddr3_parametersAtMemspec/scripts/createTraceDB.sql create mode 100644 DRAMSys/tests/ddr3_parametersAtMemspec/simulations/ddr3-example.json diff --git a/DRAMSys/library/src/common/AddressDecoder.cpp b/DRAMSys/library/src/common/AddressDecoder.cpp index b454cec6..02980d4f 100644 --- a/DRAMSys/library/src/common/AddressDecoder.cpp +++ b/DRAMSys/library/src/common/AddressDecoder.cpp @@ -143,10 +143,10 @@ AddressDecoder::AddressDecoder(std::string pathToAddressMapping) Configuration &config = Configuration::getInstance(); MemSpec *memSpec = config.memSpec; - if (config.numberOfMemChannels != channels || memSpec->numberOfRanks != ranks + if (memSpec->numberOfMemChannels != channels || memSpec->numberOfRanks != ranks || memSpec->numberOfBankGroups != bankgroups || memSpec->numberOfBanks != banks || memSpec->numberOfRows != rows || memSpec->numberOfColumns != columns - || config.numberOfDevicesOnDIMM * memSpec->bitWidth != bytes * 8) + || memSpec->numberOfDevicesOnDIMM * memSpec->bitWidth != bytes * 8) SC_REPORT_FATAL("AddressDecoder", "Memspec and address mapping do not match"); } diff --git a/DRAMSys/library/src/configuration/Configuration.cpp b/DRAMSys/library/src/configuration/Configuration.cpp index 3f8462ba..921c8c5c 100644 --- a/DRAMSys/library/src/configuration/Configuration.cpp +++ b/DRAMSys/library/src/configuration/Configuration.cpp @@ -121,20 +121,10 @@ void Configuration::setParameter(std::string name, nlohmann::json value) } else if (name == "Debug") debug = value; - else if (name == "NumberOfMemChannels") - numberOfMemChannels = value; else if (name == "ThermalSimulation") thermalSimulation = value; else if (name == "SimulationProgressBar") simulationProgressBar = value; - else if (name == "NumberOfDevicesOnDIMM") - { - numberOfDevicesOnDIMM = value; - if (numberOfDevicesOnDIMM == 0) - SC_REPORT_FATAL("Configuration", - ("Invalid value for parameter " + name + - ". This parameter must be at least one.").c_str()); - } else if (name == "AddressOffset") { #ifdef DRAMSYS_GEM5 @@ -209,12 +199,13 @@ std::uint64_t Configuration::getSimMemSizeInBytes() std::uint64_t rows = memSpec->numberOfRows; std::uint64_t columns = memSpec->numberOfColumns; std::uint64_t bitWidth = memSpec->bitWidth; + std::uint64_t devicesOnDIMM = memSpec->numberOfDevicesOnDIMM; // 2. Calculate size of one DRAM chip in bits std::uint64_t chipBitSize = banks * rows * columns * bitWidth; // 3. Calculate size of one DRAM chip in bytes std::uint64_t chipSize = chipBitSize / 8; // 4. Total memory size in Bytes of one DIMM (with only support of 1 rank on a DIMM) - std::uint64_t memorySize = chipSize * numberOfDevicesOnDIMM; + std::uint64_t memorySize = chipSize * memSpec->numberOfDevicesOnDIMM; std::cout << headline << std::endl; std::cout << "Per Channel Configuration:" << std::endl << std::endl; @@ -228,7 +219,7 @@ std::uint64_t Configuration::getSimMemSizeInBytes() std::cout << " Chip data bus width: " << bitWidth << std::endl; std::cout << " Chip size in bits: " << chipBitSize << std::endl; std::cout << " Chip Size in bytes: " << chipSize << std::endl; - std::cout << " Devices/Chips on DIMM: " << numberOfDevicesOnDIMM << std::endl; + std::cout << " Devices/Chips on DIMM: " << devicesOnDIMM << std::endl; std::cout << std::endl; assert(memorySize > 0); @@ -241,7 +232,7 @@ std::uint64_t Configuration::getSimMemSizeInBytes() // The bus width is given in bits, e.g., 64-bit data bus, 128-bit data bus, etc. unsigned int Configuration::getDataBusWidth() { - return memSpec->bitWidth * numberOfDevicesOnDIMM; + return memSpec->bitWidth * memSpec->numberOfDevicesOnDIMM; } // Returns the number of bytes transfered in a burst diff --git a/DRAMSys/library/src/configuration/Configuration.h b/DRAMSys/library/src/configuration/Configuration.h index af0ffff9..0f850baa 100644 --- a/DRAMSys/library/src/configuration/Configuration.h +++ b/DRAMSys/library/src/configuration/Configuration.h @@ -88,10 +88,8 @@ public: bool enableWindowing = false; unsigned int windowSize = 1000; bool debug = false; - unsigned int numberOfMemChannels = 1; bool thermalSimulation = false; bool simulationProgressBar = false; - unsigned int numberOfDevicesOnDIMM = 8; bool checkTLM2Protocol = false; std::string ECCMode = "Disabled"; ECCBaseClass *pECC = nullptr; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp index 3022440c..3d7984f0 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp @@ -58,6 +58,10 @@ MemSpec::MemSpec(json &memspec, unsigned numberOfRanks, unsigned banksPerRank, dataRate(parseUint(memspec["memarchitecturespec"]["dataRate"],"dataRate")), bitWidth(parseUint(memspec["memarchitecturespec"]["width"],"width")), fCKMHz(parseUdouble(memspec["memtimingspec"]["clkMhz"], "clkMhz")), + numberOfDevicesOnDIMM(parseUint(memspec["memarchitecturespec"]["NumberOfDevicesOnDIMM"], + "numberOfDevicesOnDIMM")), + numberOfMemChannels(parseUint(memspec["memarchitecturespec"]["NumberOfMemChannels"], + "NumberOfMemChannels")), tCK(sc_time(1.0 / fCKMHz, SC_US)), burstDuration(tCK * (burstLength / dataRate)), memoryId(parseString(memspec["memoryId"], "memoryId")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h index 37185107..afa311e4 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -59,6 +59,8 @@ public: unsigned burstLength; unsigned dataRate; unsigned bitWidth; + unsigned int numberOfDevicesOnDIMM; + unsigned int numberOfMemChannels; // Clock double fCKMHz; diff --git a/DRAMSys/library/src/controller/ControllerIF.h b/DRAMSys/library/src/controller/ControllerIF.h index fbcf969f..965697c2 100644 --- a/DRAMSys/library/src/controller/ControllerIF.h +++ b/DRAMSys/library/src/controller/ControllerIF.h @@ -35,7 +35,7 @@ public: // BusWidth e.g. 8 or 64 * Configuration::getInstance().memSpec->bitWidth // Number of devices on a DIMM e.g. 8 - * Configuration::getInstance().numberOfDevicesOnDIMM ) / ( 1024 ); + * Configuration::getInstance().memSpec->numberOfDevicesOnDIMM ) / ( 1024 ); std::cout << name() << std::string(" Total Time: ") << sc_time_stamp().to_string() diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp index 098c6013..6b6c061b 100644 --- a/DRAMSys/library/src/simulation/Arbiter.cpp +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -49,7 +49,7 @@ Arbiter::Arbiter(sc_module_name name, std::string pathToAddressMapping) : // Anytime an transaction comes from a memory unity to the arbiter the "bw" callback is called. iSocket.register_nb_transport_bw(this, &Arbiter::nb_transport_bw); - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; ++i) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; ++i) { channelIsFree.push_back(true); pendingRequests.push_back(std::queue()); @@ -130,7 +130,7 @@ void Arbiter::peqCallback(tlm_generic_payload &payload, const tlm_phase &phase) // Check the valid range of thread ID and channel Id // TODO: thread ID not checked - assert(channelId < Configuration::getInstance().numberOfMemChannels); + assert(channelId < Configuration::getInstance().memSpec->numberOfMemChannels); // Phases initiated by the intiator side from arbiter's point of view (devices performing memory requests to the arbiter) if (phase == BEGIN_REQ) diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index b210438d..7a9d8b8f 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -192,7 +192,7 @@ void DRAMSys::instantiateModules(const std::string &pathToResources, // Create controllers and DRAMs std::string memoryType = Configuration::getInstance().memSpec->memoryType; - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++) { std::string str = "controller" + std::to_string(i); @@ -251,7 +251,7 @@ void DRAMSys::bindSockets() if (Configuration::getInstance().checkTLM2Protocol) { - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++) { arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket); controllersTlmCheckers[i]->initiator_socket.bind(controllers[i]->tSocket); @@ -260,7 +260,7 @@ void DRAMSys::bindSockets() } else { - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++) { arbiter->iSocket.bind(controllers[i]->tSocket); controllers[i]->iSocket.bind(drams[i]->tSocket); diff --git a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp index 60e4dbd9..b55180a5 100644 --- a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp +++ b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp @@ -91,7 +91,7 @@ void DRAMSysRecordable::setupTlmRecorders(const std::string &traceName, const std::string &pathToResources) { // Create TLM Recorders, one per channel. - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++) { std::string sqlScriptURI = pathToResources + std::string("scripts/createTraceDB.sql"); @@ -140,7 +140,7 @@ void DRAMSysRecordable::instantiateModules(const std::string &traceName, // Create controllers and DRAMs std::string memoryType = Configuration::getInstance().memSpec->memoryType; - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++) { std::string str = "controller" + std::to_string(i); @@ -199,7 +199,7 @@ void DRAMSysRecordable::bindSockets() if (Configuration::getInstance().checkTLM2Protocol) { - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++) { arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket); controllersTlmCheckers[i]->initiator_socket.bind(controllers[i]->tSocket); @@ -208,7 +208,7 @@ void DRAMSysRecordable::bindSockets() } else { - for (size_t i = 0; i < Configuration::getInstance().numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++) { arbiter->iSocket.bind(controllers[i]->tSocket); controllers[i]->iSocket.bind(drams[i]->tSocket); diff --git a/DRAMSys/library/src/simulation/dram/Dram.cpp b/DRAMSys/library/src/simulation/dram/Dram.cpp index 16a76f98..845cbfbe 100644 --- a/DRAMSys/library/src/simulation/dram/Dram.cpp +++ b/DRAMSys/library/src/simulation/dram/Dram.cpp @@ -129,14 +129,14 @@ void Dram::reportPower() std::cout << name() << std::string(" Total Energy: ") << std::fixed << std::setprecision( 2 ) << DRAMPower->getEnergy().total_energy - * Configuration::getInstance().numberOfDevicesOnDIMM + * Configuration::getInstance().memSpec->numberOfDevicesOnDIMM << std::string(" pJ") << std::endl; std::cout << name() << std::string(" Average Power: ") << std::fixed << std::setprecision( 2 ) << DRAMPower->getPower().average_power - * Configuration::getInstance().numberOfDevicesOnDIMM + * Configuration::getInstance().memSpec->numberOfDevicesOnDIMM << std::string(" mW") << std::endl; } } diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp index c2319ddb..96f2ddc2 100644 --- a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp @@ -67,7 +67,7 @@ void DramRecordable::reportPower() BaseDram::reportPower(); tlmRecorder->recordPower(sc_time_stamp().to_seconds(), this->DRAMPower->getPower().window_average_power - * Configuration::getInstance().numberOfDevicesOnDIMM); + * Configuration::getInstance().memSpec->numberOfDevicesOnDIMM); } template @@ -132,15 +132,15 @@ void DramRecordable::powerWindow() // Store the time (in seconds) and the current average power (in mW) into the database tlmRecorder->recordPower(sc_time_stamp().to_seconds(), this->DRAMPower->getPower().window_average_power - * Configuration::getInstance().numberOfDevicesOnDIMM); + * Configuration::getInstance().memSpec->numberOfDevicesOnDIMM); // Here considering that DRAMPower provides the energy in pJ and the power in mW PRINTDEBUGMESSAGE(this->name(), std::string("\tWindow Energy: \t") + std::to_string( this->DRAMPower->getEnergy().window_energy * - Configuration::getInstance().numberOfDevicesOnDIMM) + std::string("\t[pJ]")); + Configuration::getInstance().memSpec->numberOfDevicesOnDIMM) + std::string("\t[pJ]")); PRINTDEBUGMESSAGE(this->name(), std::string("\tWindow Average Power: \t") + std::to_string( this->DRAMPower->getPower().window_average_power * - Configuration::getInstance().numberOfDevicesOnDIMM) + std::string("\t[mW]")); + Configuration::getInstance().memSpec->numberOfDevicesOnDIMM) + std::string("\t[mW]")); } while (true); } diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json new file mode 100644 index 00000000..c82926c9 --- /dev/null +++ b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json @@ -0,0 +1,51 @@ +{ + "CONGEN": { + "XOR":[ + { + "FIRST":13, + "SECOND":16 + } + ], + "BANK_BIT": [ + 13, + 14, + 15 + ], + "BYTE_BIT": [ + 0, + 1, + 2 + ], + "COLUMN_BIT": [ + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12 + ], + "ROW_BIT": [ + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29 + ], + "RANK_BIT": [ + 30 + ] + } +} diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/mcconfigs/fr_fcfs_grp.json b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/mcconfigs/fr_fcfs_grp.json new file mode 100644 index 00000000..4ac02e30 --- /dev/null +++ b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/mcconfigs/fr_fcfs_grp.json @@ -0,0 +1,12 @@ +{"mcconfig": + {"PagePolicy": "Open", + "Scheduler": "FrFcfsGrp", + "RequestBufferSize": 8, + "CmdMux": "Oldest", + "RespQueue": "Fifo", + "RefreshPolicy": "Rankwise", + "RefreshMode": 1, + "RefreshMaxPostponed": 0, + "RefreshMaxPulledin": 0, + "PowerDownPolicy": "Staggered", + "PowerDownTimeout": 100}} diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json new file mode 100644 index 00000000..d842bda2 --- /dev/null +++ b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json @@ -0,0 +1,62 @@ +{ + "memspec": { + "memarchitecturespec": { + "burstLength": 8, + "dataRate": 2, + "nbrOfBanks": 8, + "nbrOfColumns": 1024, + "nbrOfRanks": 2, + "nbrOfRows": 16384, + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 + }, + "memoryId": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM", + "memoryType": "DDR3", + "mempowerspec": { + "idd0": 720.0, + "idd2n": 400.0, + "idd2p0": 80.0, + "idd2p1": 200.0, + "idd3n": 440.0, + "idd3p0": 240.0, + "idd3p1": 240.0, + "idd4r": 1200.0, + "idd4w": 1200.0, + "idd5": 1760.0, + "idd6": 48.0, + "vdd": 1.5 + }, + "memtimingspec": { + "AL": 0, + "CCD": 4, + "CKE": 3, + "CKESR": 4, + "CL": 7, + "DQSCK": 0, + "FAW": 20, + "RAS": 20, + "RC": 27, + "RCD": 7, + "REFI": 4160, + "RFC": 59, + "RL": 7, + "RP": 7, + "RRD": 4, + "RTP": 4, + "WL": 6, + "WR": 8, + "WTR": 4, + "XP": 4, + "XPDLL": 13, + "XS": 64, + "XSDLL": 512, + "clkMhz": 533, + + "ACTPDEN": 1, + "PRPDEN": 1, + "REFPDEN": 1, + "RTRS": 1 + } + } +} diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/simulator/ddr3.json b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/simulator/ddr3.json new file mode 100644 index 00000000..99ccdb45 --- /dev/null +++ b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/simulator/ddr3.json @@ -0,0 +1,19 @@ +{ + "simconfig": { + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, + "ECCControllerMode": "Disabled", + "EnableWindowing": false, + "ErrorCSVFile": "", + "ErrorChipSeed": 42, + "PowerAnalysis": false, + "SimulationName": "ddr3", + "SimulationProgressBar": true, + "StoreMode": "NoStorage", + "ThermalSimulation": false, + "UseMalloc": false, + "WindowSize": 1000 + } +} diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/config.json b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/config.json new file mode 100644 index 00000000..b88ed84c --- /dev/null +++ b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/config.json @@ -0,0 +1,15 @@ +{ + "thermalsimconfig": { + "TemperatureScale": "Celsius", + "StaticTemperatureDefaultValue": 89, + "ThermalSimPeriod":100, + "ThermalSimUnit":"us", + "PowerInfoFile": "powerInfo.json", + "IceServerIp": "127.0.0.1", + "IceServerPort": 11880, + "SimPeriodAdjustFactor" : 10, + "NPowStableCyclesToIncreasePeriod": 5, + "GenerateTemperatureMap": true, + "GeneratePowerMap": true + } +} diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/core.flp b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/core.flp new file mode 100755 index 00000000..e85e6801 --- /dev/null +++ b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/core.flp @@ -0,0 +1,45 @@ +CPUs : + + position 0, 0 ; + dimension 2750, 4300 ; + +GPU : + + position 3350, 0 ; + dimension 2750, 4000 ; + +BASEBAND1 : + + position 4250, 4000 ; + dimension 1850, 3300 ; + +BASEBAND2 : + + position 3350, 7300 ; + dimension 2750, 3300 ; + +LLCACHE : + + position 0, 4300 ; + dimension 1900, 3000 ; + +DRAMCTRL1 : + + position 1900, 4300 ; + dimension 850, 3000 ; + +DRAMCTRL2 : + + position 3350, 4000 ; + dimension 900, 3300 ; + +TSVS : + + position 2750, 2300 ; + dimension 600, 6000 ; + +ACELLERATORS : + + position 0, 7300 ; + dimension 2750, 3300 ; + diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/mem.flp b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/mem.flp new file mode 100755 index 00000000..29d02254 --- /dev/null +++ b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/mem.flp @@ -0,0 +1,16 @@ +channel0 : + position 150, 100 ; + dimension 2600, 5200 ; + +channel1 : + position 3350, 100 ; + dimension 2600, 5200 ; + +channel2 : + position 150, 5300 ; + dimension 2600, 5200 ; + +channel3 : + position 3350, 5300 ; + dimension 2600, 5200 ; + diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/powerInfo.json b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/powerInfo.json new file mode 100644 index 00000000..524f690f --- /dev/null +++ b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/powerInfo.json @@ -0,0 +1,20 @@ +{ + "powerInfo": { + "dram_die_channel0": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel1": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel2": { + "init_pow": 0, + "threshold": 1.0 + }, + "dram_die_channel3": { + "init_pow": 0, + "threshold": 1.0 + } + } +} diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/stack.stk b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/stack.stk new file mode 100755 index 00000000..ec74f020 --- /dev/null +++ b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/stack.stk @@ -0,0 +1,49 @@ +material SILICON : + thermal conductivity 1.30e-4 ; + volumetric heat capacity 1.628e-12 ; + +material BEOL : + thermal conductivity 2.25e-6 ; + volumetric heat capacity 2.175e-12 ; + +material COPPER : + thermal conductivity 4.01e-04 ; + volumetric heat capacity 3.37e-12 ; + +top heat sink : + //sink height 1e03, area 100e06, material COPPER ; + //spreader height 0.5e03, area 70e06, material SILICON ; + heat transfer coefficient 1.3e-09 ; + temperature 318.15 ; +dimensions : + chip length 6100, width 10600 ; + cell length 100, width 100 ; + + +layer PCB : + height 10 ; + material BEOL ; + +die DRAM : + layer 58.5 SILICON ; + source 2 SILICON ; + layer 1.5 BEOL ; + layer 58.5 SILICON ; + + +stack: + die DRAM_DIE DRAM floorplan "./mem.flp" ; + layer CONN_TO_PCB PCB ; + +solver: + transient step 0.01, slot 0.05 ; + initial temperature 300.0 ; + +output: + Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot ); + Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot ); + Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot ); + Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot ); + Tmap (DRAM_DIE, "output1.txt", slot) ; + Pmap (DRAM_DIE, "output2.txt", slot) ; + diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/scripts/createTraceDB.sql b/DRAMSys/tests/ddr3_parametersAtMemspec/scripts/createTraceDB.sql new file mode 100644 index 00000000..7a127fac --- /dev/null +++ b/DRAMSys/tests/ddr3_parametersAtMemspec/scripts/createTraceDB.sql @@ -0,0 +1,94 @@ +DROP TABLE IF EXISTS Phases; +DROP TABLE IF EXISTS GeneralInfo; +DROP TABLE IF EXISTS CommandLengths; +DROP TABLE IF EXISTS Comments; +DROP TABLE IF EXISTS ranges; +DROP TABLE IF EXISTS Transactions; +DROP TABLE IF EXISTS DebugMessages; +DROP TABLE IF EXISTS Power; + +CREATE TABLE Phases( + ID INTEGER PRIMARY KEY, + PhaseName TEXT, + PhaseBegin INTEGER, + PhaseEnd INTEGER, + Transact INTEGER +); + +CREATE TABLE GeneralInfo( + NumberOfTransactions INTEGER, + TraceEnd INTEGER, + NumberOfRanks INTEGER, + NumberOfBanks INTEGER, + clk INTEGER, + UnitOfTime TEXT, + MCconfig TEXT, + Memspec TEXT, + Traces TEXT, + WindowSize INTEGER, + FlexibleRefresh INTEGER, + MaxRefBurst INTEGER, + ControllerThread INTEGER +); + +CREATE TABLE CommandLengths( + ACT INTEGER, + PRE INTEGER, + PREA INTEGER, + RD INTEGER, + RDA INTEGER, + WR INTEGER, + WRA INTEGER, + REFA INTEGER, + REFB INTEGER, + PDEA INTEGER, + PDXA INTEGER, + PDEP INTEGER, + PDXP INTEGER, + SREFEN INTEGER, + SREFEX INTEGER +); + +CREATE TABLE Power( + time DOUBLE, + AveragePower DOUBLE +); + + +CREATE TABLE Comments( + Time INTEGER, + Text TEXT +); + +CREATE TABLE DebugMessages( + Time INTEGER, + Message TEXT +); + +-- use SQLITE R* TREE Module to make queries on timespans effecient (see http://www.sqlite.org/rtree.html) +CREATE VIRTUAL TABLE ranges USING rtree( + id, + begin, end +); + +CREATE TABLE Transactions( + ID INTEGER, + Range INTEGER, + Address INTEGER, + Burstlength INTEGER, + TThread INTEGER, + TChannel INTEGER, + TRank INTEGER, + TBankgroup INTEGER, + TBank INTEGER, + TRow INTEGER, + TColumn INTEGER, + DataStrobeBegin INTEGER, + DataStrobeEnd INTEGER, + TimeOfGeneration INTEGER, + Command TEXT + ); + +CREATE INDEX ranges_index ON Transactions(Range); +CREATE INDEX "phasesTransactions" ON "Phases" ("Transact" ASC); +CREATE INDEX "messageTimes" ON "DebugMessages" ("Time" ASC); diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/simulations/ddr3-example.json b/DRAMSys/tests/ddr3_parametersAtMemspec/simulations/ddr3-example.json new file mode 100644 index 00000000..e3d4a4c3 --- /dev/null +++ b/DRAMSys/tests/ddr3_parametersAtMemspec/simulations/ddr3-example.json @@ -0,0 +1,16 @@ +{ + "simulation": { + "addressmapping": "am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json", + "mcconfig": "fr_fcfs_grp.json", + "memspec": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json", + "simconfig": "ddr3.json", + "simulationid": "ddr3-example-dual-rank-json", + "thermalconfig": "config.json", + "tracesetup": [ + { + "clkMhz": 533, + "name": "trace_test2.stl" + } + ] + } +} From 4265ecc3c701c803df45dac19a9c48429b615ab6 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 16 Jun 2020 10:53:43 +0200 Subject: [PATCH 03/34] Adapted memspecs to nbrOfChannels and nbrOfDevicesOnDIMM. --- DRAMSys/library/CMakeLists.txt | 3 +++ DRAMSys/library/src/common/AddressDecoder.cpp | 2 +- .../src/configuration/memspec/MemSpec.cpp | 18 +++++++++--------- .../src/configuration/memspec/MemSpec.h | 10 ++++++---- .../src/configuration/memspec/MemSpecDDR3.cpp | 4 +++- .../src/configuration/memspec/MemSpecDDR4.cpp | 4 +++- .../src/configuration/memspec/MemSpecGDDR5.cpp | 4 +++- .../configuration/memspec/MemSpecGDDR5X.cpp | 4 +++- .../src/configuration/memspec/MemSpecGDDR6.cpp | 4 +++- .../src/configuration/memspec/MemSpecHBM2.cpp | 4 +++- .../configuration/memspec/MemSpecLPDDR4.cpp | 4 +++- .../configuration/memspec/MemSpecWideIO.cpp | 4 +++- .../configuration/memspec/MemSpecWideIO2.cpp | 4 +++- DRAMSys/library/src/simulation/Arbiter.cpp | 4 ++-- DRAMSys/library/src/simulation/DRAMSys.cpp | 6 +++--- .../src/simulation/DRAMSysRecordable.cpp | 8 ++++---- DRAMSys/tests/HBM2/configs/memspecs/HBM2.json | 1 + DRAMSys/tests/HBM2/configs/simulator/hbm2.json | 2 -- .../MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json | 8 +++++++- .../ddr3_multirank/configs/simulator/ddr3.json | 2 -- .../memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json | 4 +++- .../configs/simulator/ddr4.json | 2 -- .../memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json | 4 ++++ .../tests/lpddr4/configs/simulator/lpddr4.json | 2 -- 24 files changed, 70 insertions(+), 42 deletions(-) diff --git a/DRAMSys/library/CMakeLists.txt b/DRAMSys/library/CMakeLists.txt index 0b828857..d15862ed 100644 --- a/DRAMSys/library/CMakeLists.txt +++ b/DRAMSys/library/CMakeLists.txt @@ -172,6 +172,7 @@ add_library(DRAMSysLibrary resources/simulations/lpddr4-example.json resources/simulations/ranktest.json resources/simulations/wideio-example.json + resources/simulations/wideio-thermal.json # Address Mapping Config Files resources/configs/amconfigs/am_ddr3_1Gbx8_p1KB_brc.json @@ -266,9 +267,11 @@ add_library(DRAMSysLibrary resources/configs/simulator/hbm2.json resources/configs/simulator/lpddr4.json resources/configs/simulator/wideio.json + resources/configs/simulator/wideio_thermal.json # Thermal Simulation Config Files resources/configs/thermalsim/config.json + resources/configs/thermalsim/powerInfo.json # Trace Files resources/traces/test_ecc.stl diff --git a/DRAMSys/library/src/common/AddressDecoder.cpp b/DRAMSys/library/src/common/AddressDecoder.cpp index 02980d4f..33e920c9 100644 --- a/DRAMSys/library/src/common/AddressDecoder.cpp +++ b/DRAMSys/library/src/common/AddressDecoder.cpp @@ -143,7 +143,7 @@ AddressDecoder::AddressDecoder(std::string pathToAddressMapping) Configuration &config = Configuration::getInstance(); MemSpec *memSpec = config.memSpec; - if (memSpec->numberOfMemChannels != channels || memSpec->numberOfRanks != ranks + if (memSpec->numberOfChannels != channels || memSpec->numberOfRanks != ranks || memSpec->numberOfBankGroups != bankgroups || memSpec->numberOfBanks != banks || memSpec->numberOfRows != rows || memSpec->numberOfColumns != columns || memSpec->numberOfDevicesOnDIMM * memSpec->bitWidth != bytes * 8) diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp index 3d7984f0..4cae3c73 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp @@ -43,29 +43,29 @@ using namespace tlm; using json = nlohmann::json; -MemSpec::MemSpec(json &memspec, unsigned numberOfRanks, unsigned banksPerRank, +MemSpec::MemSpec(json &memspec, unsigned numberOfChannels, + unsigned numberOfRanks, unsigned banksPerRank, unsigned groupsPerRank, unsigned banksPerGroup, - unsigned numberOfBanks, unsigned numberOfBankGroups) - : numberOfRanks(numberOfRanks), + unsigned numberOfBanks, unsigned numberOfBankGroups, + unsigned numberOfDevicesOnDIMM) + : numberOfChannels(numberOfChannels), + numberOfRanks(numberOfRanks), banksPerRank(banksPerRank), groupsPerRank(groupsPerRank), banksPerGroup(banksPerGroup), numberOfBanks(numberOfBanks), numberOfBankGroups(numberOfBankGroups), + numberOfDevicesOnDIMM(numberOfDevicesOnDIMM), numberOfRows(parseUint(memspec["memarchitecturespec"]["nbrOfRows"],"nbrOfRows")), numberOfColumns(parseUint(memspec["memarchitecturespec"]["nbrOfColumns"],"nbrOfColumns")), burstLength(parseUint(memspec["memarchitecturespec"]["burstLength"],"burstLength")), dataRate(parseUint(memspec["memarchitecturespec"]["dataRate"],"dataRate")), bitWidth(parseUint(memspec["memarchitecturespec"]["width"],"width")), fCKMHz(parseUdouble(memspec["memtimingspec"]["clkMhz"], "clkMhz")), - numberOfDevicesOnDIMM(parseUint(memspec["memarchitecturespec"]["NumberOfDevicesOnDIMM"], - "numberOfDevicesOnDIMM")), - numberOfMemChannels(parseUint(memspec["memarchitecturespec"]["NumberOfMemChannels"], - "NumberOfMemChannels")), tCK(sc_time(1.0 / fCKMHz, SC_US)), - burstDuration(tCK * (burstLength / dataRate)), memoryId(parseString(memspec["memoryId"], "memoryId")), - memoryType(parseString(memspec["memoryType"], "memoryType")) + memoryType(parseString(memspec["memoryType"], "memoryType")), + burstDuration(tCK * (burstLength / dataRate)) { commandLengthInCycles = std::vector(numberOfCommands(), 1); } diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h index afa311e4..785e52d7 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -48,19 +48,19 @@ class MemSpec { public: + unsigned numberOfChannels; unsigned numberOfRanks; unsigned banksPerRank; unsigned groupsPerRank; unsigned banksPerGroup; unsigned numberOfBanks; unsigned numberOfBankGroups; + unsigned numberOfDevicesOnDIMM; unsigned numberOfRows; unsigned numberOfColumns; unsigned burstLength; unsigned dataRate; unsigned bitWidth; - unsigned int numberOfDevicesOnDIMM; - unsigned int numberOfMemChannels; // Clock double fCKMHz; @@ -80,9 +80,11 @@ public: sc_time getCommandLength(Command) const; protected: - MemSpec(nlohmann::json &memspec, unsigned numberOfRanks, unsigned banksPerRank, + MemSpec(nlohmann::json &memspec, unsigned numberOfChannels, + unsigned numberOfRanks, unsigned banksPerRank, unsigned groupsPerRank, unsigned banksPerGroup, - unsigned numberOfBanks, unsigned numberOfBankGroups); + unsigned numberOfBanks, unsigned numberOfBankGroups, + unsigned numberOfDevicesOnDIMM); // Command lengths in cycles on bus, usually one clock cycle std::vector commandLengthInCycles; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp index 387ec6be..52fed95d 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp @@ -40,13 +40,15 @@ using json = nlohmann::json; MemSpecDDR3::MemSpecDDR3(json &memspec) : MemSpec(memspec, + parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"), parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), 1, parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), + parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), + parseUint(memspec["memarchitecturespec"]["nbrOfDevicesOnDIMM"],"nbrOfDevicesOnDIMM")), tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")), tPD (tCKE), tCKESR (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp index 5078ca0e..9e38241e 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp @@ -41,6 +41,7 @@ using json = nlohmann::json; MemSpecDDR4::MemSpecDDR4(json &memspec) : MemSpec(memspec, + parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"), parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"), @@ -49,7 +50,8 @@ MemSpecDDR4::MemSpecDDR4(json &memspec) parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), + * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), + parseUint(memspec["memarchitecturespec"]["nbrOfDevicesOnDIMM"],"nbrOfDevicesOnDIMM")), tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")), tPD (tCKE), tCKESR (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp index 66bd7f7c..0572099a 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp @@ -40,6 +40,7 @@ using json = nlohmann::json; MemSpecGDDR5::MemSpecGDDR5(json &memspec) : MemSpec(memspec, + parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"), parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"), @@ -48,7 +49,8 @@ MemSpecGDDR5::MemSpecGDDR5(json &memspec) parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), + * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), + 1), tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")), tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")), tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp index a2897967..90908bd9 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp @@ -40,6 +40,7 @@ using json = nlohmann::json; MemSpecGDDR5X::MemSpecGDDR5X(json &memspec) : MemSpec(memspec, + parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"), parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"), @@ -48,7 +49,8 @@ MemSpecGDDR5X::MemSpecGDDR5X(json &memspec) parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), + * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), + 1), tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")), tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")), tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp index 636a3351..b9a70d10 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp @@ -40,6 +40,7 @@ using json = nlohmann::json; MemSpecGDDR6::MemSpecGDDR6(json &memspec) : MemSpec(memspec, + parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"), parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"), @@ -48,7 +49,8 @@ MemSpecGDDR6::MemSpecGDDR6(json &memspec) parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), + * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), + 1), tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")), tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")), tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp index c8afaa93..da1d77b1 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp @@ -40,6 +40,7 @@ using json = nlohmann::json; MemSpecHBM2::MemSpecHBM2(json &memspec) : MemSpec(memspec, + parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"), parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"), @@ -48,7 +49,8 @@ MemSpecHBM2::MemSpecHBM2(json &memspec) parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups") - * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), + * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), + 1), tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")), tRC (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")), tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp index c16f9b50..6716744f 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp @@ -40,13 +40,15 @@ using json = nlohmann::json; MemSpecLPDDR4::MemSpecLPDDR4(json &memspec) : MemSpec(memspec, + parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"), parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), 1, parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), + parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), + 1), tREFI (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")), tREFIpb (tCK * parseUint(memspec["memtimingspec"]["REFIPB"], "REFIPB")), tRFCab (tCK * parseUint(memspec["memtimingspec"]["RFCAB"], "RFCAB")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp index ecbcb202..e4ccfadb 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp @@ -40,13 +40,15 @@ using json = nlohmann::json; MemSpecWideIO::MemSpecWideIO(json &memspec) : MemSpec(memspec, + parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"), parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), 1, parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), + parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), + 1), tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")), tCKESR (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")), tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")), diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp index 91e27078..2f07fdcd 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp @@ -40,13 +40,15 @@ using json = nlohmann::json; MemSpecWideIO2::MemSpecWideIO2(json &memspec) : MemSpec(memspec, + parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"), parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), 1, parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"), parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks") * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), - parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks")), + parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"), + 1), tDQSCK (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")), tDQSS (tCK * parseUint(memspec["memtimingspec"]["DQSS"], "DQSS")), tCKE (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")), diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp index 6b6c061b..6a74396d 100644 --- a/DRAMSys/library/src/simulation/Arbiter.cpp +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -49,7 +49,7 @@ Arbiter::Arbiter(sc_module_name name, std::string pathToAddressMapping) : // Anytime an transaction comes from a memory unity to the arbiter the "bw" callback is called. iSocket.register_nb_transport_bw(this, &Arbiter::nb_transport_bw); - for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; ++i) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; ++i) { channelIsFree.push_back(true); pendingRequests.push_back(std::queue()); @@ -130,7 +130,7 @@ void Arbiter::peqCallback(tlm_generic_payload &payload, const tlm_phase &phase) // Check the valid range of thread ID and channel Id // TODO: thread ID not checked - assert(channelId < Configuration::getInstance().memSpec->numberOfMemChannels); + assert(channelId < Configuration::getInstance().memSpec->numberOfChannels); // Phases initiated by the intiator side from arbiter's point of view (devices performing memory requests to the arbiter) if (phase == BEGIN_REQ) diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index 7a9d8b8f..5991560b 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -192,7 +192,7 @@ void DRAMSys::instantiateModules(const std::string &pathToResources, // Create controllers and DRAMs std::string memoryType = Configuration::getInstance().memSpec->memoryType; - for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++) { std::string str = "controller" + std::to_string(i); @@ -251,7 +251,7 @@ void DRAMSys::bindSockets() if (Configuration::getInstance().checkTLM2Protocol) { - for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++) { arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket); controllersTlmCheckers[i]->initiator_socket.bind(controllers[i]->tSocket); @@ -260,7 +260,7 @@ void DRAMSys::bindSockets() } else { - for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++) { arbiter->iSocket.bind(controllers[i]->tSocket); controllers[i]->iSocket.bind(drams[i]->tSocket); diff --git a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp index b55180a5..c799d8c1 100644 --- a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp +++ b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp @@ -91,7 +91,7 @@ void DRAMSysRecordable::setupTlmRecorders(const std::string &traceName, const std::string &pathToResources) { // Create TLM Recorders, one per channel. - for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++) { std::string sqlScriptURI = pathToResources + std::string("scripts/createTraceDB.sql"); @@ -140,7 +140,7 @@ void DRAMSysRecordable::instantiateModules(const std::string &traceName, // Create controllers and DRAMs std::string memoryType = Configuration::getInstance().memSpec->memoryType; - for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++) { std::string str = "controller" + std::to_string(i); @@ -199,7 +199,7 @@ void DRAMSysRecordable::bindSockets() if (Configuration::getInstance().checkTLM2Protocol) { - for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++) { arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket); controllersTlmCheckers[i]->initiator_socket.bind(controllers[i]->tSocket); @@ -208,7 +208,7 @@ void DRAMSysRecordable::bindSockets() } else { - for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfMemChannels; i++) + for (size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++) { arbiter->iSocket.bind(controllers[i]->tSocket); controllers[i]->iSocket.bind(drams[i]->tSocket); diff --git a/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json b/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json index efa8ee9e..7cf4004b 100644 --- a/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json +++ b/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json @@ -7,6 +7,7 @@ "nbrOfBanks": 16, "nbrOfColumns": 128, "nbrOfRanks": 2, + "nbrOfChannels": 1, "nbrOfRows": 32768, "width": 64 }, diff --git a/DRAMSys/tests/HBM2/configs/simulator/hbm2.json b/DRAMSys/tests/HBM2/configs/simulator/hbm2.json index 9589611f..e6affb0b 100644 --- a/DRAMSys/tests/HBM2/configs/simulator/hbm2.json +++ b/DRAMSys/tests/HBM2/configs/simulator/hbm2.json @@ -8,8 +8,6 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1, "PowerAnalysis": false, "SimulationName": "hbm2", "SimulationProgressBar": true, diff --git a/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json b/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json index 13d9fef5..08e13043 100644 --- a/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json +++ b/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json @@ -6,8 +6,10 @@ "nbrOfBanks": 8, "nbrOfColumns": 1024, "nbrOfRanks": 2, + "nbrOfChannels": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "nbrOfDevicesOnDIMM": 8 }, "memoryId": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM", "memoryType": "DDR3", @@ -49,6 +51,10 @@ "XPDLL": 13, "XS": 64, "XSDLL": 512, + "ACTPDEN": 1, + "PRPDEN": 1, + "REFPDEN": 1, + "RTRS": 1, "clkMhz": 533 } } diff --git a/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json b/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json index 4e9faadc..99ccdb45 100644 --- a/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json +++ b/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json @@ -8,8 +8,6 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, "PowerAnalysis": false, "SimulationName": "ddr3", "SimulationProgressBar": true, diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json b/DRAMSys/tests/ddr4_bankgroups/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json index 11700aaf..adbfd117 100644 --- a/DRAMSys/tests/ddr4_bankgroups/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json +++ b/DRAMSys/tests/ddr4_bankgroups/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json @@ -7,8 +7,10 @@ "nbrOfBanks": 16, "nbrOfColumns": 1024, "nbrOfRanks": 1, + "nbrOfChannels": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "nbrOfDevicesOnDIMM": 8 }, "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A", "memoryType": "DDR4", diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/simulator/ddr4.json b/DRAMSys/tests/ddr4_bankgroups/configs/simulator/ddr4.json index 8e62e680..81b72d43 100644 --- a/DRAMSys/tests/ddr4_bankgroups/configs/simulator/ddr4.json +++ b/DRAMSys/tests/ddr4_bankgroups/configs/simulator/ddr4.json @@ -8,8 +8,6 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, "PowerAnalysis": false, "SimulationName": "ddr4", "SimulationProgressBar": true, diff --git a/DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json b/DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json index 97a8cc3e..223f064d 100644 --- a/DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json +++ b/DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json @@ -6,6 +6,7 @@ "nbrOfBanks": 8, "nbrOfColumns": 1024, "nbrOfRanks": 1, + "nbrOfChannels": 1, "nbrOfRows": 65536, "width": 16 }, @@ -30,6 +31,8 @@ "RL": 28, "RPAB": 34, "RPPB": 29, + "RCAB": 102, + "RCPB": 97, "RPST": 0, "RRD": 16, "RTP": 12, @@ -40,6 +43,7 @@ "WTR": 16, "XP": 12, "XSR": 460, + "RTRS": 1, "clkMhz": 1600 } } diff --git a/DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json b/DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json index fd8fe855..0fae8a52 100644 --- a/DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json +++ b/DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json @@ -8,8 +8,6 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1, "PowerAnalysis": false, "SimulationName": "lpddr4", "SimulationProgressBar": true, From b2b70d3771a412bde69fab0651613824bb894b88 Mon Sep 17 00:00:00 2001 From: scorrea Date: Tue, 16 Jun 2020 11:25:49 +0200 Subject: [PATCH 04/34] ci and test files modified/some old tests deleted --- .gitlab-ci_old.yml | 56 +++++++++++ DRAMSys/tests/DDR3/ci.yml | 83 ---------------- .../am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml | 34 ------- .../DDR3/configs/mcconfigs/fifoStrict.xml | 20 ---- .../tests/DDR3/configs/mcconfigs/fr_fcfs.xml | 20 ---- .../memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml | 55 ----------- .../simulator/ddr3-protocol_checker.xml | 29 ------ DRAMSys/tests/DDR3/configs/simulator/ddr3.xml | 29 ------ .../tests/DDR3/configs/thermalsim/config.xml | 14 --- .../DDR3/configs/thermalsim/powerInfo.xml | 8 -- .../tests/DDR3/simulations/ddr3-example.xml | 25 ----- .../tests/DDR3/simulations/ddr3-fr_fcfs.xml | 25 ----- .../simulations/ddr3-protocol_checker.xml | 25 ----- DRAMSys/tests/DDR4/ci.yml | 29 ++++++ .../am_ddr4_8x4Gbx8_dimm_p1KB_brc.json | 0 .../configs/mcconfigs/fr_fcfs.json | 0 .../memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json | 6 +- .../configs/simulator/ddr4.json | 4 +- .../configs/thermalsim/config.json | 0 .../configs/thermalsim/core.flp | 0 .../{DDR3 => DDR4}/configs/thermalsim/mem.flp | 0 .../configs/thermalsim/powerInfo.json | 0 .../configs/thermalsim/stack.stk | 0 .../{DDR3 => DDR4}/scripts/createTraceDB.sql | 0 .../simulations/ddr4-example.json | 0 DRAMSys/tests/HBM2/ci.yml | 29 ++++++ DRAMSys/tests/HBM2/configs/memspecs/HBM2.json | 6 +- .../tests/HBM2/configs/simulator/hbm2.json | 4 +- DRAMSys/tests/WIDEIO/ci.yml | 40 -------- .../configs/amconfigs/am_wideio_brc.xml | 8 -- .../configs/amconfigs/am_wideio_rbc.xml | 8 -- .../WIDEIO/configs/mcconfigs/fifoStrict.xml | 50 ---------- .../tests/WIDEIO/configs/memspecs/wideio.xml | 61 ------------ .../tests/WIDEIO/configs/simulator/wideio.xml | 24 ----- .../WIDEIO/configs/thermalsim/config.xml | 14 --- .../tests/WIDEIO/configs/thermalsim/core.flp | 45 --------- .../tests/WIDEIO/configs/thermalsim/mem.flp | 16 ---- .../WIDEIO/configs/thermalsim/powerInfo.xml | 8 -- .../tests/WIDEIO/configs/thermalsim/stack.stk | 49 ---------- .../tests/WIDEIO/scripts/createTraceDB.sql | 94 ------------------- .../WIDEIO/simulations/wideio-example.xml | 24 ----- DRAMSys/tests/WIDEIO/traces/generator.pl | 75 --------------- DRAMSys/tests/ddr3_multirank/ci.yml | 29 ++++++ .../MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json | 11 ++- .../configs/simulator/ddr3.json | 2 - .../simulations/ddr3-example.json | 2 +- ..._ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json | 51 ---------- .../configs/mcconfigs/fr_fcfs_grp.json | 12 --- .../MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json | 62 ------------ .../configs/simulator/ddr3.json | 19 ---- .../configs/thermalsim/core.flp | 45 --------- .../configs/thermalsim/mem.flp | 16 ---- .../configs/thermalsim/stack.stk | 49 ---------- .../scripts/createTraceDB.sql | 94 ------------------- .../simulations/ddr3-example.json | 16 ---- .../configs/thermalsim/config.json | 15 --- .../configs/thermalsim/core.flp | 45 --------- .../configs/thermalsim/mem.flp | 16 ---- .../configs/thermalsim/powerInfo.json | 20 ---- .../configs/thermalsim/stack.stk | 49 ---------- .../ddr4_bankgroups/scripts/createTraceDB.sql | 94 ------------------- DRAMSys/tests/lpddr4/ci.yml | 28 ++++++ .../memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json | 10 +- .../lpddr4/configs/simulator/lpddr4.json | 4 +- 64 files changed, 200 insertions(+), 1506 deletions(-) create mode 100644 .gitlab-ci_old.yml delete mode 100644 DRAMSys/tests/DDR3/ci.yml delete mode 100644 DRAMSys/tests/DDR3/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml delete mode 100644 DRAMSys/tests/DDR3/configs/mcconfigs/fifoStrict.xml delete mode 100644 DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml delete mode 100644 DRAMSys/tests/DDR3/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml delete mode 100644 DRAMSys/tests/DDR3/configs/simulator/ddr3-protocol_checker.xml delete mode 100644 DRAMSys/tests/DDR3/configs/simulator/ddr3.xml delete mode 100644 DRAMSys/tests/DDR3/configs/thermalsim/config.xml delete mode 100644 DRAMSys/tests/DDR3/configs/thermalsim/powerInfo.xml delete mode 100644 DRAMSys/tests/DDR3/simulations/ddr3-example.xml delete mode 100644 DRAMSys/tests/DDR3/simulations/ddr3-fr_fcfs.xml delete mode 100644 DRAMSys/tests/DDR3/simulations/ddr3-protocol_checker.xml create mode 100644 DRAMSys/tests/DDR4/ci.yml rename DRAMSys/tests/{ddr4_bankgroups => DDR4}/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json (100%) rename DRAMSys/tests/{ddr4_bankgroups => DDR4}/configs/mcconfigs/fr_fcfs.json (100%) rename DRAMSys/tests/{ddr4_bankgroups => DDR4}/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json (94%) rename DRAMSys/tests/{ddr4_bankgroups => DDR4}/configs/simulator/ddr4.json (87%) rename DRAMSys/tests/{ddr3_parametersAtMemspec => DDR4}/configs/thermalsim/config.json (100%) rename DRAMSys/tests/{DDR3 => DDR4}/configs/thermalsim/core.flp (100%) rename DRAMSys/tests/{DDR3 => DDR4}/configs/thermalsim/mem.flp (100%) rename DRAMSys/tests/{ddr3_parametersAtMemspec => DDR4}/configs/thermalsim/powerInfo.json (100%) rename DRAMSys/tests/{DDR3 => DDR4}/configs/thermalsim/stack.stk (100%) rename DRAMSys/tests/{DDR3 => DDR4}/scripts/createTraceDB.sql (100%) rename DRAMSys/tests/{ddr4_bankgroups => DDR4}/simulations/ddr4-example.json (100%) create mode 100644 DRAMSys/tests/HBM2/ci.yml delete mode 100644 DRAMSys/tests/WIDEIO/ci.yml delete mode 100755 DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_brc.xml delete mode 100755 DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_rbc.xml delete mode 100644 DRAMSys/tests/WIDEIO/configs/mcconfigs/fifoStrict.xml delete mode 100644 DRAMSys/tests/WIDEIO/configs/memspecs/wideio.xml delete mode 100644 DRAMSys/tests/WIDEIO/configs/simulator/wideio.xml delete mode 100644 DRAMSys/tests/WIDEIO/configs/thermalsim/config.xml delete mode 100755 DRAMSys/tests/WIDEIO/configs/thermalsim/core.flp delete mode 100755 DRAMSys/tests/WIDEIO/configs/thermalsim/mem.flp delete mode 100644 DRAMSys/tests/WIDEIO/configs/thermalsim/powerInfo.xml delete mode 100755 DRAMSys/tests/WIDEIO/configs/thermalsim/stack.stk delete mode 100644 DRAMSys/tests/WIDEIO/scripts/createTraceDB.sql delete mode 100644 DRAMSys/tests/WIDEIO/simulations/wideio-example.xml delete mode 100644 DRAMSys/tests/WIDEIO/traces/generator.pl create mode 100644 DRAMSys/tests/ddr3_multirank/ci.yml delete mode 100644 DRAMSys/tests/ddr3_parametersAtMemspec/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json delete mode 100644 DRAMSys/tests/ddr3_parametersAtMemspec/configs/mcconfigs/fr_fcfs_grp.json delete mode 100644 DRAMSys/tests/ddr3_parametersAtMemspec/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json delete mode 100644 DRAMSys/tests/ddr3_parametersAtMemspec/configs/simulator/ddr3.json delete mode 100755 DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/core.flp delete mode 100755 DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/mem.flp delete mode 100755 DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/stack.stk delete mode 100644 DRAMSys/tests/ddr3_parametersAtMemspec/scripts/createTraceDB.sql delete mode 100644 DRAMSys/tests/ddr3_parametersAtMemspec/simulations/ddr3-example.json delete mode 100644 DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/config.json delete mode 100755 DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/core.flp delete mode 100755 DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/mem.flp delete mode 100644 DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/powerInfo.json delete mode 100755 DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/stack.stk delete mode 100644 DRAMSys/tests/ddr4_bankgroups/scripts/createTraceDB.sql create mode 100644 DRAMSys/tests/lpddr4/ci.yml diff --git a/.gitlab-ci_old.yml b/.gitlab-ci_old.yml new file mode 100644 index 00000000..9011e4ab --- /dev/null +++ b/.gitlab-ci_old.yml @@ -0,0 +1,56 @@ +# vim: set ts=4 sw=4 expandtab: +image: gcc + +variables: + GIT_STRATEGY: clone + +stages: + - build + - dramsys-gem5-build + - WIDEIO + - DDR3 + - Coverage + +build: + stage: build + script: + - git submodule sync + - git submodule update --init --recursive + - rm -rf build + - mkdir -p build + - cd build + - cmake ../DRAMSys + - make -j16 + - find . -name "*.o" -type f -delete + - rm -rf ${CI_PROJECT_DIR}/coverage + - mkdir -p ${CI_PROJECT_DIR}/coverage + + cache: + key: build + paths: + - build/ + policy: push + + artifacts: + paths: + - coverage/ + +coverage: + stage: Coverage + coverage: '/Total:\|(\d+\.?\d+\%)/' + script: + # delete all empty files since they produce errors + - find coverage -size 0 -type f -delete + - ls coverage/ -lah + - lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final.out + - lcov --list coverage/final.out + + artifacts: + paths: + - coverage/final.out + + +include: + - '/DRAMSys/tests/DDR3/ci.yml' + - '/DRAMSys/tests/WIDEIO/ci.yml' + #- '/DRAMSys/tests/dramsys-gem5/ci.yml' # Should be activated again when a new gitlab runner with right dependencies is used diff --git a/DRAMSys/tests/DDR3/ci.yml b/DRAMSys/tests/DDR3/ci.yml deleted file mode 100644 index a5afa603..00000000 --- a/DRAMSys/tests/DDR3/ci.yml +++ /dev/null @@ -1,83 +0,0 @@ -# Standard DDR3 Test: -example_ddr3: - stage: DDR3 - script: - - export GCOV_PREFIX=$(pwd) - - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') - - cd build/simulator - - ./DRAMSys ../../DRAMSys/tests/DDR3/simulations/ddr3-example.xml ../../DRAMSys/tests/DDR3/ - - ls -lah - - ls -lah ../../DRAMSys/tests/DDR3/expected/ - - sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-example_ddr3_ch0.tdb ddr3-example_ddr3_ch0.tdb - - perl -e 'if(`sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-example_ddr3_ch0.tdb ddr3-example_ddr3_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' - - cd ../traceAnalyzer - - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/ddr3-example_ddr3_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi - # Run Code Coverage - - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out - - cache: - key: build - paths: - - build/ - policy: pull - - artifacts: - paths: - - build/simulator/ddr3-example_ddr3_ch0.tdb - - coverage/${CI_JOB_NAME}.out - expire_in: 2 days - -# Testing Reordering with FR_FCFS Scheduling Algorithm: -fr_fcfs: - stage: DDR3 - script: - - export GCOV_PREFIX=$(pwd) - - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') - - cd build/simulator - - ./DRAMSys ../../DRAMSys/tests/DDR3/simulations/ddr3-fr_fcfs.xml ../../DRAMSys/tests/DDR3/ - - ls -lah - - ls -lah ../../DRAMSys/tests/DDR3/expected/ - - sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-fr_fcfs_ddr3_ch0.tdb ddr3-fr_fcfs_ddr3_ch0.tdb - - perl -e 'if(`sqldiff ../../DRAMSys/tests/DDR3/expected/ddr3-fr_fcfs_ddr3_ch0.tdb ddr3-fr_fcfs_ddr3_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' - - cd ../traceAnalyzer - - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/ddr3-fr_fcfs_ddr3_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi - # Run Code Coverage - - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out - - cache: - key: build - paths: - - build/ - policy: pull - - allow_failure: true # TODO should be removed after first tests - - artifacts: - paths: - - build/simulator/ddr3-fr_fcfs_ddr3_ch0.tdb - - coverage/${CI_JOB_NAME}.out - expire_in: 2 days - -# Testing with TLM Protocol Checker -protocol_checker: - stage: DDR3 - script: - - export GCOV_PREFIX=$(pwd) - - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') - - cd build/simulator - - ./DRAMSys ../../DRAMSys/tests/DDR3/simulations/ddr3-protocol_checker.xml ../../DRAMSys/tests/DDR3/ > output.txt - - echo "TODO" - - ls -lah - # Run Code Coverage - - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out - - cache: - key: build - paths: - - build/ - policy: pull - - artifacts: - paths: - - coverage/${CI_JOB_NAME}.out - expire_in: 2 days diff --git a/DRAMSys/tests/DDR3/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml b/DRAMSys/tests/DDR3/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml deleted file mode 100644 index b2c3af48..00000000 --- a/DRAMSys/tests/DDR3/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml +++ /dev/null @@ -1,34 +0,0 @@ - - - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - 16 - 17 - 18 - 19 - 20 - 21 - 22 - 23 - 24 - 25 - 26 - 27 - 28 - 29 - - \ No newline at end of file diff --git a/DRAMSys/tests/DDR3/configs/mcconfigs/fifoStrict.xml b/DRAMSys/tests/DDR3/configs/mcconfigs/fifoStrict.xml deleted file mode 100644 index 44bf294e..00000000 --- a/DRAMSys/tests/DDR3/configs/mcconfigs/fifoStrict.xml +++ /dev/null @@ -1,20 +0,0 @@ - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml b/DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml deleted file mode 100644 index 7240485d..00000000 --- a/DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml +++ /dev/null @@ -1,20 +0,0 @@ - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/DDR3/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml b/DRAMSys/tests/DDR3/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml deleted file mode 100644 index 052f6773..00000000 --- a/DRAMSys/tests/DDR3/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml +++ /dev/null @@ -1,55 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/DDR3/configs/simulator/ddr3-protocol_checker.xml b/DRAMSys/tests/DDR3/configs/simulator/ddr3-protocol_checker.xml deleted file mode 100644 index 3efbabe7..00000000 --- a/DRAMSys/tests/DDR3/configs/simulator/ddr3-protocol_checker.xml +++ /dev/null @@ -1,29 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/DDR3/configs/simulator/ddr3.xml b/DRAMSys/tests/DDR3/configs/simulator/ddr3.xml deleted file mode 100644 index 1613737f..00000000 --- a/DRAMSys/tests/DDR3/configs/simulator/ddr3.xml +++ /dev/null @@ -1,29 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/DDR3/configs/thermalsim/config.xml b/DRAMSys/tests/DDR3/configs/thermalsim/config.xml deleted file mode 100644 index 4d32315e..00000000 --- a/DRAMSys/tests/DDR3/configs/thermalsim/config.xml +++ /dev/null @@ -1,14 +0,0 @@ - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/DDR3/configs/thermalsim/powerInfo.xml b/DRAMSys/tests/DDR3/configs/thermalsim/powerInfo.xml deleted file mode 100644 index 192cb4ea..00000000 --- a/DRAMSys/tests/DDR3/configs/thermalsim/powerInfo.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/DRAMSys/tests/DDR3/simulations/ddr3-example.xml b/DRAMSys/tests/DDR3/simulations/ddr3-example.xml deleted file mode 100644 index c6140385..00000000 --- a/DRAMSys/tests/DDR3/simulations/ddr3-example.xml +++ /dev/null @@ -1,25 +0,0 @@ - - - - - - - - - - - - - - - - - ddr3_example.stl - - diff --git a/DRAMSys/tests/DDR3/simulations/ddr3-fr_fcfs.xml b/DRAMSys/tests/DDR3/simulations/ddr3-fr_fcfs.xml deleted file mode 100644 index a432321b..00000000 --- a/DRAMSys/tests/DDR3/simulations/ddr3-fr_fcfs.xml +++ /dev/null @@ -1,25 +0,0 @@ - - - - - - - - - - - - - - - - - ddr3_example.stl - - diff --git a/DRAMSys/tests/DDR3/simulations/ddr3-protocol_checker.xml b/DRAMSys/tests/DDR3/simulations/ddr3-protocol_checker.xml deleted file mode 100644 index ececf822..00000000 --- a/DRAMSys/tests/DDR3/simulations/ddr3-protocol_checker.xml +++ /dev/null @@ -1,25 +0,0 @@ - - - - - - - - - - - - - - - - - ddr3_example.stl - - diff --git a/DRAMSys/tests/DDR4/ci.yml b/DRAMSys/tests/DDR4/ci.yml new file mode 100644 index 00000000..d6226908 --- /dev/null +++ b/DRAMSys/tests/DDR4/ci.yml @@ -0,0 +1,29 @@ +# DDR4 with 4 bank groups, flexible rankwise refresh and FrFcfs scheduler: +example_ddr4: + stage: DDR4 + script: + - export GCOV_PREFIX=$(pwd) + - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') + - cd build/simulator + - ./DRAMSys ../../DRAMSys/tests/DDR4/simulations/ddr4-example.json ../../DRAMSys/tests/DDR4/ + - ls -lah + - ls -lah ../../DRAMSys/tests/DDR4/expected/ + - sqldiff ../../DRAMSys/tests/DDR4/expected/ddr4-bankgrp_ddr4_ch0.tdb ddr4-bankgrp_ddr4_ch0.tdb + - perl -e 'if(`sqldiff ../../DRAMSys/tests/DDR4/expected/ddr4-bankgrp_ddr4_ch0.tdb ddr4-bankgrp_ddr4_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' + - cd ../traceAnalyzer + - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/ddr4-bankgrp_ddr4_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi + # Run Code Coverage + - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out + + cache: + key: build + paths: + - build/ + policy: pull + + artifacts: + paths: + - build/simulator/ddr4-bankgrp_ddr4_ch0.tdb + - coverage/${CI_JOB_NAME}.out + expire_in: 2 days + diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json b/DRAMSys/tests/DDR4/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json similarity index 100% rename from DRAMSys/tests/ddr4_bankgroups/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json rename to DRAMSys/tests/DDR4/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/mcconfigs/fr_fcfs.json b/DRAMSys/tests/DDR4/configs/mcconfigs/fr_fcfs.json similarity index 100% rename from DRAMSys/tests/ddr4_bankgroups/configs/mcconfigs/fr_fcfs.json rename to DRAMSys/tests/DDR4/configs/mcconfigs/fr_fcfs.json diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json b/DRAMSys/tests/DDR4/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json similarity index 94% rename from DRAMSys/tests/ddr4_bankgroups/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json rename to DRAMSys/tests/DDR4/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json index 11700aaf..abad7eab 100644 --- a/DRAMSys/tests/ddr4_bankgroups/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json +++ b/DRAMSys/tests/DDR4/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json @@ -8,7 +8,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A", "memoryType": "DDR4", @@ -63,4 +65,4 @@ "clkMhz": 933 } } -} \ No newline at end of file +} diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/simulator/ddr4.json b/DRAMSys/tests/DDR4/configs/simulator/ddr4.json similarity index 87% rename from DRAMSys/tests/ddr4_bankgroups/configs/simulator/ddr4.json rename to DRAMSys/tests/DDR4/configs/simulator/ddr4.json index 8e62e680..05cd86e2 100644 --- a/DRAMSys/tests/ddr4_bankgroups/configs/simulator/ddr4.json +++ b/DRAMSys/tests/DDR4/configs/simulator/ddr4.json @@ -8,8 +8,6 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, "PowerAnalysis": false, "SimulationName": "ddr4", "SimulationProgressBar": true, @@ -18,4 +16,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/config.json b/DRAMSys/tests/DDR4/configs/thermalsim/config.json similarity index 100% rename from DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/config.json rename to DRAMSys/tests/DDR4/configs/thermalsim/config.json diff --git a/DRAMSys/tests/DDR3/configs/thermalsim/core.flp b/DRAMSys/tests/DDR4/configs/thermalsim/core.flp similarity index 100% rename from DRAMSys/tests/DDR3/configs/thermalsim/core.flp rename to DRAMSys/tests/DDR4/configs/thermalsim/core.flp diff --git a/DRAMSys/tests/DDR3/configs/thermalsim/mem.flp b/DRAMSys/tests/DDR4/configs/thermalsim/mem.flp similarity index 100% rename from DRAMSys/tests/DDR3/configs/thermalsim/mem.flp rename to DRAMSys/tests/DDR4/configs/thermalsim/mem.flp diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/powerInfo.json b/DRAMSys/tests/DDR4/configs/thermalsim/powerInfo.json similarity index 100% rename from DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/powerInfo.json rename to DRAMSys/tests/DDR4/configs/thermalsim/powerInfo.json diff --git a/DRAMSys/tests/DDR3/configs/thermalsim/stack.stk b/DRAMSys/tests/DDR4/configs/thermalsim/stack.stk similarity index 100% rename from DRAMSys/tests/DDR3/configs/thermalsim/stack.stk rename to DRAMSys/tests/DDR4/configs/thermalsim/stack.stk diff --git a/DRAMSys/tests/DDR3/scripts/createTraceDB.sql b/DRAMSys/tests/DDR4/scripts/createTraceDB.sql similarity index 100% rename from DRAMSys/tests/DDR3/scripts/createTraceDB.sql rename to DRAMSys/tests/DDR4/scripts/createTraceDB.sql diff --git a/DRAMSys/tests/ddr4_bankgroups/simulations/ddr4-example.json b/DRAMSys/tests/DDR4/simulations/ddr4-example.json similarity index 100% rename from DRAMSys/tests/ddr4_bankgroups/simulations/ddr4-example.json rename to DRAMSys/tests/DDR4/simulations/ddr4-example.json diff --git a/DRAMSys/tests/HBM2/ci.yml b/DRAMSys/tests/HBM2/ci.yml new file mode 100644 index 00000000..fb9474a1 --- /dev/null +++ b/DRAMSys/tests/HBM2/ci.yml @@ -0,0 +1,29 @@ +# HBM2 test with 4 bank groups, 2 trace players, fifo strict scheduler and closed pg policy.: +example_HBM2: + stage: HBM2 + script: + - export GCOV_PREFIX=$(pwd) + - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') + - cd build/simulator + - ./DRAMSys ../../DRAMSys/tests/HBM2/simulations/hbm2-example.json ../../DRAMSys/tests/HBM2/ + - ls -lah + - ls -lah ../../DRAMSys/tests/HBM2/expected/ + - sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch0.tdb hbm2-example_hbm2_ch0.tdb + - perl -e 'if(`sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch0.tdb hbm2-example_hbm2_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' + - cd ../traceAnalyzer + - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/hbm2-example_hbm2_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi + # Run Code Coverage + - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out + + cache: + key: build + paths: + - build/ + policy: pull + + artifacts: + paths: + - build/simulator/hbm2-example_hbm2_ch0.tdb + - coverage/${CI_JOB_NAME}.out + expire_in: 2 days + diff --git a/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json b/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json index efa8ee9e..b5985d10 100644 --- a/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json +++ b/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json @@ -8,7 +8,9 @@ "nbrOfColumns": 128, "nbrOfRanks": 2, "nbrOfRows": 32768, - "width": 64 + "width": 64, + "NumberOfDevicesOnDIMM": 1, + "NumberOfMemChannels": 1 }, "memoryId": "https://www.computerbase.de/2019-05/amd-memory-tweak-vram-oc/#bilder", "memoryType": "HBM2", @@ -43,4 +45,4 @@ "clkMhz": 1000 } } -} \ No newline at end of file +} diff --git a/DRAMSys/tests/HBM2/configs/simulator/hbm2.json b/DRAMSys/tests/HBM2/configs/simulator/hbm2.json index 9589611f..608aec41 100644 --- a/DRAMSys/tests/HBM2/configs/simulator/hbm2.json +++ b/DRAMSys/tests/HBM2/configs/simulator/hbm2.json @@ -8,8 +8,6 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1, "PowerAnalysis": false, "SimulationName": "hbm2", "SimulationProgressBar": true, @@ -18,4 +16,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/tests/WIDEIO/ci.yml b/DRAMSys/tests/WIDEIO/ci.yml deleted file mode 100644 index e04215e0..00000000 --- a/DRAMSys/tests/WIDEIO/ci.yml +++ /dev/null @@ -1,40 +0,0 @@ -# vim: set ts=4 sw=4 expandtab: -example_wideio: - stage: WIDEIO - script: - - export GCOV_PREFIX=$(pwd) - - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') - # Generate specific traces for WIDEIO: - - cd DRAMSys/tests/WIDEIO/traces/ - - perl generator.pl - - cd - - # Run DRAMSys - - cd build/simulator - - ./DRAMSys ../../DRAMSys/tests/WIDEIO/simulations/wideio-example.xml ../../DRAMSys/tests/WIDEIO/ - - ls - # Run Traceanalyzer testing scripts: - - cd ../traceAnalyzer - - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/wideio-example_wideio_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi - - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/wideio-example_wideio_ch1.tdb | if ! grep "failed"; then exit 0; else exit 1; fi - - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/wideio-example_wideio_ch2.tdb | if ! grep "failed"; then exit 0; else exit 1; fi - - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/wideio-example_wideio_ch3.tdb | if ! grep "failed"; then exit 0; else exit 1; fi - # Run Code Coverage - - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out - - cache: - key: build - paths: - - build/ - policy: pull - - allow_failure: true # TODO: should be removed once the problems are fixed! - - artifacts: - paths: - - build/simulator/wideio-example_wideio_ch0.tdb - - build/simulator/wideio-example_wideio_ch1.tdb - - build/simulator/wideio-example_wideio_ch2.tdb - - build/simulator/wideio-example_wideio_ch3.tdb - - coverage/${CI_JOB_NAME}.out - expire_in: 2 days - diff --git a/DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_brc.xml b/DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_brc.xml deleted file mode 100755 index c6a33e71..00000000 --- a/DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_brc.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_rbc.xml b/DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_rbc.xml deleted file mode 100755 index 511a7f0a..00000000 --- a/DRAMSys/tests/WIDEIO/configs/amconfigs/am_wideio_rbc.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/DRAMSys/tests/WIDEIO/configs/mcconfigs/fifoStrict.xml b/DRAMSys/tests/WIDEIO/configs/mcconfigs/fifoStrict.xml deleted file mode 100644 index ed869b57..00000000 --- a/DRAMSys/tests/WIDEIO/configs/mcconfigs/fifoStrict.xml +++ /dev/null @@ -1,50 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/WIDEIO/configs/memspecs/wideio.xml b/DRAMSys/tests/WIDEIO/configs/memspecs/wideio.xml deleted file mode 100644 index fbe252d6..00000000 --- a/DRAMSys/tests/WIDEIO/configs/memspecs/wideio.xml +++ /dev/null @@ -1,61 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/WIDEIO/configs/simulator/wideio.xml b/DRAMSys/tests/WIDEIO/configs/simulator/wideio.xml deleted file mode 100644 index acd95599..00000000 --- a/DRAMSys/tests/WIDEIO/configs/simulator/wideio.xml +++ /dev/null @@ -1,24 +0,0 @@ - - - - - - - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/WIDEIO/configs/thermalsim/config.xml b/DRAMSys/tests/WIDEIO/configs/thermalsim/config.xml deleted file mode 100644 index 4d32315e..00000000 --- a/DRAMSys/tests/WIDEIO/configs/thermalsim/config.xml +++ /dev/null @@ -1,14 +0,0 @@ - - - - - - - - - - - - - - diff --git a/DRAMSys/tests/WIDEIO/configs/thermalsim/core.flp b/DRAMSys/tests/WIDEIO/configs/thermalsim/core.flp deleted file mode 100755 index e85e6801..00000000 --- a/DRAMSys/tests/WIDEIO/configs/thermalsim/core.flp +++ /dev/null @@ -1,45 +0,0 @@ -CPUs : - - position 0, 0 ; - dimension 2750, 4300 ; - -GPU : - - position 3350, 0 ; - dimension 2750, 4000 ; - -BASEBAND1 : - - position 4250, 4000 ; - dimension 1850, 3300 ; - -BASEBAND2 : - - position 3350, 7300 ; - dimension 2750, 3300 ; - -LLCACHE : - - position 0, 4300 ; - dimension 1900, 3000 ; - -DRAMCTRL1 : - - position 1900, 4300 ; - dimension 850, 3000 ; - -DRAMCTRL2 : - - position 3350, 4000 ; - dimension 900, 3300 ; - -TSVS : - - position 2750, 2300 ; - dimension 600, 6000 ; - -ACELLERATORS : - - position 0, 7300 ; - dimension 2750, 3300 ; - diff --git a/DRAMSys/tests/WIDEIO/configs/thermalsim/mem.flp b/DRAMSys/tests/WIDEIO/configs/thermalsim/mem.flp deleted file mode 100755 index 29d02254..00000000 --- a/DRAMSys/tests/WIDEIO/configs/thermalsim/mem.flp +++ /dev/null @@ -1,16 +0,0 @@ -channel0 : - position 150, 100 ; - dimension 2600, 5200 ; - -channel1 : - position 3350, 100 ; - dimension 2600, 5200 ; - -channel2 : - position 150, 5300 ; - dimension 2600, 5200 ; - -channel3 : - position 3350, 5300 ; - dimension 2600, 5200 ; - diff --git a/DRAMSys/tests/WIDEIO/configs/thermalsim/powerInfo.xml b/DRAMSys/tests/WIDEIO/configs/thermalsim/powerInfo.xml deleted file mode 100644 index 192cb4ea..00000000 --- a/DRAMSys/tests/WIDEIO/configs/thermalsim/powerInfo.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/DRAMSys/tests/WIDEIO/configs/thermalsim/stack.stk b/DRAMSys/tests/WIDEIO/configs/thermalsim/stack.stk deleted file mode 100755 index ec74f020..00000000 --- a/DRAMSys/tests/WIDEIO/configs/thermalsim/stack.stk +++ /dev/null @@ -1,49 +0,0 @@ -material SILICON : - thermal conductivity 1.30e-4 ; - volumetric heat capacity 1.628e-12 ; - -material BEOL : - thermal conductivity 2.25e-6 ; - volumetric heat capacity 2.175e-12 ; - -material COPPER : - thermal conductivity 4.01e-04 ; - volumetric heat capacity 3.37e-12 ; - -top heat sink : - //sink height 1e03, area 100e06, material COPPER ; - //spreader height 0.5e03, area 70e06, material SILICON ; - heat transfer coefficient 1.3e-09 ; - temperature 318.15 ; -dimensions : - chip length 6100, width 10600 ; - cell length 100, width 100 ; - - -layer PCB : - height 10 ; - material BEOL ; - -die DRAM : - layer 58.5 SILICON ; - source 2 SILICON ; - layer 1.5 BEOL ; - layer 58.5 SILICON ; - - -stack: - die DRAM_DIE DRAM floorplan "./mem.flp" ; - layer CONN_TO_PCB PCB ; - -solver: - transient step 0.01, slot 0.05 ; - initial temperature 300.0 ; - -output: - Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot ); - Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot ); - Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot ); - Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot ); - Tmap (DRAM_DIE, "output1.txt", slot) ; - Pmap (DRAM_DIE, "output2.txt", slot) ; - diff --git a/DRAMSys/tests/WIDEIO/scripts/createTraceDB.sql b/DRAMSys/tests/WIDEIO/scripts/createTraceDB.sql deleted file mode 100644 index 7a127fac..00000000 --- a/DRAMSys/tests/WIDEIO/scripts/createTraceDB.sql +++ /dev/null @@ -1,94 +0,0 @@ -DROP TABLE IF EXISTS Phases; -DROP TABLE IF EXISTS GeneralInfo; -DROP TABLE IF EXISTS CommandLengths; -DROP TABLE IF EXISTS Comments; -DROP TABLE IF EXISTS ranges; -DROP TABLE IF EXISTS Transactions; -DROP TABLE IF EXISTS DebugMessages; -DROP TABLE IF EXISTS Power; - -CREATE TABLE Phases( - ID INTEGER PRIMARY KEY, - PhaseName TEXT, - PhaseBegin INTEGER, - PhaseEnd INTEGER, - Transact INTEGER -); - -CREATE TABLE GeneralInfo( - NumberOfTransactions INTEGER, - TraceEnd INTEGER, - NumberOfRanks INTEGER, - NumberOfBanks INTEGER, - clk INTEGER, - UnitOfTime TEXT, - MCconfig TEXT, - Memspec TEXT, - Traces TEXT, - WindowSize INTEGER, - FlexibleRefresh INTEGER, - MaxRefBurst INTEGER, - ControllerThread INTEGER -); - -CREATE TABLE CommandLengths( - ACT INTEGER, - PRE INTEGER, - PREA INTEGER, - RD INTEGER, - RDA INTEGER, - WR INTEGER, - WRA INTEGER, - REFA INTEGER, - REFB INTEGER, - PDEA INTEGER, - PDXA INTEGER, - PDEP INTEGER, - PDXP INTEGER, - SREFEN INTEGER, - SREFEX INTEGER -); - -CREATE TABLE Power( - time DOUBLE, - AveragePower DOUBLE -); - - -CREATE TABLE Comments( - Time INTEGER, - Text TEXT -); - -CREATE TABLE DebugMessages( - Time INTEGER, - Message TEXT -); - --- use SQLITE R* TREE Module to make queries on timespans effecient (see http://www.sqlite.org/rtree.html) -CREATE VIRTUAL TABLE ranges USING rtree( - id, - begin, end -); - -CREATE TABLE Transactions( - ID INTEGER, - Range INTEGER, - Address INTEGER, - Burstlength INTEGER, - TThread INTEGER, - TChannel INTEGER, - TRank INTEGER, - TBankgroup INTEGER, - TBank INTEGER, - TRow INTEGER, - TColumn INTEGER, - DataStrobeBegin INTEGER, - DataStrobeEnd INTEGER, - TimeOfGeneration INTEGER, - Command TEXT - ); - -CREATE INDEX ranges_index ON Transactions(Range); -CREATE INDEX "phasesTransactions" ON "Phases" ("Transact" ASC); -CREATE INDEX "messageTimes" ON "DebugMessages" ("Time" ASC); diff --git a/DRAMSys/tests/WIDEIO/simulations/wideio-example.xml b/DRAMSys/tests/WIDEIO/simulations/wideio-example.xml deleted file mode 100644 index fea1f568..00000000 --- a/DRAMSys/tests/WIDEIO/simulations/wideio-example.xml +++ /dev/null @@ -1,24 +0,0 @@ - - - - - - - - - - - - - - - - - wideio.stl - - diff --git a/DRAMSys/tests/WIDEIO/traces/generator.pl b/DRAMSys/tests/WIDEIO/traces/generator.pl deleted file mode 100644 index 173a0248..00000000 --- a/DRAMSys/tests/WIDEIO/traces/generator.pl +++ /dev/null @@ -1,75 +0,0 @@ -#!/usr/bin/perl -w -use warnings; -use strict; - -# Width: 128 bit -# -# Mapping: -# 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 -# H | H B B B | R R R R | R R R R | R R R R | R C C C | C C C C | Y Y Y Y - - -open(OUT, "> wideio.stl"); - -my $length = 100000; -my $size = 0x10; -my $channelOffset = 0x8000000; -my $state = 0; -# state 0: reads only linear -# state 1: reads only random -# state 2: read and writes linear - -for(my $i=0; $i < $length; $i += 4) -{ - my $r = 0; - - if($state == 0) - { - print OUT ($i+0).": read ".sprintf("0x%x",($size*$i)+0*$channelOffset)."\n"; - print OUT ($i+1).": read ".sprintf("0x%x",($size*$i)+1*$channelOffset)."\n"; - print OUT ($i+2).": read ".sprintf("0x%x",($size*$i)+2*$channelOffset)."\n"; - print OUT ($i+3).": read ".sprintf("0x%x",($size*$i)+3*$channelOffset)."\n"; - } - elsif($state == 1) - { - $r = int(rand($channelOffset)); - print OUT ($i+0).": read ".sprintf("0x%x",($size*$r)+0*$channelOffset)."\n"; - $r = int(rand($channelOffset)); - print OUT ($i+1).": read ".sprintf("0x%x",($size*$r)+1*$channelOffset)."\n"; - $r = int(rand($channelOffset)); - print OUT ($i+2).": read ".sprintf("0x%x",($size*$r)+2*$channelOffset)."\n"; - $r = int(rand($channelOffset)); - print OUT ($i+3).": read ".sprintf("0x%x",($size*$r)+3*$channelOffset)."\n"; - } - elsif($state == 2) - { - my $rw = int(rand(2))%2; - if($rw == 0) - { - print OUT "$i: read ".sprintf("0x%x",($size*$i)+0*$channelOffset)."\n"; - print OUT "$i: read ".sprintf("0x%x",($size*$i)+1*$channelOffset)."\n"; - print OUT "$i: read ".sprintf("0x%x",($size*$i)+2*$channelOffset)."\n"; - print OUT "$i: read ".sprintf("0x%x",($size*$i)+3*$channelOffset)."\n"; - } - else - { - print OUT "$i: write ".sprintf("0x%x",($size*$i)+0*$channelOffset)."\n"; - print OUT "$i: write ".sprintf("0x%x",($size*$i)+1*$channelOffset)."\n"; - print OUT "$i: write ".sprintf("0x%x",($size*$i)+2*$channelOffset)."\n"; - print OUT "$i: write ".sprintf("0x%x",($size*$i)+3*$channelOffset)."\n"; - } - } - else - { - print "Error generating traces (".$state.")"; - exit(-1); - } - - if(($i != 0) && (($i % 1000) == 0)) - { - # GOTO next state every 1000st request: - $state = ($state + 1) % 3; - } -} - -close(OUT); diff --git a/DRAMSys/tests/ddr3_multirank/ci.yml b/DRAMSys/tests/ddr3_multirank/ci.yml new file mode 100644 index 00000000..da90393a --- /dev/null +++ b/DRAMSys/tests/ddr3_multirank/ci.yml @@ -0,0 +1,29 @@ +# DDR3 Dual Rank Test with Staggered Power Down Policy and Scheduler FrFcfsGrp +example_ddr3: + stage: DDR3 + script: + - export GCOV_PREFIX=$(pwd) + - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') + - cd build/simulator + - ./DRAMSys ../../DRAMSys/tests/ddr3_multirank/ddr3-example.json ../../DRAMSys/tests/ddr3_multirank/ + - ls -lah + - ls -lah ../../DRAMSys/tests/ddr3_multirank/expected/ + - sqldiff ../../DRAMSys/tests/ddr3_multirank/expected/ddr3-dual-rank_ddr3_ch0.tdb ddr3-dual-rank_ddr3_ch0.tdb + - perl -e 'if(`sqldiff ../../DRAMSys/tests/ddr3_multirank/expected/ddr3-dual-rank_ddr3_ch0.tdb ddr3-dual-rank_ddr3_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' + - cd ../traceAnalyzer + - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/ddr3_multirank_ddr3_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi + # Run Code Coverage + - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out + + cache: + key: build + paths: + - build/ + policy: pull + + artifacts: + paths: + - build/simulator/ddr3_multirank_ddr3_ch0.tdb + - coverage/${CI_JOB_NAME}.out + expire_in: 2 days + diff --git a/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json b/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json index 13d9fef5..d842bda2 100644 --- a/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json +++ b/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 2, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM", "memoryType": "DDR3", @@ -49,7 +51,12 @@ "XPDLL": 13, "XS": 64, "XSDLL": 512, - "clkMhz": 533 + "clkMhz": 533, + + "ACTPDEN": 1, + "PRPDEN": 1, + "REFPDEN": 1, + "RTRS": 1 } } } diff --git a/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json b/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json index 4e9faadc..99ccdb45 100644 --- a/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json +++ b/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json @@ -8,8 +8,6 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, "PowerAnalysis": false, "SimulationName": "ddr3", "SimulationProgressBar": true, diff --git a/DRAMSys/tests/ddr3_multirank/simulations/ddr3-example.json b/DRAMSys/tests/ddr3_multirank/simulations/ddr3-example.json index e3d4a4c3..b924da62 100644 --- a/DRAMSys/tests/ddr3_multirank/simulations/ddr3-example.json +++ b/DRAMSys/tests/ddr3_multirank/simulations/ddr3-example.json @@ -4,7 +4,7 @@ "mcconfig": "fr_fcfs_grp.json", "memspec": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json", "simconfig": "ddr3.json", - "simulationid": "ddr3-example-dual-rank-json", + "simulationid": "ddr3-dual-rank", "thermalconfig": "config.json", "tracesetup": [ { diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json deleted file mode 100644 index c82926c9..00000000 --- a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json +++ /dev/null @@ -1,51 +0,0 @@ -{ - "CONGEN": { - "XOR":[ - { - "FIRST":13, - "SECOND":16 - } - ], - "BANK_BIT": [ - 13, - 14, - 15 - ], - "BYTE_BIT": [ - 0, - 1, - 2 - ], - "COLUMN_BIT": [ - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12 - ], - "ROW_BIT": [ - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25, - 26, - 27, - 28, - 29 - ], - "RANK_BIT": [ - 30 - ] - } -} diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/mcconfigs/fr_fcfs_grp.json b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/mcconfigs/fr_fcfs_grp.json deleted file mode 100644 index 4ac02e30..00000000 --- a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/mcconfigs/fr_fcfs_grp.json +++ /dev/null @@ -1,12 +0,0 @@ -{"mcconfig": - {"PagePolicy": "Open", - "Scheduler": "FrFcfsGrp", - "RequestBufferSize": 8, - "CmdMux": "Oldest", - "RespQueue": "Fifo", - "RefreshPolicy": "Rankwise", - "RefreshMode": 1, - "RefreshMaxPostponed": 0, - "RefreshMaxPulledin": 0, - "PowerDownPolicy": "Staggered", - "PowerDownTimeout": 100}} diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json deleted file mode 100644 index d842bda2..00000000 --- a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json +++ /dev/null @@ -1,62 +0,0 @@ -{ - "memspec": { - "memarchitecturespec": { - "burstLength": 8, - "dataRate": 2, - "nbrOfBanks": 8, - "nbrOfColumns": 1024, - "nbrOfRanks": 2, - "nbrOfRows": 16384, - "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 - }, - "memoryId": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM", - "memoryType": "DDR3", - "mempowerspec": { - "idd0": 720.0, - "idd2n": 400.0, - "idd2p0": 80.0, - "idd2p1": 200.0, - "idd3n": 440.0, - "idd3p0": 240.0, - "idd3p1": 240.0, - "idd4r": 1200.0, - "idd4w": 1200.0, - "idd5": 1760.0, - "idd6": 48.0, - "vdd": 1.5 - }, - "memtimingspec": { - "AL": 0, - "CCD": 4, - "CKE": 3, - "CKESR": 4, - "CL": 7, - "DQSCK": 0, - "FAW": 20, - "RAS": 20, - "RC": 27, - "RCD": 7, - "REFI": 4160, - "RFC": 59, - "RL": 7, - "RP": 7, - "RRD": 4, - "RTP": 4, - "WL": 6, - "WR": 8, - "WTR": 4, - "XP": 4, - "XPDLL": 13, - "XS": 64, - "XSDLL": 512, - "clkMhz": 533, - - "ACTPDEN": 1, - "PRPDEN": 1, - "REFPDEN": 1, - "RTRS": 1 - } - } -} diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/simulator/ddr3.json b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/simulator/ddr3.json deleted file mode 100644 index 99ccdb45..00000000 --- a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/simulator/ddr3.json +++ /dev/null @@ -1,19 +0,0 @@ -{ - "simconfig": { - "AddressOffset": 0, - "CheckTLM2Protocol": false, - "DatabaseRecording": true, - "Debug": false, - "ECCControllerMode": "Disabled", - "EnableWindowing": false, - "ErrorCSVFile": "", - "ErrorChipSeed": 42, - "PowerAnalysis": false, - "SimulationName": "ddr3", - "SimulationProgressBar": true, - "StoreMode": "NoStorage", - "ThermalSimulation": false, - "UseMalloc": false, - "WindowSize": 1000 - } -} diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/core.flp b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/core.flp deleted file mode 100755 index e85e6801..00000000 --- a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/core.flp +++ /dev/null @@ -1,45 +0,0 @@ -CPUs : - - position 0, 0 ; - dimension 2750, 4300 ; - -GPU : - - position 3350, 0 ; - dimension 2750, 4000 ; - -BASEBAND1 : - - position 4250, 4000 ; - dimension 1850, 3300 ; - -BASEBAND2 : - - position 3350, 7300 ; - dimension 2750, 3300 ; - -LLCACHE : - - position 0, 4300 ; - dimension 1900, 3000 ; - -DRAMCTRL1 : - - position 1900, 4300 ; - dimension 850, 3000 ; - -DRAMCTRL2 : - - position 3350, 4000 ; - dimension 900, 3300 ; - -TSVS : - - position 2750, 2300 ; - dimension 600, 6000 ; - -ACELLERATORS : - - position 0, 7300 ; - dimension 2750, 3300 ; - diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/mem.flp b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/mem.flp deleted file mode 100755 index 29d02254..00000000 --- a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/mem.flp +++ /dev/null @@ -1,16 +0,0 @@ -channel0 : - position 150, 100 ; - dimension 2600, 5200 ; - -channel1 : - position 3350, 100 ; - dimension 2600, 5200 ; - -channel2 : - position 150, 5300 ; - dimension 2600, 5200 ; - -channel3 : - position 3350, 5300 ; - dimension 2600, 5200 ; - diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/stack.stk b/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/stack.stk deleted file mode 100755 index ec74f020..00000000 --- a/DRAMSys/tests/ddr3_parametersAtMemspec/configs/thermalsim/stack.stk +++ /dev/null @@ -1,49 +0,0 @@ -material SILICON : - thermal conductivity 1.30e-4 ; - volumetric heat capacity 1.628e-12 ; - -material BEOL : - thermal conductivity 2.25e-6 ; - volumetric heat capacity 2.175e-12 ; - -material COPPER : - thermal conductivity 4.01e-04 ; - volumetric heat capacity 3.37e-12 ; - -top heat sink : - //sink height 1e03, area 100e06, material COPPER ; - //spreader height 0.5e03, area 70e06, material SILICON ; - heat transfer coefficient 1.3e-09 ; - temperature 318.15 ; -dimensions : - chip length 6100, width 10600 ; - cell length 100, width 100 ; - - -layer PCB : - height 10 ; - material BEOL ; - -die DRAM : - layer 58.5 SILICON ; - source 2 SILICON ; - layer 1.5 BEOL ; - layer 58.5 SILICON ; - - -stack: - die DRAM_DIE DRAM floorplan "./mem.flp" ; - layer CONN_TO_PCB PCB ; - -solver: - transient step 0.01, slot 0.05 ; - initial temperature 300.0 ; - -output: - Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot ); - Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot ); - Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot ); - Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot ); - Tmap (DRAM_DIE, "output1.txt", slot) ; - Pmap (DRAM_DIE, "output2.txt", slot) ; - diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/scripts/createTraceDB.sql b/DRAMSys/tests/ddr3_parametersAtMemspec/scripts/createTraceDB.sql deleted file mode 100644 index 7a127fac..00000000 --- a/DRAMSys/tests/ddr3_parametersAtMemspec/scripts/createTraceDB.sql +++ /dev/null @@ -1,94 +0,0 @@ -DROP TABLE IF EXISTS Phases; -DROP TABLE IF EXISTS GeneralInfo; -DROP TABLE IF EXISTS CommandLengths; -DROP TABLE IF EXISTS Comments; -DROP TABLE IF EXISTS ranges; -DROP TABLE IF EXISTS Transactions; -DROP TABLE IF EXISTS DebugMessages; -DROP TABLE IF EXISTS Power; - -CREATE TABLE Phases( - ID INTEGER PRIMARY KEY, - PhaseName TEXT, - PhaseBegin INTEGER, - PhaseEnd INTEGER, - Transact INTEGER -); - -CREATE TABLE GeneralInfo( - NumberOfTransactions INTEGER, - TraceEnd INTEGER, - NumberOfRanks INTEGER, - NumberOfBanks INTEGER, - clk INTEGER, - UnitOfTime TEXT, - MCconfig TEXT, - Memspec TEXT, - Traces TEXT, - WindowSize INTEGER, - FlexibleRefresh INTEGER, - MaxRefBurst INTEGER, - ControllerThread INTEGER -); - -CREATE TABLE CommandLengths( - ACT INTEGER, - PRE INTEGER, - PREA INTEGER, - RD INTEGER, - RDA INTEGER, - WR INTEGER, - WRA INTEGER, - REFA INTEGER, - REFB INTEGER, - PDEA INTEGER, - PDXA INTEGER, - PDEP INTEGER, - PDXP INTEGER, - SREFEN INTEGER, - SREFEX INTEGER -); - -CREATE TABLE Power( - time DOUBLE, - AveragePower DOUBLE -); - - -CREATE TABLE Comments( - Time INTEGER, - Text TEXT -); - -CREATE TABLE DebugMessages( - Time INTEGER, - Message TEXT -); - --- use SQLITE R* TREE Module to make queries on timespans effecient (see http://www.sqlite.org/rtree.html) -CREATE VIRTUAL TABLE ranges USING rtree( - id, - begin, end -); - -CREATE TABLE Transactions( - ID INTEGER, - Range INTEGER, - Address INTEGER, - Burstlength INTEGER, - TThread INTEGER, - TChannel INTEGER, - TRank INTEGER, - TBankgroup INTEGER, - TBank INTEGER, - TRow INTEGER, - TColumn INTEGER, - DataStrobeBegin INTEGER, - DataStrobeEnd INTEGER, - TimeOfGeneration INTEGER, - Command TEXT - ); - -CREATE INDEX ranges_index ON Transactions(Range); -CREATE INDEX "phasesTransactions" ON "Phases" ("Transact" ASC); -CREATE INDEX "messageTimes" ON "DebugMessages" ("Time" ASC); diff --git a/DRAMSys/tests/ddr3_parametersAtMemspec/simulations/ddr3-example.json b/DRAMSys/tests/ddr3_parametersAtMemspec/simulations/ddr3-example.json deleted file mode 100644 index e3d4a4c3..00000000 --- a/DRAMSys/tests/ddr3_parametersAtMemspec/simulations/ddr3-example.json +++ /dev/null @@ -1,16 +0,0 @@ -{ - "simulation": { - "addressmapping": "am_ddr3_8x2Gbx8_dimm_p1KB_dual_rank_rbc.json", - "mcconfig": "fr_fcfs_grp.json", - "memspec": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json", - "simconfig": "ddr3.json", - "simulationid": "ddr3-example-dual-rank-json", - "thermalconfig": "config.json", - "tracesetup": [ - { - "clkMhz": 533, - "name": "trace_test2.stl" - } - ] - } -} diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/config.json b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/config.json deleted file mode 100644 index b88ed84c..00000000 --- a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/config.json +++ /dev/null @@ -1,15 +0,0 @@ -{ - "thermalsimconfig": { - "TemperatureScale": "Celsius", - "StaticTemperatureDefaultValue": 89, - "ThermalSimPeriod":100, - "ThermalSimUnit":"us", - "PowerInfoFile": "powerInfo.json", - "IceServerIp": "127.0.0.1", - "IceServerPort": 11880, - "SimPeriodAdjustFactor" : 10, - "NPowStableCyclesToIncreasePeriod": 5, - "GenerateTemperatureMap": true, - "GeneratePowerMap": true - } -} diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/core.flp b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/core.flp deleted file mode 100755 index e85e6801..00000000 --- a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/core.flp +++ /dev/null @@ -1,45 +0,0 @@ -CPUs : - - position 0, 0 ; - dimension 2750, 4300 ; - -GPU : - - position 3350, 0 ; - dimension 2750, 4000 ; - -BASEBAND1 : - - position 4250, 4000 ; - dimension 1850, 3300 ; - -BASEBAND2 : - - position 3350, 7300 ; - dimension 2750, 3300 ; - -LLCACHE : - - position 0, 4300 ; - dimension 1900, 3000 ; - -DRAMCTRL1 : - - position 1900, 4300 ; - dimension 850, 3000 ; - -DRAMCTRL2 : - - position 3350, 4000 ; - dimension 900, 3300 ; - -TSVS : - - position 2750, 2300 ; - dimension 600, 6000 ; - -ACELLERATORS : - - position 0, 7300 ; - dimension 2750, 3300 ; - diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/mem.flp b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/mem.flp deleted file mode 100755 index 29d02254..00000000 --- a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/mem.flp +++ /dev/null @@ -1,16 +0,0 @@ -channel0 : - position 150, 100 ; - dimension 2600, 5200 ; - -channel1 : - position 3350, 100 ; - dimension 2600, 5200 ; - -channel2 : - position 150, 5300 ; - dimension 2600, 5200 ; - -channel3 : - position 3350, 5300 ; - dimension 2600, 5200 ; - diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/powerInfo.json b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/powerInfo.json deleted file mode 100644 index 524f690f..00000000 --- a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/powerInfo.json +++ /dev/null @@ -1,20 +0,0 @@ -{ - "powerInfo": { - "dram_die_channel0": { - "init_pow": 0, - "threshold": 1.0 - }, - "dram_die_channel1": { - "init_pow": 0, - "threshold": 1.0 - }, - "dram_die_channel2": { - "init_pow": 0, - "threshold": 1.0 - }, - "dram_die_channel3": { - "init_pow": 0, - "threshold": 1.0 - } - } -} diff --git a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/stack.stk b/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/stack.stk deleted file mode 100755 index ec74f020..00000000 --- a/DRAMSys/tests/ddr4_bankgroups/configs/thermalsim/stack.stk +++ /dev/null @@ -1,49 +0,0 @@ -material SILICON : - thermal conductivity 1.30e-4 ; - volumetric heat capacity 1.628e-12 ; - -material BEOL : - thermal conductivity 2.25e-6 ; - volumetric heat capacity 2.175e-12 ; - -material COPPER : - thermal conductivity 4.01e-04 ; - volumetric heat capacity 3.37e-12 ; - -top heat sink : - //sink height 1e03, area 100e06, material COPPER ; - //spreader height 0.5e03, area 70e06, material SILICON ; - heat transfer coefficient 1.3e-09 ; - temperature 318.15 ; -dimensions : - chip length 6100, width 10600 ; - cell length 100, width 100 ; - - -layer PCB : - height 10 ; - material BEOL ; - -die DRAM : - layer 58.5 SILICON ; - source 2 SILICON ; - layer 1.5 BEOL ; - layer 58.5 SILICON ; - - -stack: - die DRAM_DIE DRAM floorplan "./mem.flp" ; - layer CONN_TO_PCB PCB ; - -solver: - transient step 0.01, slot 0.05 ; - initial temperature 300.0 ; - -output: - Tflpel(DRAM_DIE.channel0 , "temp_flp_element_ch0.txt" , average , slot ); - Tflpel(DRAM_DIE.channel1 , "temp_flp_element_ch1.txt" , average , slot ); - Tflpel(DRAM_DIE.channel2 , "temp_flp_element_ch2.txt" , average , slot ); - Tflpel(DRAM_DIE.channel3 , "temp_flp_element_ch3.txt" , average , slot ); - Tmap (DRAM_DIE, "output1.txt", slot) ; - Pmap (DRAM_DIE, "output2.txt", slot) ; - diff --git a/DRAMSys/tests/ddr4_bankgroups/scripts/createTraceDB.sql b/DRAMSys/tests/ddr4_bankgroups/scripts/createTraceDB.sql deleted file mode 100644 index 7a127fac..00000000 --- a/DRAMSys/tests/ddr4_bankgroups/scripts/createTraceDB.sql +++ /dev/null @@ -1,94 +0,0 @@ -DROP TABLE IF EXISTS Phases; -DROP TABLE IF EXISTS GeneralInfo; -DROP TABLE IF EXISTS CommandLengths; -DROP TABLE IF EXISTS Comments; -DROP TABLE IF EXISTS ranges; -DROP TABLE IF EXISTS Transactions; -DROP TABLE IF EXISTS DebugMessages; -DROP TABLE IF EXISTS Power; - -CREATE TABLE Phases( - ID INTEGER PRIMARY KEY, - PhaseName TEXT, - PhaseBegin INTEGER, - PhaseEnd INTEGER, - Transact INTEGER -); - -CREATE TABLE GeneralInfo( - NumberOfTransactions INTEGER, - TraceEnd INTEGER, - NumberOfRanks INTEGER, - NumberOfBanks INTEGER, - clk INTEGER, - UnitOfTime TEXT, - MCconfig TEXT, - Memspec TEXT, - Traces TEXT, - WindowSize INTEGER, - FlexibleRefresh INTEGER, - MaxRefBurst INTEGER, - ControllerThread INTEGER -); - -CREATE TABLE CommandLengths( - ACT INTEGER, - PRE INTEGER, - PREA INTEGER, - RD INTEGER, - RDA INTEGER, - WR INTEGER, - WRA INTEGER, - REFA INTEGER, - REFB INTEGER, - PDEA INTEGER, - PDXA INTEGER, - PDEP INTEGER, - PDXP INTEGER, - SREFEN INTEGER, - SREFEX INTEGER -); - -CREATE TABLE Power( - time DOUBLE, - AveragePower DOUBLE -); - - -CREATE TABLE Comments( - Time INTEGER, - Text TEXT -); - -CREATE TABLE DebugMessages( - Time INTEGER, - Message TEXT -); - --- use SQLITE R* TREE Module to make queries on timespans effecient (see http://www.sqlite.org/rtree.html) -CREATE VIRTUAL TABLE ranges USING rtree( - id, - begin, end -); - -CREATE TABLE Transactions( - ID INTEGER, - Range INTEGER, - Address INTEGER, - Burstlength INTEGER, - TThread INTEGER, - TChannel INTEGER, - TRank INTEGER, - TBankgroup INTEGER, - TBank INTEGER, - TRow INTEGER, - TColumn INTEGER, - DataStrobeBegin INTEGER, - DataStrobeEnd INTEGER, - TimeOfGeneration INTEGER, - Command TEXT - ); - -CREATE INDEX ranges_index ON Transactions(Range); -CREATE INDEX "phasesTransactions" ON "Phases" ("Transact" ASC); -CREATE INDEX "messageTimes" ON "DebugMessages" ("Time" ASC); diff --git a/DRAMSys/tests/lpddr4/ci.yml b/DRAMSys/tests/lpddr4/ci.yml new file mode 100644 index 00000000..40860f3f --- /dev/null +++ b/DRAMSys/tests/lpddr4/ci.yml @@ -0,0 +1,28 @@ +# LPDDR4 with Bankwise Flexible Refresh and FIFO Scheduler: +example_lpddr4: + stage: LPDDR4 + script: + - export GCOV_PREFIX=$(pwd) + - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') + - cd build/simulator + - ./DRAMSys ../../DRAMSys/tests/lpddr4/simulations/lpddr4-example.json ../../DRAMSys/tests/lpddr4/ + - ls -lah + - ls -lah ../../DRAMSys/tests/lpddr4/expected/ + - sqldiff ../../DRAMSys/tests/lpddr4/expected/lpddr4-example_lpddr4_ch0.tdb lpddr4-example_lpddr4_ch0.tdb + - perl -e 'if(`sqldiff ../../DRAMSys/tests/lpddr4/expected/lpddr4-example_lpddr4_ch0.tdb lpddr4-example_lpddr4_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' + - cd ../traceAnalyzer + - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/lpddr4-example_lpddr4_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi + # Run Code Coverage + - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out + + cache: + key: build + paths: + - build/ + policy: pull + + artifacts: + paths: + - build/simulator/lpddr4-example_lpddr4_ch0.tdb + - coverage/${CI_JOB_NAME}.out + expire_in: 2 days diff --git a/DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json b/DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json index 97a8cc3e..fce6c632 100644 --- a/DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json +++ b/DRAMSys/tests/lpddr4/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 65536, - "width": 16 + "width": 16, + "NumberOfDevicesOnDIMM": 1, + "NumberOfMemChannels": 1, }, "memoryId": "JEDEC_8Gb_LPDDR4-3200_16bit", "memoryType": "LPDDR4", @@ -40,7 +42,11 @@ "WTR": 16, "XP": 12, "XSR": 460, + "ACTPDEN": 1, + "PRPDEN": 1, + "REFPDEN": 1, + "RTRS": 1, "clkMhz": 1600 } } -} \ No newline at end of file +} diff --git a/DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json b/DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json index fd8fe855..6ea5b1bd 100644 --- a/DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json +++ b/DRAMSys/tests/lpddr4/configs/simulator/lpddr4.json @@ -8,8 +8,6 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1, "PowerAnalysis": false, "SimulationName": "lpddr4", "SimulationProgressBar": true, @@ -18,4 +16,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} From ab206aa68839e7c245be317c78cb53b98564f644 Mon Sep 17 00:00:00 2001 From: scorrea Date: Tue, 16 Jun 2020 11:50:11 +0200 Subject: [PATCH 05/34] ci.yml edited --- .gitlab-ci.yml | 11 +++++---- .gitlab-ci_old.yml | 56 ---------------------------------------------- 2 files changed, 7 insertions(+), 60 deletions(-) delete mode 100644 .gitlab-ci_old.yml diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 9011e4ab..800215b0 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -6,9 +6,10 @@ variables: stages: - build - - dramsys-gem5-build - - WIDEIO + - LPDDR4 - DDR3 + - DDR4 + - HBM2 - Coverage build: @@ -51,6 +52,8 @@ coverage: include: - - '/DRAMSys/tests/DDR3/ci.yml' - - '/DRAMSys/tests/WIDEIO/ci.yml' + - '/DRAMSys/tests/lpddr4/ci.yml' + - '/DRAMSys/tests/ddr3_multirank/ci.yml' + - '/DRAMSys/tests/DDR4/ci.yml' + - '/DRAMSys/tests/HBM2/ci.yml' #- '/DRAMSys/tests/dramsys-gem5/ci.yml' # Should be activated again when a new gitlab runner with right dependencies is used diff --git a/.gitlab-ci_old.yml b/.gitlab-ci_old.yml deleted file mode 100644 index 9011e4ab..00000000 --- a/.gitlab-ci_old.yml +++ /dev/null @@ -1,56 +0,0 @@ -# vim: set ts=4 sw=4 expandtab: -image: gcc - -variables: - GIT_STRATEGY: clone - -stages: - - build - - dramsys-gem5-build - - WIDEIO - - DDR3 - - Coverage - -build: - stage: build - script: - - git submodule sync - - git submodule update --init --recursive - - rm -rf build - - mkdir -p build - - cd build - - cmake ../DRAMSys - - make -j16 - - find . -name "*.o" -type f -delete - - rm -rf ${CI_PROJECT_DIR}/coverage - - mkdir -p ${CI_PROJECT_DIR}/coverage - - cache: - key: build - paths: - - build/ - policy: push - - artifacts: - paths: - - coverage/ - -coverage: - stage: Coverage - coverage: '/Total:\|(\d+\.?\d+\%)/' - script: - # delete all empty files since they produce errors - - find coverage -size 0 -type f -delete - - ls coverage/ -lah - - lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final.out - - lcov --list coverage/final.out - - artifacts: - paths: - - coverage/final.out - - -include: - - '/DRAMSys/tests/DDR3/ci.yml' - - '/DRAMSys/tests/WIDEIO/ci.yml' - #- '/DRAMSys/tests/dramsys-gem5/ci.yml' # Should be activated again when a new gitlab runner with right dependencies is used From 5f57c29224a27aa279d8b11cf632a636d1e7adb8 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 16 Jun 2020 13:24:20 +0200 Subject: [PATCH 06/34] Per-bank refresh fix. --- .../src/controller/checker/CheckerLPDDR4.cpp | 2 +- .../refresh/RefreshManagerBankwise.cpp | 25 ++++++++++++++----- .../refresh/RefreshManagerBankwise.h | 1 + 3 files changed, 21 insertions(+), 7 deletions(-) diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp index 09adc6d1..98e304fc 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp @@ -164,7 +164,7 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, Bank } else if (command == Command::ACT) { - lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][rank.ID()]; + lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != SC_ZERO_TIME) earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCpb); diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp index 349bef14..84429e4c 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp @@ -91,14 +91,17 @@ sc_time RefreshManagerBankwise::start() bool forcedRefresh = (flexibilityCounter == maxPostponed); bool allBanksBusy = true; - for (auto it = remainingBankMachines.begin(); it != remainingBankMachines.end(); it++) + if (!skipSelection) { - if ((*it)->isIdle()) + for (auto it = remainingBankMachines.begin(); it != remainingBankMachines.end(); it++) { - currentIterator = it; - currentBankMachine = *it; - allBanksBusy = false; - break; + if ((*it)->isIdle()) + { + currentIterator = it; + currentBankMachine = *it; + allBanksBusy = false; + break; + } } } @@ -113,7 +116,16 @@ sc_time RefreshManagerBankwise::start() if (currentBankMachine->getState() == BmState::Activated) nextCommand = Command::PRE; else + { nextCommand = Command::REFB; + + if (forcedRefresh) + { + currentBankMachine->block(); + skipSelection = true; + } + } + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, currentBankMachine->getBankGroup(), currentBankMachine->getBank()); return timeToSchedule; @@ -161,6 +173,7 @@ void RefreshManagerBankwise::updateState(Command command, tlm_generic_payload *p switch (command) { case Command::REFB: + skipSelection = false; remainingBankMachines.erase(currentIterator); if (remainingBankMachines.empty()) remainingBankMachines = allBankMachines; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h index 285329b5..252a4b9e 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h @@ -74,6 +74,7 @@ private: int maxPulledin = 0; bool sleeping = false; + bool skipSelection = false; }; #endif // REFRESHMANAGERBANKWISE_H From 295810ac1b69fe0da354e2f4131a28e810ae3779 Mon Sep 17 00:00:00 2001 From: scorrea Date: Thu, 18 Jun 2020 10:40:37 +0200 Subject: [PATCH 07/34] ci tests traces and memspec modified --- DRAMSys/library/resources/configs/memspecs/HBM2.json | 5 +++-- .../configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json | 5 +++-- .../configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json | 5 +++-- .../configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json | 6 ++++-- .../configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json | 6 ++++-- .../configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json | 5 +++-- .../configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json | 5 +++-- .../configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json | 5 +++-- .../configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json | 5 +++-- .../configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json | 5 +++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json | 6 ++++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json | 6 ++++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json | 6 ++++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json | 6 ++++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json | 6 ++++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json | 6 ++++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json | 6 ++++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json | 6 ++++-- .../configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json | 4 +++- .../configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json | 6 ++++-- .../configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json | 6 ++++-- .../memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json | 6 ++++-- .../configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json | 6 ++++-- .../configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json | 6 ++++-- .../memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json | 6 ++++-- .../memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json | 6 ++++-- .../memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json | 6 ++++-- .../memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json | 6 ++++-- .../configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json | 6 ++++-- .../configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json | 6 ++++-- .../configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json | 6 ++++-- .../configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json | 6 ++++-- .../configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json | 6 ++++-- .../configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json | 6 ++++-- .../configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json | 6 ++++-- .../configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json | 6 ++++-- .../configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json | 5 +++-- .../configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json | 5 +++-- .../configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json | 5 +++-- .../configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json | 5 +++-- .../configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json | 6 ++++-- .../configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json | 6 ++++-- .../configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json | 5 +++-- .../configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json | 5 +++-- .../configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json | 5 +++-- .../memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json | 6 ++++-- .../memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json | 6 ++++-- .../resources/configs/memspecs/memspec_ranktest.json | 5 +++-- .../resources/configs/simulator/ddr3-single-device.json | 4 +--- DRAMSys/library/resources/configs/simulator/ddr3.json | 2 -- .../resources/configs/simulator/ddr3_boot_linux.json | 4 +--- DRAMSys/library/resources/configs/simulator/ddr3_ecc.json | 4 +--- .../library/resources/configs/simulator/ddr3_gem5_se.json | 4 +--- DRAMSys/library/resources/configs/simulator/ddr4.json | 4 +--- DRAMSys/library/resources/configs/simulator/hbm2.json | 4 +--- DRAMSys/library/resources/configs/simulator/lpddr4.json | 3 +-- DRAMSys/library/resources/configs/simulator/wideio.json | 4 +--- DRAMSys/library/resources/configs/simulator/wideio_ecc.json | 4 +--- .../library/resources/configs/simulator/wideio_thermal.json | 4 +--- DRAMSys/tests/DDR4/configs/mcconfigs/fr_fcfs.json | 4 ++-- DRAMSys/tests/HBM2/configs/memspecs/HBM2.json | 1 - .../memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json | 4 ++-- 62 files changed, 189 insertions(+), 131 deletions(-) diff --git a/DRAMSys/library/resources/configs/memspecs/HBM2.json b/DRAMSys/library/resources/configs/memspecs/HBM2.json index efa8ee9e..bc9faa23 100644 --- a/DRAMSys/library/resources/configs/memspecs/HBM2.json +++ b/DRAMSys/library/resources/configs/memspecs/HBM2.json @@ -8,7 +8,8 @@ "nbrOfColumns": 128, "nbrOfRanks": 2, "nbrOfRows": 32768, - "width": 64 + "width": 64, + "NumberOfMemChannels": 1 }, "memoryId": "https://www.computerbase.de/2019-05/amd-memory-tweak-vram-oc/#bilder", "memoryType": "HBM2", @@ -43,4 +44,4 @@ "clkMhz": 1000 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json index 64256e3c..17630099 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json @@ -7,7 +7,8 @@ "nbrOfColumns": 128, "nbrOfRanks": 1, "nbrOfRows": 4096, - "width": 128 + "width": 128, + "NumberOfMemChannels": 4 }, "memoryId": "JEDEC_256Mb_WIDEIO_SDR-200_128bit", "memoryType": "WIDEIO_SDR", @@ -62,4 +63,4 @@ "clkMhz": 200 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json index c2d60cd9..7f576e12 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json @@ -7,7 +7,8 @@ "nbrOfColumns": 128, "nbrOfRanks": 1, "nbrOfRows": 4096, - "width": 128 + "width": 128, + "NumberOfMemChannels": 4 }, "memoryId": "JEDEC_256Mb_WIDEIO_SDR-266_128bit", "memoryType": "WIDEIO_SDR", @@ -62,4 +63,4 @@ "clkMhz": 266 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json index c7c0e7a0..db212fc7 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json @@ -8,7 +8,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A", "memoryType": "DDR4", @@ -65,4 +67,4 @@ "clkMhz": 933 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json index 51ac9635..9ea5ca87 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json @@ -8,7 +8,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_4Gb_DDR4-2400_8bit_A", "memoryType": "DDR4", @@ -65,4 +67,4 @@ "clkMhz": 1200 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json index 65be78a0..29e9f3d6 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json @@ -7,7 +7,8 @@ "nbrOfColumns": 512, "nbrOfRanks": 1, "nbrOfRows": 8192, - "width": 64 + "width": 64, + "NumberOfMemChannels": 4 }, "memoryId": "JEDEC_4x64_2Gb_WIDEIO2-400_64bit", "memoryType": "WIDEIO2", @@ -39,4 +40,4 @@ "clkMhz": 400 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json index a01fedb0..16f3546f 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json @@ -7,7 +7,8 @@ "nbrOfColumns": 512, "nbrOfRanks": 1, "nbrOfRows": 8192, - "width": 64 + "width": 64, + "NumberOfMemChannels": 4 }, "memoryId": "JEDEC_4x64_2Gb_WIDEIO2-533_64bit", "memoryType": "WIDEIO2", @@ -39,4 +40,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json index c41d427f..6504cd54 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json @@ -7,7 +7,8 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 65536, - "width": 16 + "width": 16, + "NumberOfMemChannels": 1 }, "memoryId": "JEDEC_8Gb_LPDDR4-3200_16bit", "memoryType": "LPDDR4", @@ -93,4 +94,4 @@ "clkMhz": 1600 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json index aaecf874..42692386 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json @@ -7,7 +7,8 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 8192, - "width": 16 + "width": 16, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR2-1066_16bit_H", "memoryType": "DDR2", @@ -52,4 +53,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json index 33f80da5..3cbdec2d 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json @@ -7,7 +7,8 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 8192, - "width": 16 + "width": 16, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR2-800_16bit_H", "memoryType": "DDR2", @@ -52,4 +53,4 @@ "clkMhz": 400 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json index 467c599b..0e15b9b3 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 8192, - "width": 16 + "width": 16, + "NumberOfDevicesOnDIMM": 4, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json index 6ff10023..f6557d3d 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 8192, - "width": 16 + "width": 16, + "NumberOfDevicesOnDIMM": 4, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G_2s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json index 9b4a0ad8..f8b477bb 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 8192, - "width": 16 + "width": 16, + "NumberOfDevicesOnDIMM": 4, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G_3s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json index 9459ab49..fe0feff6 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 8192, - "width": 16 + "width": 16, + "NumberOfDevicesOnDIMM": 4, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G_mu", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json index 5dd17ce0..549f79ae 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json index 8f7e730b..fb5a2a58 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G_2s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json index 315c3fce..378722ed 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G_3s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json index ae39db63..a79e2ea0 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G_mu", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json index 3020b53b..fca362ca 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json index 6867118b..f193410e 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G_2s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json index 2988bf90..69084ebe 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G_3s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json index c6dabf1d..9515ac0d 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json index 9aaa2c4c..eed0f3b5 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G_mu", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json index 0aef9bf9..9be74831 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-800_8bit_G", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 400 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json index b8cd6ba9..8d85c957 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 2, "nbrOfRows": 16384, - "width": 64 + "width": 64, + "NumberOfDevicesOnDIMM": 1, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json index d19953e5..589c2ef7 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 2, "nbrOfRows": 16384, - "width": 64 + "width": 64, + "NumberOfDevicesOnDIMM": 1, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2GB_DDR3-1066_64bit_G_UDIMM", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json index 2b954795..4b665ba4 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 2, "nbrOfRows": 16384, - "width": 64 + "width": 64, + "NumberOfDevicesOnDIMM": 1, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2GB_DDR3-1333_64bit_D_SODIMM", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 666 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json index ef9a59b8..f52937e5 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 2, "nbrOfRows": 16384, - "width": 64 + "width": 64, + "NumberOfDevicesOnDIMM": 1, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2GB_DDR3-1600_64bit_G_UDIMM", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json index f135a2e6..8247a00d 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json index 0cd99819..067f826b 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D_2s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json index 647e8938..2fba0c69 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D_3s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json index 1273f6e2..ada0ddbd 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D_mu", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json index a6a5a43a..c52f37bf 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 16 + "width": 16, + "NumberOfDevicesOnDIMM": 4, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json index 768b1cae..a0a6e4ea 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 16 + "width": 16, + "NumberOfDevicesOnDIMM": 4, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D_2s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json index a5b3a676..14bf56fa 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 16 + "width": 16, + "NumberOfDevicesOnDIMM": 4, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D_3s", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json index a6b86516..2809f069 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 16 + "width": 16, + "NumberOfDevicesOnDIMM": 4, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D_mu", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json index a75ff24b..579d540d 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json @@ -7,7 +7,8 @@ "nbrOfColumns": 2048, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 16 + "width": 16, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2Gb_LPDDR-266_16bit_A", "memoryType": "LPDDR", @@ -51,4 +52,4 @@ "clkMhz": 133 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json index 8b17dc3f..6038029c 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json @@ -7,7 +7,8 @@ "nbrOfColumns": 2048, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 16 + "width": 16, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2Gb_LPDDR-333_16bit_A", "memoryType": "LPDDR", @@ -51,4 +52,4 @@ "clkMhz": 166 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json index 8aadde0a..bb424df9 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json @@ -7,7 +7,8 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 16 + "width": 16, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2Gb_LPDDR2-1066-S4_16bit_A", "memoryType": "LPDDR2", @@ -64,4 +65,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json index ebe11f7a..4b6dbcf8 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json @@ -7,7 +7,8 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 16 + "width": 16, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_2Gb_LPDDR2-800-S4_16bit_A", "memoryType": "LPDDR2", @@ -64,4 +65,4 @@ "clkMhz": 400 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json index 11700aaf..9d837139 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json @@ -8,7 +8,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A", "memoryType": "DDR4", @@ -63,4 +65,4 @@ "clkMhz": 933 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json index ed4906cd..b1160755 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json @@ -8,7 +8,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 8 + "width": 8, + "NumberOfDevicesOnDIMM": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_4Gb_DDR4-2400_8bit_A", "memoryType": "DDR4", @@ -63,4 +65,4 @@ "clkMhz": 1200 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json index 35e1fe35..025531d1 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json @@ -7,7 +7,8 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 32 + "width": 32, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_4Gb_LPDDR3-1333_32bit_A", "memoryType": "LPDDR3", @@ -64,4 +65,4 @@ "clkMhz": 667 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json index 60d40c43..a9e32fdd 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json @@ -7,7 +7,8 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 16384, - "width": 32 + "width": 32, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_4Gb_LPDDR3-1600_32bit_A", "memoryType": "LPDDR3", @@ -64,4 +65,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json index 17638bb1..9faeea25 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json @@ -7,7 +7,8 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 49152, - "width": 16 + "width": 16, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_6Gb_LPDDR3-3200_16bit_A", "memoryType": "LPDDR4", @@ -92,4 +93,4 @@ "clkMhz": 1600 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json b/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json index 41f5cef2..628077a9 100644 --- a/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json +++ b/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 8192, - "width": 16 + "width": 16, + "NumberOfMemChannels": 1, + "NumberOfDevicesOnDIMM": 1, }, "memoryId": "SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json b/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json index ca86b2d5..7cb2625c 100644 --- a/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json +++ b/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json @@ -7,7 +7,9 @@ "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfRows": 32768, - "width": 16 + "width": 16, + "NumberOfDevicesOnDIMM": 1, + "NumberOfMemChannels": 1 }, "memoryId": "SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit", "memoryType": "DDR3", @@ -56,4 +58,4 @@ "clkMhz": 533 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.json b/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.json index 88044fdd..b7d49c2a 100644 --- a/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.json +++ b/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.json @@ -7,7 +7,8 @@ "nbrOfColumns": 1024, "nbrOfRanks": 4, "nbrOfRows": 16384, - "width": 8 + "width": 8, + "NumberOfMemChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G", "memoryType": "DDR3", @@ -56,4 +57,4 @@ "clkMhz": 800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/ddr3-single-device.json b/DRAMSys/library/resources/configs/simulator/ddr3-single-device.json index a1621422..de1a1bec 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr3-single-device.json +++ b/DRAMSys/library/resources/configs/simulator/ddr3-single-device.json @@ -8,8 +8,6 @@ "EnableWindowing": true, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1, "PowerAnalysis": true, "SimulationName": "ddr3_single_dev", "SimulationProgressBar": true, @@ -18,4 +16,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/ddr3.json b/DRAMSys/library/resources/configs/simulator/ddr3.json index 4e9faadc..99ccdb45 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr3.json +++ b/DRAMSys/library/resources/configs/simulator/ddr3.json @@ -8,8 +8,6 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, "PowerAnalysis": false, "SimulationName": "ddr3", "SimulationProgressBar": true, diff --git a/DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.json b/DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.json index fd35bdee..d885c677 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.json +++ b/DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.json @@ -8,8 +8,6 @@ "EnableWindowing": true, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, "PowerAnalysis": true, "SimulationName": "ddr3", "SimulationProgressBar": true, @@ -18,4 +16,4 @@ "UseMalloc": true, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/ddr3_ecc.json b/DRAMSys/library/resources/configs/simulator/ddr3_ecc.json index 2b813f99..e148c3aa 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr3_ecc.json +++ b/DRAMSys/library/resources/configs/simulator/ddr3_ecc.json @@ -8,8 +8,6 @@ "EnableWindowing": true, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, "PowerAnalysis": true, "SimulationName": "ddr3", "SimulationProgressBar": true, @@ -18,4 +16,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.json b/DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.json index 72ebcf9b..c0b12f97 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.json +++ b/DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.json @@ -8,8 +8,6 @@ "EnableWindowing": true, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, "PowerAnalysis": true, "SimulationName": "ddr3", "SimulationProgressBar": true, @@ -18,4 +16,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/ddr4.json b/DRAMSys/library/resources/configs/simulator/ddr4.json index 8e62e680..05cd86e2 100644 --- a/DRAMSys/library/resources/configs/simulator/ddr4.json +++ b/DRAMSys/library/resources/configs/simulator/ddr4.json @@ -8,8 +8,6 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1, "PowerAnalysis": false, "SimulationName": "ddr4", "SimulationProgressBar": true, @@ -18,4 +16,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/hbm2.json b/DRAMSys/library/resources/configs/simulator/hbm2.json index 9589611f..608aec41 100644 --- a/DRAMSys/library/resources/configs/simulator/hbm2.json +++ b/DRAMSys/library/resources/configs/simulator/hbm2.json @@ -8,8 +8,6 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1, "PowerAnalysis": false, "SimulationName": "hbm2", "SimulationProgressBar": true, @@ -18,4 +16,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/lpddr4.json b/DRAMSys/library/resources/configs/simulator/lpddr4.json index fd8fe855..ee38bd66 100644 --- a/DRAMSys/library/resources/configs/simulator/lpddr4.json +++ b/DRAMSys/library/resources/configs/simulator/lpddr4.json @@ -8,7 +8,6 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, "NumberOfMemChannels": 1, "PowerAnalysis": false, "SimulationName": "lpddr4", @@ -18,4 +17,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/wideio.json b/DRAMSys/library/resources/configs/simulator/wideio.json index 4a0bd0ee..0c285f79 100644 --- a/DRAMSys/library/resources/configs/simulator/wideio.json +++ b/DRAMSys/library/resources/configs/simulator/wideio.json @@ -7,8 +7,6 @@ "EnableWindowing": true, "ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 4, "PowerAnalysis": true, "SimulationName": "wideio", "SimulationProgressBar": true, @@ -17,4 +15,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/wideio_ecc.json b/DRAMSys/library/resources/configs/simulator/wideio_ecc.json index 216d3623..80acc3be 100644 --- a/DRAMSys/library/resources/configs/simulator/wideio_ecc.json +++ b/DRAMSys/library/resources/configs/simulator/wideio_ecc.json @@ -7,8 +7,6 @@ "EnableWindowing": true, "ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1, "PowerAnalysis": true, "SimulationName": "wideio_ecc", "SimulationProgressBar": true, @@ -17,4 +15,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/simulator/wideio_thermal.json b/DRAMSys/library/resources/configs/simulator/wideio_thermal.json index 6a47ff5b..b37cda4f 100644 --- a/DRAMSys/library/resources/configs/simulator/wideio_thermal.json +++ b/DRAMSys/library/resources/configs/simulator/wideio_thermal.json @@ -7,8 +7,6 @@ "EnableWindowing": true, "ErrorCSVFile": "../../DRAMSys/library/resources/error/wideio.csv", "ErrorChipSeed": 42, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 4, "PowerAnalysis": true, "SimulationName": "wideio", "SimulationProgressBar": true, @@ -17,4 +15,4 @@ "UseMalloc": false, "WindowSize": 1000 } -} \ No newline at end of file +} diff --git a/DRAMSys/tests/DDR4/configs/mcconfigs/fr_fcfs.json b/DRAMSys/tests/DDR4/configs/mcconfigs/fr_fcfs.json index 2da01ceb..5eea8b88 100644 --- a/DRAMSys/tests/DDR4/configs/mcconfigs/fr_fcfs.json +++ b/DRAMSys/tests/DDR4/configs/mcconfigs/fr_fcfs.json @@ -6,7 +6,7 @@ "RespQueue": "Fifo", "RefreshPolicy": "Rankwise", "RefreshMode": 1, - "RefreshMaxPostponed": 128, - "RefreshMaxPulledin": 128, + "RefreshMaxPostponed": 8, + "RefreshMaxPulledin": 8, "PowerDownPolicy": "NoPowerDown", "PowerDownTimeout": 100}} diff --git a/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json b/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json index 5014ff9a..933baeba 100644 --- a/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json +++ b/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json @@ -10,7 +10,6 @@ "nbrOfChannels": 1, "nbrOfRows": 32768, "width": 64, - "NumberOfDevicesOnDIMM": 1, "NumberOfMemChannels": 1 }, "memoryId": "https://www.computerbase.de/2019-05/amd-memory-tweak-vram-oc/#bilder", diff --git a/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json b/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json index 08e13043..0c90c3ca 100644 --- a/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json +++ b/DRAMSys/tests/ddr3_multirank/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json @@ -8,8 +8,8 @@ "nbrOfRanks": 2, "nbrOfChannels": 1, "nbrOfRows": 16384, - "width": 8, - "nbrOfDevicesOnDIMM": 8 + "width": 64, + "nbrOfDevicesOnDIMM": 1 }, "memoryId": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM", "memoryType": "DDR3", From 5cbfa36339d5b73788e0b330d490b3c30104784e Mon Sep 17 00:00:00 2001 From: scorrea Date: Thu, 18 Jun 2020 12:39:50 +0200 Subject: [PATCH 08/34] PAGE POLICIES AND TRACES MODIFIED --- DRAMSys/tests/DDR4/configs/mcconfigs/fr_fcfs.json | 2 +- DRAMSys/tests/lpddr4/configs/mcconfigs/fifo.json | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/DRAMSys/tests/DDR4/configs/mcconfigs/fr_fcfs.json b/DRAMSys/tests/DDR4/configs/mcconfigs/fr_fcfs.json index 5eea8b88..01603197 100644 --- a/DRAMSys/tests/DDR4/configs/mcconfigs/fr_fcfs.json +++ b/DRAMSys/tests/DDR4/configs/mcconfigs/fr_fcfs.json @@ -1,5 +1,5 @@ {"mcconfig": { - "PagePolicy": "Open", + "PagePolicy": "ClosedAdaptive", "Scheduler": "FrFcfs", "RequestBufferSize": 8, "CmdMux": "Oldest", diff --git a/DRAMSys/tests/lpddr4/configs/mcconfigs/fifo.json b/DRAMSys/tests/lpddr4/configs/mcconfigs/fifo.json index 712e1c96..59b55965 100644 --- a/DRAMSys/tests/lpddr4/configs/mcconfigs/fifo.json +++ b/DRAMSys/tests/lpddr4/configs/mcconfigs/fifo.json @@ -1,4 +1,4 @@ -{"mcconfig": {"PagePolicy": "Open", +{"mcconfig": {"PagePolicy": "OpenAdaptive", "Scheduler": "Fifo", "RequestBufferSize": 8, "CmdMux": "Oldest", From 81c67fb1d3491ba983029f949fa9e7d41f0bf7b1 Mon Sep 17 00:00:00 2001 From: scorrea Date: Thu, 18 Jun 2020 15:45:27 +0200 Subject: [PATCH 09/34] NumberOfMemChannels to nbrOfChannels --- DRAMSys/library/resources/configs/memspecs/HBM2.json | 2 +- .../configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json | 2 +- .../configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json | 2 +- .../configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json | 4 ++-- .../configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json | 4 ++-- .../configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json | 2 +- .../configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json | 2 +- .../configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json | 2 +- .../configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json | 2 +- .../configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json | 2 +- .../configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json | 4 ++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json | 4 ++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json | 4 ++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json | 4 ++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json | 4 ++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json | 4 ++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json | 4 ++-- .../configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json | 4 ++-- .../configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json | 4 ++-- .../configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json | 4 ++-- .../configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json | 4 ++-- .../memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json | 4 ++-- .../configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json | 4 ++-- .../configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json | 4 ++-- .../configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json | 4 ++-- .../configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json | 4 ++-- .../configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json | 4 ++-- .../configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json | 4 ++-- .../configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json | 4 ++-- .../configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json | 4 ++-- .../configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json | 4 ++-- .../configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json | 4 ++-- .../configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json | 4 ++-- .../configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json | 4 ++-- .../configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json | 4 ++-- .../configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json | 4 ++-- .../configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json | 2 +- .../configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json | 2 +- .../configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json | 2 +- .../configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json | 2 +- .../configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json | 4 ++-- .../configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json | 4 ++-- .../configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json | 2 +- .../configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json | 2 +- .../configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json | 2 +- .../memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json | 4 ++-- .../memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json | 4 ++-- .../library/resources/configs/memspecs/memspec_ranktest.json | 2 +- 48 files changed, 80 insertions(+), 80 deletions(-) diff --git a/DRAMSys/library/resources/configs/memspecs/HBM2.json b/DRAMSys/library/resources/configs/memspecs/HBM2.json index bc9faa23..0f60243d 100644 --- a/DRAMSys/library/resources/configs/memspecs/HBM2.json +++ b/DRAMSys/library/resources/configs/memspecs/HBM2.json @@ -9,7 +9,7 @@ "nbrOfRanks": 2, "nbrOfRows": 32768, "width": 64, - "NumberOfMemChannels": 1 + "nbrOfChannels": 1 }, "memoryId": "https://www.computerbase.de/2019-05/amd-memory-tweak-vram-oc/#bilder", "memoryType": "HBM2", diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json index 17630099..114a76fb 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json @@ -8,7 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 4096, "width": 128, - "NumberOfMemChannels": 4 + "nbrOfChannels": 4 }, "memoryId": "JEDEC_256Mb_WIDEIO_SDR-200_128bit", "memoryType": "WIDEIO_SDR", diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json index 7f576e12..8ef5ffe8 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json @@ -8,7 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 4096, "width": 128, - "NumberOfMemChannels": 4 + "nbrOfChannels": 4 }, "memoryId": "JEDEC_256Mb_WIDEIO_SDR-266_128bit", "memoryType": "WIDEIO_SDR", diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json index db212fc7..8343c6f8 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json @@ -9,8 +9,8 @@ "nbrOfRanks": 1, "nbrOfRows": 32768, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A", "memoryType": "DDR4", diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json index 9ea5ca87..1e16ea82 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json @@ -9,8 +9,8 @@ "nbrOfRanks": 1, "nbrOfRows": 32768, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_4Gb_DDR4-2400_8bit_A", "memoryType": "DDR4", diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json index 29e9f3d6..04886e6b 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json @@ -8,7 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 8192, "width": 64, - "NumberOfMemChannels": 4 + "nbrOfChannels": 4 }, "memoryId": "JEDEC_4x64_2Gb_WIDEIO2-400_64bit", "memoryType": "WIDEIO2", diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json index 16f3546f..fc6aab68 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json @@ -8,7 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 8192, "width": 64, - "NumberOfMemChannels": 4 + "nbrOfChannels": 4 }, "memoryId": "JEDEC_4x64_2Gb_WIDEIO2-533_64bit", "memoryType": "WIDEIO2", diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json index 6504cd54..03008970 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json @@ -8,7 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 65536, "width": 16, - "NumberOfMemChannels": 1 + "nbrOfChannels": 1 }, "memoryId": "JEDEC_8Gb_LPDDR4-3200_16bit", "memoryType": "LPDDR4", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json index 42692386..60ef5c90 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json @@ -8,7 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 8192, "width": 16, - "NumberOfMemChannels": 1 + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR2-1066_16bit_H", "memoryType": "DDR2", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json index 3cbdec2d..77317ff8 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json @@ -8,7 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 8192, "width": 16, - "NumberOfMemChannels": 1 + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR2-800_16bit_H", "memoryType": "DDR2", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json index 0e15b9b3..06f79649 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 8192, "width": 16, - "NumberOfDevicesOnDIMM": 4, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json index f6557d3d..dfd064bf 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 8192, "width": 16, - "NumberOfDevicesOnDIMM": 4, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G_2s", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json index f8b477bb..8a40d4d0 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 8192, "width": 16, - "NumberOfDevicesOnDIMM": 4, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G_3s", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json index fe0feff6..989c7697 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 8192, "width": 16, - "NumberOfDevicesOnDIMM": 4, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_16bit_G_mu", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json index 549f79ae..5a96131d 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json index fb5a2a58..4ef0bc5b 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G_2s", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json index 378722ed..c28ed4b3 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G_3s", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json index a79e2ea0..16d6d572 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1066_8bit_G_mu", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json index fca362ca..9d4d682c 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json index f193410e..379cd55d 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G_2s", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json index 69084ebe..e3a00e86 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G_3s", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json index 9515ac0d..fd672487 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json index eed0f3b5..061219e6 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G_mu", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json index 9be74831..ceace84b 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-800_8bit_G", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json index 8d85c957..947f6aa4 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json @@ -8,8 +8,8 @@ "nbrOfRanks": 2, "nbrOfRows": 16384, "width": 64, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 1, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2GB_DDR3-1066_64bit_D_SODIMM", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json index 589c2ef7..4a249d45 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json @@ -8,8 +8,8 @@ "nbrOfRanks": 2, "nbrOfRows": 16384, "width": 64, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 1, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2GB_DDR3-1066_64bit_G_UDIMM", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json index 4b665ba4..c9927028 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json @@ -8,8 +8,8 @@ "nbrOfRanks": 2, "nbrOfRows": 16384, "width": 64, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 1, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2GB_DDR3-1333_64bit_D_SODIMM", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json index f52937e5..cfca2ccd 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json @@ -8,8 +8,8 @@ "nbrOfRanks": 2, "nbrOfRows": 16384, "width": 64, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 1, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2GB_DDR3-1600_64bit_G_UDIMM", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json index 8247a00d..bb451167 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 32768, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json index 067f826b..7ac094bc 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 32768, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D_2s", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json index 2fba0c69..f16c8d27 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 32768, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D_3s", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json index ada0ddbd..e962654a 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 32768, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1066_8bit_D_mu", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json index c52f37bf..d404eba9 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 16, - "NumberOfDevicesOnDIMM": 4, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json index a0a6e4ea..949cd56e 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 16, - "NumberOfDevicesOnDIMM": 4, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D_2s", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json index 14bf56fa..2da4909c 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 16, - "NumberOfDevicesOnDIMM": 4, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D_3s", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json index 2809f069..dfc21103 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 16, - "NumberOfDevicesOnDIMM": 4, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 4, + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_DDR3-1600_16bit_D_mu", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json index 579d540d..f7c989f9 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json @@ -8,7 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 16, - "NumberOfMemChannels": 1 + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_LPDDR-266_16bit_A", "memoryType": "LPDDR", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json index 6038029c..2e271810 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json @@ -8,7 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 16, - "NumberOfMemChannels": 1 + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_LPDDR-333_16bit_A", "memoryType": "LPDDR", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json index bb424df9..638afb58 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json @@ -8,7 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 16, - "NumberOfMemChannels": 1 + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_LPDDR2-1066-S4_16bit_A", "memoryType": "LPDDR2", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json index 4b6dbcf8..fa1a357c 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json @@ -8,7 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 16, - "NumberOfMemChannels": 1 + "nbrOfChannels": 1 }, "memoryId": "MICRON_2Gb_LPDDR2-800-S4_16bit_A", "memoryType": "LPDDR2", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json index 9d837139..7afe6d81 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json @@ -9,8 +9,8 @@ "nbrOfRanks": 1, "nbrOfRows": 32768, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_4Gb_DDR4-1866_8bit_A", "memoryType": "DDR4", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json index b1160755..0406d803 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json @@ -9,8 +9,8 @@ "nbrOfRanks": 1, "nbrOfRows": 32768, "width": 8, - "NumberOfDevicesOnDIMM": 8, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 8, + "nbrOfChannels": 1 }, "memoryId": "MICRON_4Gb_DDR4-2400_8bit_A", "memoryType": "DDR4", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json index 025531d1..9bee9f8b 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json @@ -8,7 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 32, - "NumberOfMemChannels": 1 + "nbrOfChannels": 1 }, "memoryId": "MICRON_4Gb_LPDDR3-1333_32bit_A", "memoryType": "LPDDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json index a9e32fdd..87f5047e 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json @@ -8,7 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 16384, "width": 32, - "NumberOfMemChannels": 1 + "nbrOfChannels": 1 }, "memoryId": "MICRON_4Gb_LPDDR3-1600_32bit_A", "memoryType": "LPDDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json b/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json index 9faeea25..1d61ae45 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json @@ -8,7 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 49152, "width": 16, - "NumberOfMemChannels": 1 + "nbrOfChannels": 1 }, "memoryId": "MICRON_6Gb_LPDDR3-3200_16bit_A", "memoryType": "LPDDR4", diff --git a/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json b/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json index 628077a9..2706f93d 100644 --- a/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json +++ b/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 8192, "width": 16, - "NumberOfMemChannels": 1, - "NumberOfDevicesOnDIMM": 1, + "nbrOfChannels": 1, + "nbrOfDevicesOnDIMM": 1, }, "memoryId": "SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json b/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json index 7cb2625c..a58d953a 100644 --- a/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json +++ b/DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json @@ -8,8 +8,8 @@ "nbrOfRanks": 1, "nbrOfRows": 32768, "width": 16, - "NumberOfDevicesOnDIMM": 1, - "NumberOfMemChannels": 1 + "nbrOfDevicesOnDIMM": 1, + "nbrOfChannels": 1 }, "memoryId": "SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit", "memoryType": "DDR3", diff --git a/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.json b/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.json index b7d49c2a..3faa3399 100644 --- a/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.json +++ b/DRAMSys/library/resources/configs/memspecs/memspec_ranktest.json @@ -8,7 +8,7 @@ "nbrOfRanks": 4, "nbrOfRows": 16384, "width": 8, - "NumberOfMemChannels": 1 + "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR3-1600_8bit_G", "memoryType": "DDR3", From 54f3285b17bebbf28580f00034edc6f36c653891 Mon Sep 17 00:00:00 2001 From: scorrea Date: Sat, 20 Jun 2020 16:12:35 +0200 Subject: [PATCH 10/34] HBM2 test to dual-channel/ DDR2 memspecs updated --- .../MICRON_1Gb_DDR2-1066_16bit_H.json | 1 + .../memspecs/MICRON_1Gb_DDR2-800_16bit_H.json | 1 + .../configs/amconfigs/am_hbm2_8Gb_pc_brc.json | 23 ++++++++++--------- DRAMSys/tests/HBM2/configs/memspecs/HBM2.json | 7 +++--- 4 files changed, 17 insertions(+), 15 deletions(-) diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json index 60ef5c90..0554838d 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json @@ -8,6 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 8192, "width": 16, + "nbrOfDevicesOnDIMM": 4, "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR2-1066_16bit_H", diff --git a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json index 77317ff8..d54ddb75 100644 --- a/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json +++ b/DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json @@ -8,6 +8,7 @@ "nbrOfRanks": 1, "nbrOfRows": 8192, "width": 16, + "nbrOfDevicesOnDIMM": 4, "nbrOfChannels": 1 }, "memoryId": "MICRON_1Gb_DDR2-800_16bit_H", diff --git a/DRAMSys/tests/HBM2/configs/amconfigs/am_hbm2_8Gb_pc_brc.json b/DRAMSys/tests/HBM2/configs/amconfigs/am_hbm2_8Gb_pc_brc.json index 354217a5..c9362ea4 100644 --- a/DRAMSys/tests/HBM2/configs/amconfigs/am_hbm2_8Gb_pc_brc.json +++ b/DRAMSys/tests/HBM2/configs/amconfigs/am_hbm2_8Gb_pc_brc.json @@ -1,32 +1,32 @@ { "CONGEN": { - "RANK_BIT":[ - 29 + "CHANNEL_BIT":[ + 30 ], "BANKGROUP_BIT":[ - 27, - 28 + 28, + 29 ], "BANK_BIT": [ - 25, - 26 + 26, + 27 ], "BYTE_BIT": [ 0, 1, - 2 + 2, + 3 ], "COLUMN_BIT": [ - 3, 4, 5, 6, 7, 8, - 9 + 9, + 10 ], "ROW_BIT": [ - 10, 11, 12, 13, @@ -40,7 +40,8 @@ 21, 22, 23, - 24 + 24, + 25 ] } } diff --git a/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json b/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json index 933baeba..c10d1242 100644 --- a/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json +++ b/DRAMSys/tests/HBM2/configs/memspecs/HBM2.json @@ -6,11 +6,10 @@ "nbrOfBankGroups": 4, "nbrOfBanks": 16, "nbrOfColumns": 128, - "nbrOfRanks": 2, - "nbrOfChannels": 1, + "nbrOfRanks": 1, + "nbrOfChannels": 2, "nbrOfRows": 32768, - "width": 64, - "NumberOfMemChannels": 1 + "width": 128 }, "memoryId": "https://www.computerbase.de/2019-05/amd-memory-tweak-vram-oc/#bilder", "memoryType": "HBM2", From c016959d50498e706857fd70b51c5536c00eb5c5 Mon Sep 17 00:00:00 2001 From: scorrea Date: Tue, 23 Jun 2020 11:09:17 +0200 Subject: [PATCH 11/34] traceAnalyzer tests excluded from ci tests --- DRAMSys/tests/DDR4/ci.yml | 4 ++-- DRAMSys/tests/HBM2/ci.yml | 6 ++++-- DRAMSys/tests/ddr3_multirank/ci.yml | 4 ++-- DRAMSys/tests/lpddr4/ci.yml | 4 ++-- 4 files changed, 10 insertions(+), 8 deletions(-) diff --git a/DRAMSys/tests/DDR4/ci.yml b/DRAMSys/tests/DDR4/ci.yml index d6226908..94dc5d4c 100644 --- a/DRAMSys/tests/DDR4/ci.yml +++ b/DRAMSys/tests/DDR4/ci.yml @@ -10,8 +10,8 @@ example_ddr4: - ls -lah ../../DRAMSys/tests/DDR4/expected/ - sqldiff ../../DRAMSys/tests/DDR4/expected/ddr4-bankgrp_ddr4_ch0.tdb ddr4-bankgrp_ddr4_ch0.tdb - perl -e 'if(`sqldiff ../../DRAMSys/tests/DDR4/expected/ddr4-bankgrp_ddr4_ch0.tdb ddr4-bankgrp_ddr4_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' - - cd ../traceAnalyzer - - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/ddr4-bankgrp_ddr4_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi + #- cd ../traceAnalyzer + #- python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/ddr4-bankgrp_ddr4_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi # Run Code Coverage - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out diff --git a/DRAMSys/tests/HBM2/ci.yml b/DRAMSys/tests/HBM2/ci.yml index fb9474a1..80a4b981 100644 --- a/DRAMSys/tests/HBM2/ci.yml +++ b/DRAMSys/tests/HBM2/ci.yml @@ -10,8 +10,10 @@ example_HBM2: - ls -lah ../../DRAMSys/tests/HBM2/expected/ - sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch0.tdb hbm2-example_hbm2_ch0.tdb - perl -e 'if(`sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch0.tdb hbm2-example_hbm2_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' - - cd ../traceAnalyzer - - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/hbm2-example_hbm2_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi + - sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch1.tdb hbm2-example_hbm2_ch1.tdb + - perl -e 'if(`sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch1.tdb hbm2-example_hbm2_ch1.tdb` eq "") {exit(0)} else {exit(-1)}' + #- cd ../traceAnalyzer + #- python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/hbm2-example_hbm2_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi # Run Code Coverage - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out diff --git a/DRAMSys/tests/ddr3_multirank/ci.yml b/DRAMSys/tests/ddr3_multirank/ci.yml index da90393a..941a2aee 100644 --- a/DRAMSys/tests/ddr3_multirank/ci.yml +++ b/DRAMSys/tests/ddr3_multirank/ci.yml @@ -10,8 +10,8 @@ example_ddr3: - ls -lah ../../DRAMSys/tests/ddr3_multirank/expected/ - sqldiff ../../DRAMSys/tests/ddr3_multirank/expected/ddr3-dual-rank_ddr3_ch0.tdb ddr3-dual-rank_ddr3_ch0.tdb - perl -e 'if(`sqldiff ../../DRAMSys/tests/ddr3_multirank/expected/ddr3-dual-rank_ddr3_ch0.tdb ddr3-dual-rank_ddr3_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' - - cd ../traceAnalyzer - - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/ddr3_multirank_ddr3_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi + #- cd ../traceAnalyzer + #- python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/ddr3_multirank_ddr3_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi # Run Code Coverage - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out diff --git a/DRAMSys/tests/lpddr4/ci.yml b/DRAMSys/tests/lpddr4/ci.yml index 40860f3f..ff811142 100644 --- a/DRAMSys/tests/lpddr4/ci.yml +++ b/DRAMSys/tests/lpddr4/ci.yml @@ -10,8 +10,8 @@ example_lpddr4: - ls -lah ../../DRAMSys/tests/lpddr4/expected/ - sqldiff ../../DRAMSys/tests/lpddr4/expected/lpddr4-example_lpddr4_ch0.tdb lpddr4-example_lpddr4_ch0.tdb - perl -e 'if(`sqldiff ../../DRAMSys/tests/lpddr4/expected/lpddr4-example_lpddr4_ch0.tdb lpddr4-example_lpddr4_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' - - cd ../traceAnalyzer - - python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/lpddr4-example_lpddr4_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi + #- cd ../traceAnalyzer + #- python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/lpddr4-example_lpddr4_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi # Run Code Coverage - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out From 26c2c7f66fe3aa78ca2adaa942edc5cb140d2684 Mon Sep 17 00:00:00 2001 From: scorrea Date: Tue, 23 Jun 2020 11:45:54 +0200 Subject: [PATCH 12/34] HBM2 ci.yml correction --- DRAMSys/tests/HBM2/ci.yml | 54 +++++++++++++++++---------------------- 1 file changed, 24 insertions(+), 30 deletions(-) diff --git a/DRAMSys/tests/HBM2/ci.yml b/DRAMSys/tests/HBM2/ci.yml index 80a4b981..1f34b6d1 100644 --- a/DRAMSys/tests/HBM2/ci.yml +++ b/DRAMSys/tests/HBM2/ci.yml @@ -1,31 +1,25 @@ -# HBM2 test with 4 bank groups, 2 trace players, fifo strict scheduler and closed pg policy.: -example_HBM2: - stage: HBM2 - script: - - export GCOV_PREFIX=$(pwd) - - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') - - cd build/simulator - - ./DRAMSys ../../DRAMSys/tests/HBM2/simulations/hbm2-example.json ../../DRAMSys/tests/HBM2/ - - ls -lah - - ls -lah ../../DRAMSys/tests/HBM2/expected/ - - sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch0.tdb hbm2-example_hbm2_ch0.tdb - - perl -e 'if(`sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch0.tdb hbm2-example_hbm2_ch0.tdb` eq "") {exit(0)} else {exit(-1)}' - - sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch1.tdb hbm2-example_hbm2_ch1.tdb - - perl -e 'if(`sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch1.tdb hbm2-example_hbm2_ch1.tdb` eq "") {exit(0)} else {exit(-1)}' - #- cd ../traceAnalyzer - #- python3 ../../DRAMSys/traceAnalyzer/scripts/tests.py ../simulator/hbm2-example_hbm2_ch0.tdb | if ! grep "failed"; then exit 0; else exit 1; fi - # Run Code Coverage - - lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out - - cache: - key: build - paths: - - build/ - policy: pull - - artifacts: - paths: - - build/simulator/hbm2-example_hbm2_ch0.tdb - - coverage/${CI_JOB_NAME}.out - expire_in: 2 days +example_HBM2: + artifacts: + expire_in: "2 days" + paths: + - build/simulator/hbm2-example_hbm2_ch0.tdb + - "coverage/${CI_JOB_NAME}.out" + cache: + key: build + paths: + - build/ + policy: pull + script: + - "export GCOV_PREFIX=$(pwd)" + - "export GCOV_PREFIX_STRIP=$(pwd | awk -F\"/\" '{print NF-1}')" + - "cd build/simulator" + - "./DRAMSys ../../DRAMSys/tests/HBM2/simulations/hbm2-example.json ../../DRAMSys/tests/HBM2/" + - "ls -lah" + - "ls -lah ../../DRAMSys/tests/HBM2/expected/" + - "sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch0.tdb hbm2-example_hbm2_ch0.tdb" + - "perl -e 'if(`sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch0.tdb hbm2-example_hbm2_ch0.tdb` eq \"\") {exit(0)} else {exit(-1)}'" + - "sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch1.tdb hbm2-example_hbm2_ch1.tdb" + - "perl -e 'if(`sqldiff ../../DRAMSys/tests/HBM2/expected/hbm2-example_hbm2_ch1.tdb hbm2-example_hbm2_ch1.tdb` eq \"\") {exit(0)} else {exit(-1)}'" + - "lcov -q -c --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR}/build/ -o ${CI_PROJECT_DIR}/coverage/${CI_JOB_NAME}.out" + stage: HBM2 From 4cf1f2c0b4cebee0d80d81870e72247ba0627d19 Mon Sep 17 00:00:00 2001 From: scorrea Date: Tue, 23 Jun 2020 12:07:02 +0200 Subject: [PATCH 13/34] .tdb in expected folders excluded from gitignore --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 99b20805..118c019c 100644 --- a/.gitignore +++ b/.gitignore @@ -5,6 +5,7 @@ /dram/build *.user *.tdb +!/DRAMSys/tests/*/expected/*.tdb *.tdb-journal *.out /build-simulation From 2e5483e122f7b3b24b9fb2e8c750208bb057f22b Mon Sep 17 00:00:00 2001 From: scorrea Date: Wed, 24 Jun 2020 16:15:43 +0200 Subject: [PATCH 14/34] ddr3 ci.yml file corrected --- DRAMSys/tests/ddr3_multirank/ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/DRAMSys/tests/ddr3_multirank/ci.yml b/DRAMSys/tests/ddr3_multirank/ci.yml index 941a2aee..ea32584e 100644 --- a/DRAMSys/tests/ddr3_multirank/ci.yml +++ b/DRAMSys/tests/ddr3_multirank/ci.yml @@ -5,7 +5,7 @@ example_ddr3: - export GCOV_PREFIX=$(pwd) - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') - cd build/simulator - - ./DRAMSys ../../DRAMSys/tests/ddr3_multirank/ddr3-example.json ../../DRAMSys/tests/ddr3_multirank/ + - ./DRAMSys ../../DRAMSys/tests/ddr3_multirank/simulations/ddr3-example.json ../../DRAMSys/tests/ddr3_multirank/ - ls -lah - ls -lah ../../DRAMSys/tests/ddr3_multirank/expected/ - sqldiff ../../DRAMSys/tests/ddr3_multirank/expected/ddr3-dual-rank_ddr3_ch0.tdb ddr3-dual-rank_ddr3_ch0.tdb From 542a7d9f3216f289ae6696f24a3df605cbb598fe Mon Sep 17 00:00:00 2001 From: scorrea Date: Wed, 24 Jun 2020 17:53:56 +0200 Subject: [PATCH 15/34] gcov option passed to GCC --- .gitlab-ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 800215b0..76dbafb4 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -20,7 +20,7 @@ build: - rm -rf build - mkdir -p build - cd build - - cmake ../DRAMSys + - cmake -Wl,-fprofile-arcs,-ftest-coverage ../DRAMSys - make -j16 - find . -name "*.o" -type f -delete - rm -rf ${CI_PROJECT_DIR}/coverage From 8ed64a85cfa05f161692a72b8bc882e77fbd7422 Mon Sep 17 00:00:00 2001 From: scorrea Date: Wed, 24 Jun 2020 18:05:01 +0200 Subject: [PATCH 16/34] --coverage option --- .gitlab-ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 76dbafb4..ae825116 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -20,7 +20,7 @@ build: - rm -rf build - mkdir -p build - cd build - - cmake -Wl,-fprofile-arcs,-ftest-coverage ../DRAMSys + - cmake --coverage ../DRAMSys - make -j16 - find . -name "*.o" -type f -delete - rm -rf ${CI_PROJECT_DIR}/coverage From 5a75a627609afa9263360747786ad9cf740b56a0 Mon Sep 17 00:00:00 2001 From: scorrea Date: Wed, 24 Jun 2020 18:35:50 +0200 Subject: [PATCH 17/34] coverage flags changed --- .gitlab-ci.yml | 2 +- DRAMSys/CMakeLists.txt | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index ae825116..800215b0 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -20,7 +20,7 @@ build: - rm -rf build - mkdir -p build - cd build - - cmake --coverage ../DRAMSys + - cmake ../DRAMSys - make -j16 - find . -name "*.o" -type f -delete - rm -rf ${CI_PROJECT_DIR}/coverage diff --git a/DRAMSys/CMakeLists.txt b/DRAMSys/CMakeLists.txt index 6a50c48c..f5cb1045 100644 --- a/DRAMSys/CMakeLists.txt +++ b/DRAMSys/CMakeLists.txt @@ -39,6 +39,11 @@ project(DRAMSys) set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version") set(DCMAKE_SH "CMAKE_SH-NOTFOUND" CACHE STRING "Ignore sh.exe error on Windows") +SET(GCC_COVERAGE_COMPILE_FLAGS "-g -O0 -coverage -fprofile-arcs -ftest-coverage") +SET(GCC_COVERAGE_LINK_FLAGS "-coverage -lgcov") +SET( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}" ) +SET( CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${GCC_COVERAGE_LINK_FLAGS}") + # Add DRAMSysLibrary: add_subdirectory(library) @@ -54,3 +59,4 @@ add_subdirectory(simulator) if(DEFINED ENV{GEM5}) add_subdirectory(gem5) endif() + From 416b1bbcc717d8b447fbe76d16753b3ff0e44510 Mon Sep 17 00:00:00 2001 From: scorrea Date: Fri, 26 Jun 2020 09:43:13 +0200 Subject: [PATCH 18/34] coverage added to CMakelists --- DRAMSys/CMakeLists.txt | 2 +- DRAMSys/library/CMakeLists.txt | 6 ++++++ DRAMSys/simulator/CMakeLists.txt | 5 +++++ 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/DRAMSys/CMakeLists.txt b/DRAMSys/CMakeLists.txt index f5cb1045..ec99b946 100644 --- a/DRAMSys/CMakeLists.txt +++ b/DRAMSys/CMakeLists.txt @@ -38,12 +38,12 @@ project(DRAMSys) # Configuration: set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version") set(DCMAKE_SH "CMAKE_SH-NOTFOUND" CACHE STRING "Ignore sh.exe error on Windows") - SET(GCC_COVERAGE_COMPILE_FLAGS "-g -O0 -coverage -fprofile-arcs -ftest-coverage") SET(GCC_COVERAGE_LINK_FLAGS "-coverage -lgcov") SET( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}" ) SET( CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${GCC_COVERAGE_LINK_FLAGS}") + # Add DRAMSysLibrary: add_subdirectory(library) diff --git a/DRAMSys/library/CMakeLists.txt b/DRAMSys/library/CMakeLists.txt index d15862ed..a8301da7 100644 --- a/DRAMSys/library/CMakeLists.txt +++ b/DRAMSys/library/CMakeLists.txt @@ -38,6 +38,12 @@ project(DRAMSysLibrary) # Configuration: set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version") set(DCMAKE_SH="CMAKE_SH-NOTFOUND") +SET(GCC_COVERAGE_COMPILE_FLAGS "-g -O0 -coverage -fprofile-arcs -ftest-coverage") +SET(GCC_COVERAGE_LINK_FLAGS "-coverage -lgcov") +SET( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}" ) +SET( CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${GCC_COVERAGE_LINK_FLAGS}") + + # Add DRAMPower: add_subdirectory(src/common/third_party/DRAMPower) diff --git a/DRAMSys/simulator/CMakeLists.txt b/DRAMSys/simulator/CMakeLists.txt index 23c68f3a..fad8af38 100644 --- a/DRAMSys/simulator/CMakeLists.txt +++ b/DRAMSys/simulator/CMakeLists.txt @@ -38,6 +38,11 @@ project(DRAMSysSimulator) # Configuration: set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version") set(DCMAKE_SH="CMAKE_SH-NOTFOUND") +SET(GCC_COVERAGE_COMPILE_FLAGS "-g -O0 -coverage -fprofile-arcs -ftest-coverage") +SET(GCC_COVERAGE_LINK_FLAGS "-coverage -lgcov") +SET( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}" ) +SET( CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${GCC_COVERAGE_LINK_FLAGS}") + if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/../library/src/simulation/DRAMSysRecordable.cpp) add_definitions(-DRECORDING) From 1751e0c6cd92a6f4171471a0e85607398e2967a8 Mon Sep 17 00:00:00 2001 From: scorrea Date: Fri, 26 Jun 2020 11:22:53 +0200 Subject: [PATCH 19/34] ci build and path updated --- .gitlab-ci.yml | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 800215b0..e77b5f89 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -25,6 +25,12 @@ build: - find . -name "*.o" -type f -delete - rm -rf ${CI_PROJECT_DIR}/coverage - mkdir -p ${CI_PROJECT_DIR}/coverage + - cd ${CI_PROJECT_DIR} + - export GCOV_PREFIX=$(pwd) + - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') + - lcov -q -c --initial --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR} -o ${CI_PROJECT_DIR}/coverage/base.out + + cache: key: build @@ -34,21 +40,28 @@ build: artifacts: paths: - - coverage/ + - coverage/base.out coverage: stage: Coverage coverage: '/Total:\|(\d+\.?\d+\%)/' script: - # delete all empty files since they produce errors + # delete all empty files since they produce errors - find coverage -size 0 -type f -delete - ls coverage/ -lah - - lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final.out - - lcov --list coverage/final.out + - lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final.out + - lcov --remove coverage/final.out '*/systemc*/include/*' '*/gcc*/include/*' '/usr/include/*' '*/third_party/*' -o coverage/final_dramsys.out + - lcov --list coverage/final_dramsys.out + # Create html + - mkdir ${CI_PROJECT_DIR}/html + - genhtml --prefix ${CI_PROJECT_DIR} --ignore-errors source coverage/final_dramsys.out --legend --title "`git log | head | grep commit`" --output-directory=html/ + artifacts: paths: - coverage/final.out + - coverage/final_drasys.out + -html/ include: From 3c00374d39a81c15206f97275d4228b28798b885 Mon Sep 17 00:00:00 2001 From: scorrea Date: Fri, 26 Jun 2020 11:29:22 +0200 Subject: [PATCH 20/34] ci build and path updated --- .gitlab-ci.yml => gitlab-ci.yml | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) rename .gitlab-ci.yml => gitlab-ci.yml (89%) diff --git a/.gitlab-ci.yml b/gitlab-ci.yml similarity index 89% rename from .gitlab-ci.yml rename to gitlab-ci.yml index e77b5f89..5ca5a2f2 100644 --- a/.gitlab-ci.yml +++ b/gitlab-ci.yml @@ -20,18 +20,16 @@ build: - rm -rf build - mkdir -p build - cd build - - cmake ../DRAMSys - - make -j16 + - qmake ../DRAMSys/DRAMSys.pro + - make -j4 - find . -name "*.o" -type f -delete - - rm -rf ${CI_PROJECT_DIR}/coverage + # Create Base file to cover all lines - mkdir -p ${CI_PROJECT_DIR}/coverage - cd ${CI_PROJECT_DIR} - export GCOV_PREFIX=$(pwd) - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') - lcov -q -c --initial --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR} -o ${CI_PROJECT_DIR}/coverage/base.out - - cache: key: build paths: @@ -41,12 +39,12 @@ build: artifacts: paths: - coverage/base.out - + coverage: stage: Coverage coverage: '/Total:\|(\d+\.?\d+\%)/' script: - # delete all empty files since they produce errors + # delete all empty files since they produce errors - find coverage -size 0 -type f -delete - ls coverage/ -lah - lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final.out @@ -56,13 +54,11 @@ coverage: - mkdir ${CI_PROJECT_DIR}/html - genhtml --prefix ${CI_PROJECT_DIR} --ignore-errors source coverage/final_dramsys.out --legend --title "`git log | head | grep commit`" --output-directory=html/ - artifacts: paths: - coverage/final.out - - coverage/final_drasys.out - -html/ - + - coverage/final_dramsys.out + - html/ include: - '/DRAMSys/tests/lpddr4/ci.yml' From 79574c83ecf66fb0668b26a470e55fba9d519b05 Mon Sep 17 00:00:00 2001 From: scorrea Date: Fri, 26 Jun 2020 11:31:55 +0200 Subject: [PATCH 21/34] ci build and path updated2 --- gitlab-ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gitlab-ci.yml b/gitlab-ci.yml index 5ca5a2f2..070986b1 100644 --- a/gitlab-ci.yml +++ b/gitlab-ci.yml @@ -65,4 +65,4 @@ include: - '/DRAMSys/tests/ddr3_multirank/ci.yml' - '/DRAMSys/tests/DDR4/ci.yml' - '/DRAMSys/tests/HBM2/ci.yml' - #- '/DRAMSys/tests/dramsys-gem5/ci.yml' # Should be activated again when a new gitlab runner with right dependencies is used + #- '/DRAMSys/tests/dramsys-gem5/ci.yml' # Should be activated again when a new gitlab runner with right dependencies is used From c97c3b87f69fd0d2ba7286ae4b4b1d8a3567e35f Mon Sep 17 00:00:00 2001 From: scorrea Date: Fri, 26 Jun 2020 11:34:35 +0200 Subject: [PATCH 22/34] ci build and path updated3 --- gitlab-ci.yml => .gitlab-ci.yml | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename gitlab-ci.yml => .gitlab-ci.yml (100%) diff --git a/gitlab-ci.yml b/.gitlab-ci.yml similarity index 100% rename from gitlab-ci.yml rename to .gitlab-ci.yml From bc8f2aaecaafb378f65f59e509938e4c98cf424e Mon Sep 17 00:00:00 2001 From: scorrea Date: Fri, 26 Jun 2020 11:44:10 +0200 Subject: [PATCH 23/34] ci build and path updated4 --- .gitlab-ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 070986b1..3acd0825 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -20,7 +20,7 @@ build: - rm -rf build - mkdir -p build - cd build - - qmake ../DRAMSys/DRAMSys.pro + - cmake ../DRAMSys - make -j4 - find . -name "*.o" -type f -delete # Create Base file to cover all lines From 066f22c798271321a945fbc04637b5598cfed0d6 Mon Sep 17 00:00:00 2001 From: scorrea Date: Fri, 26 Jun 2020 15:56:22 +0200 Subject: [PATCH 24/34] cov path modified --- .gitlab-ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 3acd0825..7d147bbc 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -25,7 +25,7 @@ build: - find . -name "*.o" -type f -delete # Create Base file to cover all lines - mkdir -p ${CI_PROJECT_DIR}/coverage - - cd ${CI_PROJECT_DIR} + - cd ${CI_PROJECT_DIR}/coverage - export GCOV_PREFIX=$(pwd) - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') - lcov -q -c --initial --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR} -o ${CI_PROJECT_DIR}/coverage/base.out From 117937f4aaddeacbe47427f6958c3093b4e89512 Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Tue, 30 Jun 2020 11:15:46 +0200 Subject: [PATCH 25/34] Includes flag for coverage build. --- .gitlab-ci.yml | 3 ++- DRAMSys/CMakeLists.txt | 12 +++++++----- DRAMSys/library/CMakeLists.txt | 12 ++++++------ DRAMSys/simulator/CMakeLists.txt | 11 ++++++----- DRAMSys/tests/ddr3_multirank/ci.yml | 2 +- 5 files changed, 22 insertions(+), 18 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 7d147bbc..8cee2556 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -20,8 +20,9 @@ build: - rm -rf build - mkdir -p build - cd build + - export COVERAGE=true - cmake ../DRAMSys - - make -j4 + - make -j 24 - find . -name "*.o" -type f -delete # Create Base file to cover all lines - mkdir -p ${CI_PROJECT_DIR}/coverage diff --git a/DRAMSys/CMakeLists.txt b/DRAMSys/CMakeLists.txt index ec99b946..ccb2df9f 100644 --- a/DRAMSys/CMakeLists.txt +++ b/DRAMSys/CMakeLists.txt @@ -38,11 +38,13 @@ project(DRAMSys) # Configuration: set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version") set(DCMAKE_SH "CMAKE_SH-NOTFOUND" CACHE STRING "Ignore sh.exe error on Windows") -SET(GCC_COVERAGE_COMPILE_FLAGS "-g -O0 -coverage -fprofile-arcs -ftest-coverage") -SET(GCC_COVERAGE_LINK_FLAGS "-coverage -lgcov") -SET( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}" ) -SET( CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${GCC_COVERAGE_LINK_FLAGS}") - +if(DEFINED ENV{COVERAGE}) + set(GCC_COVERAGE_COMPILE_FLAGS "-g -O0 -coverage -fprofile-arcs -ftest-coverage") + set(GCC_COVERAGE_LINK_FLAGS "-coverage -lgcov") + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}") + set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${GCC_COVERAGE_LINK_FLAGS}") + message("-- Coverage check enabled") +endif() # Add DRAMSysLibrary: add_subdirectory(library) diff --git a/DRAMSys/library/CMakeLists.txt b/DRAMSys/library/CMakeLists.txt index a8301da7..a84e0f29 100644 --- a/DRAMSys/library/CMakeLists.txt +++ b/DRAMSys/library/CMakeLists.txt @@ -38,12 +38,12 @@ project(DRAMSysLibrary) # Configuration: set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version") set(DCMAKE_SH="CMAKE_SH-NOTFOUND") -SET(GCC_COVERAGE_COMPILE_FLAGS "-g -O0 -coverage -fprofile-arcs -ftest-coverage") -SET(GCC_COVERAGE_LINK_FLAGS "-coverage -lgcov") -SET( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}" ) -SET( CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${GCC_COVERAGE_LINK_FLAGS}") - - +if(DEFINED ENV{COVERAGE}) + set(GCC_COVERAGE_COMPILE_FLAGS "-g -O0 -coverage -fprofile-arcs -ftest-coverage") + set(GCC_COVERAGE_LINK_FLAGS "-coverage -lgcov") + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}") + set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${GCC_COVERAGE_LINK_FLAGS}") +endif() # Add DRAMPower: add_subdirectory(src/common/third_party/DRAMPower) diff --git a/DRAMSys/simulator/CMakeLists.txt b/DRAMSys/simulator/CMakeLists.txt index fad8af38..3018a14f 100644 --- a/DRAMSys/simulator/CMakeLists.txt +++ b/DRAMSys/simulator/CMakeLists.txt @@ -38,11 +38,12 @@ project(DRAMSysSimulator) # Configuration: set(CMAKE_CXX_STANDARD 11 CACHE STRING "C++ Version") set(DCMAKE_SH="CMAKE_SH-NOTFOUND") -SET(GCC_COVERAGE_COMPILE_FLAGS "-g -O0 -coverage -fprofile-arcs -ftest-coverage") -SET(GCC_COVERAGE_LINK_FLAGS "-coverage -lgcov") -SET( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}" ) -SET( CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${GCC_COVERAGE_LINK_FLAGS}") - +if(DEFINED ENV{COVERAGE}) + set(GCC_COVERAGE_COMPILE_FLAGS "-g -O0 -coverage -fprofile-arcs -ftest-coverage") + set(GCC_COVERAGE_LINK_FLAGS "-coverage -lgcov") + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}") + set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${GCC_COVERAGE_LINK_FLAGS}") +endif() if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/../library/src/simulation/DRAMSysRecordable.cpp) add_definitions(-DRECORDING) diff --git a/DRAMSys/tests/ddr3_multirank/ci.yml b/DRAMSys/tests/ddr3_multirank/ci.yml index ea32584e..254c0e62 100644 --- a/DRAMSys/tests/ddr3_multirank/ci.yml +++ b/DRAMSys/tests/ddr3_multirank/ci.yml @@ -23,7 +23,7 @@ example_ddr3: artifacts: paths: - - build/simulator/ddr3_multirank_ddr3_ch0.tdb + - build/simulator/ddr3-dual-rank_ddr3_ch0.tdb - coverage/${CI_JOB_NAME}.out expire_in: 2 days From 9241689b99552d2610bbf0fc02bb0a5cce28db24 Mon Sep 17 00:00:00 2001 From: scorrea Date: Tue, 30 Jun 2020 12:33:12 +0200 Subject: [PATCH 26/34] cov test updated --- .gitlab-ci.yml | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 7d147bbc..04fdd89e 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -47,18 +47,18 @@ coverage: # delete all empty files since they produce errors - find coverage -size 0 -type f -delete - ls coverage/ -lah - - lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final.out - - lcov --remove coverage/final.out '*/systemc*/include/*' '*/gcc*/include/*' '/usr/include/*' '*/third_party/*' -o coverage/final_dramsys.out + - lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final_dramsys.out + - lcov --remove coverage/final.out '*/systemc*/include/*' '*/traceAnalyzer/*' '*/gcc*/include/*' '/usr/include/*' '*/third_party/*' -o coverage/final_dramsys.out - lcov --list coverage/final_dramsys.out # Create html - - mkdir ${CI_PROJECT_DIR}/html - - genhtml --prefix ${CI_PROJECT_DIR} --ignore-errors source coverage/final_dramsys.out --legend --title "`git log | head | grep commit`" --output-directory=html/ + #- mkdir ${CI_PROJECT_DIR}/html + #- genhtml --prefix ${CI_PROJECT_DIR} --ignore-errors source coverage/final_dramsys.out --legend --title "`git log | head | grep commit`" --output-directory=html/ artifacts: paths: - - coverage/final.out + #- coverage/final.out - coverage/final_dramsys.out - - html/ + #- html/ include: - '/DRAMSys/tests/lpddr4/ci.yml' From 5db27a8b17dbf1bd33fc5cd571485d6805547477 Mon Sep 17 00:00:00 2001 From: scorrea Date: Tue, 30 Jun 2020 12:59:24 +0200 Subject: [PATCH 27/34] undone changes to cov test --- .gitlab-ci.yml | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 83ae3ce9..72a8088a 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -48,18 +48,18 @@ coverage: # delete all empty files since they produce errors - find coverage -size 0 -type f -delete - ls coverage/ -lah - - lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final_dramsys.out + - lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final.out - lcov --remove coverage/final.out '*/systemc*/include/*' '*/traceAnalyzer/*' '*/gcc*/include/*' '/usr/include/*' '*/third_party/*' -o coverage/final_dramsys.out - lcov --list coverage/final_dramsys.out # Create html - #- mkdir ${CI_PROJECT_DIR}/html - #- genhtml --prefix ${CI_PROJECT_DIR} --ignore-errors source coverage/final_dramsys.out --legend --title "`git log | head | grep commit`" --output-directory=html/ + - mkdir ${CI_PROJECT_DIR}/html + - genhtml --prefix ${CI_PROJECT_DIR} --ignore-errors source coverage/final_dramsys.out --legend --title "`git log | head | grep commit`" --output-directory=html/ artifacts: paths: - #- coverage/final.out + - coverage/final.out - coverage/final_dramsys.out - #- html/ + - html/ include: - '/DRAMSys/tests/lpddr4/ci.yml' From 153d68dee8fbbb0ab61a80d88dbe591a33ecf0b5 Mon Sep 17 00:00:00 2001 From: scorrea Date: Tue, 30 Jun 2020 15:58:23 +0200 Subject: [PATCH 28/34] base file removed --- .gitlab-ci.yml | 1 - 1 file changed, 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 72a8088a..a54fbd85 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -29,7 +29,6 @@ build: - cd ${CI_PROJECT_DIR}/coverage - export GCOV_PREFIX=$(pwd) - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') - - lcov -q -c --initial --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR} -o ${CI_PROJECT_DIR}/coverage/base.out cache: key: build From 6e8ea831c62701c2f620e9294a7eaad3969c721b Mon Sep 17 00:00:00 2001 From: scorrea Date: Tue, 30 Jun 2020 16:12:48 +0200 Subject: [PATCH 29/34] removed base.out before coverage eval --- .gitlab-ci.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index a54fbd85..0160fe3b 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -29,6 +29,7 @@ build: - cd ${CI_PROJECT_DIR}/coverage - export GCOV_PREFIX=$(pwd) - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') + - lcov -q -c --initial --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR} -o ${CI_PROJECT_DIR}/coverage/base.out cache: key: build @@ -46,6 +47,7 @@ coverage: script: # delete all empty files since they produce errors - find coverage -size 0 -type f -delete + - rm coverage/base.out - ls coverage/ -lah - lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final.out - lcov --remove coverage/final.out '*/systemc*/include/*' '*/traceAnalyzer/*' '*/gcc*/include/*' '/usr/include/*' '*/third_party/*' -o coverage/final_dramsys.out From f0d3a081c85287dd0097b4169d01232a3132dafa Mon Sep 17 00:00:00 2001 From: scorrea Date: Tue, 30 Jun 2020 17:07:51 +0200 Subject: [PATCH 30/34] .gitlab-ci.yml back to older version --- .gitlab-ci.yml | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 0160fe3b..30aa8890 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -24,12 +24,9 @@ build: - cmake ../DRAMSys - make -j 24 - find . -name "*.o" -type f -delete - # Create Base file to cover all lines + - rm -rf ${CI_PROJECT_DIR}/coverage - mkdir -p ${CI_PROJECT_DIR}/coverage - - cd ${CI_PROJECT_DIR}/coverage - - export GCOV_PREFIX=$(pwd) - - export GCOV_PREFIX_STRIP=$(pwd | awk -F"/" '{print NF-1}') - - lcov -q -c --initial --rc geninfo_adjust_src_path=$GCOV_PREFIX -d ${CI_PROJECT_DIR} -o ${CI_PROJECT_DIR}/coverage/base.out + cache: key: build @@ -39,7 +36,7 @@ build: artifacts: paths: - - coverage/base.out + - coverage/ coverage: stage: Coverage @@ -47,7 +44,6 @@ coverage: script: # delete all empty files since they produce errors - find coverage -size 0 -type f -delete - - rm coverage/base.out - ls coverage/ -lah - lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final.out - lcov --remove coverage/final.out '*/systemc*/include/*' '*/traceAnalyzer/*' '*/gcc*/include/*' '/usr/include/*' '*/third_party/*' -o coverage/final_dramsys.out From e98e1c49aaaf83815c1bb8416f6db30bc891af60 Mon Sep 17 00:00:00 2001 From: scorrea Date: Tue, 30 Jun 2020 17:42:08 +0200 Subject: [PATCH 31/34] html removed --- .gitlab-ci.yml | 7 +- .../AddressDecoder.cpp.func-sort-c.html | 93 ++ .../src/common/AddressDecoder.cpp.func.html | 93 ++ .../src/common/AddressDecoder.cpp.gcov.html | 367 ++++++ .../common/AddressDecoder.h.func-sort-c.html | 81 ++ .../src/common/AddressDecoder.h.func.html | 81 ++ .../src/common/AddressDecoder.h.gcov.html | 144 +++ .../common/TlmRecorder.cpp.func-sort-c.html | 153 +++ .../src/common/TlmRecorder.cpp.func.html | 153 +++ .../src/common/TlmRecorder.cpp.gcov.html | 557 ++++++++ .../src/common/TlmRecorder.h.func-sort-c.html | 81 ++ .../src/common/TlmRecorder.h.func.html | 81 ++ .../src/common/TlmRecorder.h.gcov.html | 184 +++ .../dramExtensions.cpp.func-sort-c.html | 309 +++++ .../src/common/dramExtensions.cpp.func.html | 309 +++++ .../src/common/dramExtensions.cpp.gcov.html | 434 +++++++ .../common/dramExtensions.h.func-sort-c.html | 97 ++ .../src/common/dramExtensions.h.func.html | 97 ++ .../src/common/dramExtensions.h.gcov.html | 321 +++++ .../library/src/common/index-sort-f.html | 183 +++ .../library/src/common/index-sort-l.html | 183 +++ html/DRAMSys/library/src/common/index.html | 183 +++ ...2_base_protocol_checker.h.func-sort-c.html | 181 +++ .../tlm2_base_protocol_checker.h.func.html | 181 +++ .../tlm2_base_protocol_checker.h.gcov.html | 1128 +++++++++++++++++ .../src/common/utils.cpp.func-sort-c.html | 109 ++ .../library/src/common/utils.cpp.func.html | 109 ++ .../library/src/common/utils.cpp.gcov.html | 239 ++++ .../src/common/utils.h.func-sort-c.html | 85 ++ .../library/src/common/utils.h.func.html | 85 ++ .../library/src/common/utils.h.gcov.html | 187 +++ .../Configuration.cpp.func-sort-c.html | 113 ++ .../configuration/Configuration.cpp.func.html | 113 ++ .../configuration/Configuration.cpp.gcov.html | 397 ++++++ .../Configuration.h.func-sort-c.html | 93 ++ .../configuration/Configuration.h.func.html | 93 ++ .../configuration/Configuration.h.gcov.html | 147 +++ .../TemperatureSimConfig.h.func-sort-c.html | 85 ++ .../TemperatureSimConfig.h.func.html | 85 ++ .../TemperatureSimConfig.h.gcov.html | 207 +++ .../src/configuration/index-sort-f.html | 123 ++ .../src/configuration/index-sort-l.html | 123 ++ .../library/src/configuration/index.html | 123 ++ .../memspec/MemSpec.cpp.func-sort-c.html | 97 ++ .../memspec/MemSpec.cpp.func.html | 97 ++ .../memspec/MemSpec.cpp.gcov.html | 161 +++ .../memspec/MemSpec.h.func-sort-c.html | 89 ++ .../configuration/memspec/MemSpec.h.func.html | 89 ++ .../configuration/memspec/MemSpec.h.gcov.html | 157 +++ .../memspec/MemSpecDDR3.cpp.func-sort-c.html | 109 ++ .../memspec/MemSpecDDR3.cpp.func.html | 109 ++ .../memspec/MemSpecDDR3.cpp.gcov.html | 225 ++++ .../memspec/MemSpecDDR3.h.func-sort-c.html | 89 ++ .../memspec/MemSpecDDR3.h.func.html | 89 ++ .../memspec/MemSpecDDR3.h.gcov.html | 127 ++ .../memspec/MemSpecDDR4.cpp.func-sort-c.html | 105 ++ .../memspec/MemSpecDDR4.cpp.func.html | 105 ++ .../memspec/MemSpecDDR4.cpp.gcov.html | 242 ++++ .../memspec/MemSpecDDR4.h.func-sort-c.html | 89 ++ .../memspec/MemSpecDDR4.h.func.html | 89 ++ .../memspec/MemSpecDDR4.h.gcov.html | 127 ++ .../memspec/MemSpecGDDR5.cpp.func-sort-c.html | 109 ++ .../memspec/MemSpecGDDR5.cpp.func.html | 109 ++ .../memspec/MemSpecGDDR5.cpp.gcov.html | 229 ++++ .../memspec/MemSpecGDDR5.h.func-sort-c.html | 89 ++ .../memspec/MemSpecGDDR5.h.func.html | 89 ++ .../memspec/MemSpecGDDR5.h.gcov.html | 127 ++ .../MemSpecGDDR5X.cpp.func-sort-c.html | 109 ++ .../memspec/MemSpecGDDR5X.cpp.func.html | 109 ++ .../memspec/MemSpecGDDR5X.cpp.gcov.html | 229 ++++ .../memspec/MemSpecGDDR5X.h.func-sort-c.html | 89 ++ .../memspec/MemSpecGDDR5X.h.func.html | 89 ++ .../memspec/MemSpecGDDR5X.h.gcov.html | 127 ++ .../memspec/MemSpecGDDR6.cpp.func-sort-c.html | 109 ++ .../memspec/MemSpecGDDR6.cpp.func.html | 109 ++ .../memspec/MemSpecGDDR6.cpp.gcov.html | 231 ++++ .../memspec/MemSpecGDDR6.h.func-sort-c.html | 89 ++ .../memspec/MemSpecGDDR6.h.func.html | 89 ++ .../memspec/MemSpecGDDR6.h.gcov.html | 127 ++ .../memspec/MemSpecHBM2.cpp.func-sort-c.html | 109 ++ .../memspec/MemSpecHBM2.cpp.func.html | 109 ++ .../memspec/MemSpecHBM2.cpp.gcov.html | 226 ++++ .../memspec/MemSpecHBM2.h.func-sort-c.html | 89 ++ .../memspec/MemSpecHBM2.h.func.html | 89 ++ .../memspec/MemSpecHBM2.h.gcov.html | 127 ++ .../MemSpecLPDDR4.cpp.func-sort-c.html | 109 ++ .../memspec/MemSpecLPDDR4.cpp.func.html | 109 ++ .../memspec/MemSpecLPDDR4.cpp.gcov.html | 233 ++++ .../memspec/MemSpecLPDDR4.h.func-sort-c.html | 89 ++ .../memspec/MemSpecLPDDR4.h.func.html | 89 ++ .../memspec/MemSpecLPDDR4.h.gcov.html | 127 ++ .../MemSpecWideIO.cpp.func-sort-c.html | 109 ++ .../memspec/MemSpecWideIO.cpp.func.html | 109 ++ .../memspec/MemSpecWideIO.cpp.gcov.html | 233 ++++ .../memspec/MemSpecWideIO.h.func-sort-c.html | 89 ++ .../memspec/MemSpecWideIO.h.func.html | 89 ++ .../memspec/MemSpecWideIO.h.gcov.html | 127 ++ .../MemSpecWideIO2.cpp.func-sort-c.html | 109 ++ .../memspec/MemSpecWideIO2.cpp.func.html | 109 ++ .../memspec/MemSpecWideIO2.cpp.gcov.html | 218 ++++ .../memspec/MemSpecWideIO2.h.func-sort-c.html | 89 ++ .../memspec/MemSpecWideIO2.h.func.html | 89 ++ .../memspec/MemSpecWideIO2.h.gcov.html | 127 ++ .../configuration/memspec/index-sort-f.html | 293 +++++ .../configuration/memspec/index-sort-l.html | 293 +++++ .../src/configuration/memspec/index.html | 293 +++++ .../BankMachine.cpp.func-sort-c.html | 161 +++ .../src/controller/BankMachine.cpp.func.html | 161 +++ .../src/controller/BankMachine.cpp.gcov.html | 413 ++++++ .../controller/BankMachine.h.func-sort-c.html | 113 ++ .../src/controller/BankMachine.h.func.html | 113 ++ .../src/controller/BankMachine.h.gcov.html | 194 +++ .../controller/Command.cpp.func-sort-c.html | 133 ++ .../src/controller/Command.cpp.func.html | 133 ++ .../src/controller/Command.cpp.gcov.html | 257 ++++ .../src/controller/Command.h.func-sort-c.html | 81 ++ .../src/controller/Command.h.func.html | 81 ++ .../src/controller/Command.h.gcov.html | 155 +++ .../Controller.cpp.func-sort-c.html | 125 ++ .../src/controller/Controller.cpp.func.html | 125 ++ .../src/controller/Controller.cpp.gcov.html | 528 ++++++++ .../ControllerIF.h.func-sort-c.html | 97 ++ .../src/controller/ControllerIF.h.func.html | 97 ++ .../src/controller/ControllerIF.h.gcov.html | 186 +++ .../ControllerRecordable.cpp.func-sort-c.html | 109 ++ .../ControllerRecordable.cpp.func.html | 109 ++ .../ControllerRecordable.cpp.gcov.html | 174 +++ .../ControllerRecordable.h.func-sort-c.html | 93 ++ .../ControllerRecordable.h.func.html | 93 ++ .../ControllerRecordable.h.gcov.html | 130 ++ .../checker/CheckerDDR3.cpp.func-sort-c.html | 97 ++ .../checker/CheckerDDR3.cpp.func.html | 97 ++ .../checker/CheckerDDR3.cpp.gcov.html | 516 ++++++++ .../checker/CheckerDDR3.h.func-sort-c.html | 85 ++ .../checker/CheckerDDR3.h.func.html | 85 ++ .../checker/CheckerDDR3.h.gcov.html | 129 ++ .../checker/CheckerDDR4.cpp.func-sort-c.html | 97 ++ .../checker/CheckerDDR4.cpp.func.html | 97 ++ .../checker/CheckerDDR4.cpp.gcov.html | 547 ++++++++ .../checker/CheckerDDR4.h.func-sort-c.html | 85 ++ .../checker/CheckerDDR4.h.func.html | 85 ++ .../checker/CheckerDDR4.h.gcov.html | 129 ++ .../checker/CheckerGDDR5.cpp.func-sort-c.html | 97 ++ .../checker/CheckerGDDR5.cpp.func.html | 97 ++ .../checker/CheckerGDDR5.cpp.gcov.html | 636 ++++++++++ .../checker/CheckerGDDR5.h.func-sort-c.html | 85 ++ .../checker/CheckerGDDR5.h.func.html | 85 ++ .../checker/CheckerGDDR5.h.gcov.html | 129 ++ .../CheckerGDDR5X.cpp.func-sort-c.html | 97 ++ .../checker/CheckerGDDR5X.cpp.func.html | 97 ++ .../checker/CheckerGDDR5X.cpp.gcov.html | 636 ++++++++++ .../checker/CheckerGDDR5X.h.func-sort-c.html | 85 ++ .../checker/CheckerGDDR5X.h.func.html | 85 ++ .../checker/CheckerGDDR5X.h.gcov.html | 129 ++ .../checker/CheckerGDDR6.cpp.func-sort-c.html | 97 ++ .../checker/CheckerGDDR6.cpp.func.html | 97 ++ .../checker/CheckerGDDR6.cpp.gcov.html | 653 ++++++++++ .../checker/CheckerGDDR6.h.func-sort-c.html | 85 ++ .../checker/CheckerGDDR6.h.func.html | 85 ++ .../checker/CheckerGDDR6.h.gcov.html | 129 ++ .../checker/CheckerHBM2.cpp.func-sort-c.html | 97 ++ .../checker/CheckerHBM2.cpp.func.html | 97 ++ .../checker/CheckerHBM2.cpp.gcov.html | 601 +++++++++ .../checker/CheckerHBM2.h.func-sort-c.html | 85 ++ .../checker/CheckerHBM2.h.func.html | 85 ++ .../checker/CheckerHBM2.h.gcov.html | 129 ++ .../CheckerLPDDR4.cpp.func-sort-c.html | 97 ++ .../checker/CheckerLPDDR4.cpp.func.html | 97 ++ .../checker/CheckerLPDDR4.cpp.gcov.html | 600 +++++++++ .../checker/CheckerLPDDR4.h.func-sort-c.html | 85 ++ .../checker/CheckerLPDDR4.h.func.html | 85 ++ .../checker/CheckerLPDDR4.h.gcov.html | 129 ++ .../CheckerWideIO.cpp.func-sort-c.html | 97 ++ .../checker/CheckerWideIO.cpp.func.html | 97 ++ .../checker/CheckerWideIO.cpp.gcov.html | 488 +++++++ .../checker/CheckerWideIO.h.func-sort-c.html | 85 ++ .../checker/CheckerWideIO.h.func.html | 85 ++ .../checker/CheckerWideIO.h.gcov.html | 129 ++ .../CheckerWideIO2.cpp.func-sort-c.html | 97 ++ .../checker/CheckerWideIO2.cpp.func.html | 97 ++ .../checker/CheckerWideIO2.cpp.gcov.html | 566 +++++++++ .../checker/CheckerWideIO2.h.func-sort-c.html | 85 ++ .../checker/CheckerWideIO2.h.func.html | 85 ++ .../checker/CheckerWideIO2.h.gcov.html | 129 ++ .../src/controller/checker/index-sort-f.html | 273 ++++ .../src/controller/checker/index-sort-l.html | 273 ++++ .../library/src/controller/checker/index.html | 273 ++++ .../cmdmux/CmdMuxOldest.cpp.func-sort-c.html | 89 ++ .../cmdmux/CmdMuxOldest.cpp.func.html | 89 ++ .../cmdmux/CmdMuxOldest.cpp.gcov.html | 145 +++ .../cmdmux/CmdMuxOldest.h.func-sort-c.html | 89 ++ .../cmdmux/CmdMuxOldest.h.func.html | 89 ++ .../cmdmux/CmdMuxOldest.h.gcov.html | 125 ++ .../cmdmux/CmdMuxStrict.cpp.func-sort-c.html | 89 ++ .../cmdmux/CmdMuxStrict.cpp.func.html | 89 ++ .../cmdmux/CmdMuxStrict.cpp.gcov.html | 146 +++ .../cmdmux/CmdMuxStrict.h.func-sort-c.html | 89 ++ .../cmdmux/CmdMuxStrict.h.func.html | 89 ++ .../cmdmux/CmdMuxStrict.h.gcov.html | 125 ++ .../src/controller/cmdmux/index-sort-f.html | 133 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mode 100644 html/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp.func-sort-c.html create mode 100644 html/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp.func.html create mode 100644 html/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp.gcov.html create mode 100644 html/DRAMSys/library/src/simulation/dram/DramGDDR5.h.func-sort-c.html create mode 100644 html/DRAMSys/library/src/simulation/dram/DramGDDR5.h.func.html create mode 100644 html/DRAMSys/library/src/simulation/dram/DramGDDR5.h.gcov.html create mode 100644 html/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp.func-sort-c.html create mode 100644 html/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp.func.html create mode 100644 html/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp.gcov.html create mode 100644 html/DRAMSys/library/src/simulation/dram/DramGDDR5X.h.func-sort-c.html create mode 100644 html/DRAMSys/library/src/simulation/dram/DramGDDR5X.h.func.html create mode 100644 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create mode 100644 html/DRAMSys/library/src/simulation/dram/DramHBM2.h.gcov.html create mode 100644 html/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp.func-sort-c.html create mode 100644 html/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp.func.html create mode 100644 html/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp.gcov.html create mode 100644 html/DRAMSys/library/src/simulation/dram/DramLPDDR4.h.func-sort-c.html create mode 100644 html/DRAMSys/library/src/simulation/dram/DramLPDDR4.h.func.html create mode 100644 html/DRAMSys/library/src/simulation/dram/DramLPDDR4.h.gcov.html create mode 100644 html/DRAMSys/library/src/simulation/dram/DramRecordable.cpp.func-sort-c.html create mode 100644 html/DRAMSys/library/src/simulation/dram/DramRecordable.cpp.func.html create mode 100644 html/DRAMSys/library/src/simulation/dram/DramRecordable.cpp.gcov.html create mode 100644 html/DRAMSys/library/src/simulation/dram/DramRecordable.h.func-sort-c.html create mode 100644 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html/DRAMSys/library/src/simulation/dram/index-sort-f.html create mode 100644 html/DRAMSys/library/src/simulation/dram/index-sort-l.html create mode 100644 html/DRAMSys/library/src/simulation/dram/index.html create mode 100644 html/DRAMSys/library/src/simulation/index-sort-f.html create mode 100644 html/DRAMSys/library/src/simulation/index-sort-l.html create mode 100644 html/DRAMSys/library/src/simulation/index.html create mode 100644 html/DRAMSys/simulator/MemoryManager.cpp.func-sort-c.html create mode 100644 html/DRAMSys/simulator/MemoryManager.cpp.func.html create mode 100644 html/DRAMSys/simulator/MemoryManager.cpp.gcov.html create mode 100644 html/DRAMSys/simulator/StlPlayer.h.func-sort-c.html create mode 100644 html/DRAMSys/simulator/StlPlayer.h.func.html create mode 100644 html/DRAMSys/simulator/StlPlayer.h.gcov.html create mode 100644 html/DRAMSys/simulator/TracePlayer.cpp.func-sort-c.html create mode 100644 html/DRAMSys/simulator/TracePlayer.cpp.func.html create mode 100644 html/DRAMSys/simulator/TracePlayer.cpp.gcov.html create mode 100644 html/DRAMSys/simulator/TracePlayer.h.func-sort-c.html create mode 100644 html/DRAMSys/simulator/TracePlayer.h.func.html create mode 100644 html/DRAMSys/simulator/TracePlayer.h.gcov.html create mode 100644 html/DRAMSys/simulator/TracePlayerListener.h.func-sort-c.html create mode 100644 html/DRAMSys/simulator/TracePlayerListener.h.func.html create mode 100644 html/DRAMSys/simulator/TracePlayerListener.h.gcov.html create mode 100644 html/DRAMSys/simulator/TraceSetup.cpp.func-sort-c.html create mode 100644 html/DRAMSys/simulator/TraceSetup.cpp.func.html create mode 100644 html/DRAMSys/simulator/TraceSetup.cpp.gcov.html create mode 100644 html/DRAMSys/simulator/TraceSetup.h.func-sort-c.html create mode 100644 html/DRAMSys/simulator/TraceSetup.h.func.html create mode 100644 html/DRAMSys/simulator/TraceSetup.h.gcov.html create mode 100644 html/DRAMSys/simulator/index-sort-f.html create mode 100644 html/DRAMSys/simulator/index-sort-l.html create mode 100644 html/DRAMSys/simulator/index.html create mode 100644 html/DRAMSys/simulator/main.cpp.func-sort-c.html create mode 100644 html/DRAMSys/simulator/main.cpp.func.html create mode 100644 html/DRAMSys/simulator/main.cpp.gcov.html create mode 100644 html/gcov.css create mode 100644 html/index-sort-f.html create mode 100644 html/index-sort-l.html create mode 100644 html/index.html diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 30aa8890..bb478fa4 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -20,9 +20,8 @@ build: - rm -rf build - mkdir -p build - cd build - - export COVERAGE=true - cmake ../DRAMSys - - make -j 24 + - make -j 16 - find . -name "*.o" -type f -delete - rm -rf ${CI_PROJECT_DIR}/coverage - mkdir -p ${CI_PROJECT_DIR}/coverage @@ -48,15 +47,11 @@ coverage: - lcov `find coverage -type f -exec echo "-a {}" \;` -o coverage/final.out - lcov --remove coverage/final.out '*/systemc*/include/*' '*/traceAnalyzer/*' '*/gcc*/include/*' '/usr/include/*' '*/third_party/*' -o coverage/final_dramsys.out - lcov --list coverage/final_dramsys.out - # Create html - - mkdir ${CI_PROJECT_DIR}/html - - genhtml --prefix ${CI_PROJECT_DIR} --ignore-errors source coverage/final_dramsys.out --legend --title "`git log | head | grep commit`" --output-directory=html/ artifacts: paths: - coverage/final.out - coverage/final_dramsys.out - - html/ include: - '/DRAMSys/tests/lpddr4/ci.yml' diff --git a/html/DRAMSys/library/src/common/AddressDecoder.cpp.func-sort-c.html b/html/DRAMSys/library/src/common/AddressDecoder.cpp.func-sort-c.html new file mode 100644 index 00000000..a49c5700 --- /dev/null +++ b/html/DRAMSys/library/src/common/AddressDecoder.cpp.func-sort-c.html @@ -0,0 +1,93 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/common/AddressDecoder.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/common - AddressDecoder.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11313782.5 %
Date:2020-06-30 17:34:44Functions:77100.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN14AddressDecoder23getUnsignedAttrFromJsonEN8nlohmann10basic_jsonISt3mapSt6vectorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEblmdSaNS0_14adl_serializerEEES9_30
_Z41__static_initialization_and_destruction_0ii30
_ZN14AddressDecoder5printEv30
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/common/AddressDecoder.cpp.func.html b/html/DRAMSys/library/src/common/AddressDecoder.cpp.func.html new file mode 100644 index 00000000..08e0325a --- /dev/null +++ b/html/DRAMSys/library/src/common/AddressDecoder.cpp.func.html @@ -0,0 +1,93 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/common/AddressDecoder.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/common - AddressDecoder.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11313782.5 %
Date:2020-06-30 17:34:44Functions:77100.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN14AddressDecoder23getUnsignedAttrFromJsonEN8nlohmann10basic_jsonISt3mapSt6vectorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEblmdSaNS0_14adl_serializerEEES9_30
_Z41__static_initialization_and_destruction_0ii30
_ZN14AddressDecoder5printEv30
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/common/AddressDecoder.cpp.gcov.html b/html/DRAMSys/library/src/common/AddressDecoder.cpp.gcov.html new file mode 100644 index 00000000..9316d48d --- /dev/null +++ b/html/DRAMSys/library/src/common/AddressDecoder.cpp.gcov.html @@ -0,0 +1,367 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/common/AddressDecoder.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/common - AddressDecoder.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11313782.5 %
Date:2020-06-30 17:34:44Functions:77100.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/common - AddressDecoder.h (source / functions)HitTotalCoverage
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Generated by: LCOV version 1.13
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Function Name Sort by function nameHit count Sort by hit count
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:00-
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/common - TlmRecorder.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:232688.5 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/common - TlmRecorder.cpp (source / functions)HitTotalCoverage
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/common - TlmRecorder.h (source / functions)HitTotalCoverage
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Date:2020-06-30 17:34:44Functions:33100.0 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/common - TlmRecorder.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:33100.0 %
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Current view:top level - DRAMSys/library/src/common - TlmRecorder.h (source / functions)HitTotalCoverage
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Date:2020-06-30 17:34:44Functions:33100.0 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/common - dramExtensions.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:4713235.6 %
Date:2020-06-30 17:34:44Functions:215736.8 %
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_Z41__static_initialization_and_destruction_0ii30
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/common/dramExtensions.cpp.gcov.html b/html/DRAMSys/library/src/common/dramExtensions.cpp.gcov.html new file mode 100644 index 00000000..24492eef --- /dev/null +++ b/html/DRAMSys/library/src/common/dramExtensions.cpp.gcov.html @@ -0,0 +1,434 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/common/dramExtensions.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/common - dramExtensions.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:4713235.6 %
Date:2020-06-30 17:34:44Functions:215736.8 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
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+
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+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/common/dramExtensions.h.func-sort-c.html b/html/DRAMSys/library/src/common/dramExtensions.h.func-sort-c.html new file mode 100644 index 00000000..7fd8bf7d --- /dev/null +++ b/html/DRAMSys/library/src/common/dramExtensions.h.func-sort-c.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/common/dramExtensions.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/common - dramExtensions.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:1818100.0 %
Date:2020-06-30 17:34:44Functions:2450.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN13DramExtensionD2Ev0
_ZN19GenerationExtensionD2Ev0
_ZN19GenerationExtensionD0Ev252908
_ZN13DramExtensionD0Ev253044
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/common/dramExtensions.h.func.html b/html/DRAMSys/library/src/common/dramExtensions.h.func.html new file mode 100644 index 00000000..9b4a65b6 --- /dev/null +++ b/html/DRAMSys/library/src/common/dramExtensions.h.func.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/common/dramExtensions.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/common - dramExtensions.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:1818100.0 %
Date:2020-06-30 17:34:44Functions:2450.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN13DramExtensionD0Ev253044
_ZN13DramExtensionD2Ev0
_ZN19GenerationExtensionD0Ev252908
_ZN19GenerationExtensionD2Ev0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/common/dramExtensions.h.gcov.html b/html/DRAMSys/library/src/common/dramExtensions.h.gcov.html new file mode 100644 index 00000000..9e02640b --- /dev/null +++ b/html/DRAMSys/library/src/common/dramExtensions.h.gcov.html @@ -0,0 +1,321 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/common/dramExtensions.h + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/common - dramExtensions.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:1818100.0 %
Date:2020-06-30 17:34:44Functions:2450.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
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0.2%0.2%
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100.0%
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100.0%
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82.5%82.5%
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Generated by: LCOV version 1.13
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
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91.0%91.0%
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100.0%
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100.0%
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82.5%82.5%
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+      98             : /* EOF */
+      99             : /* EOF */
+     100             : /* EOF */
+     101             : /* EOF */
+     102             : /* EOF */
+     103             : /* EOF */
+     104             : /* EOF */
+     105             : /* EOF */
+     106             : /* EOF */
+     107             : /* EOF */
+     108             : /* EOF */
+     109             : /* EOF */
+     110             : /* EOF */
+     111             : /* EOF */
+     112             : /* EOF */
+     113             : /* EOF */
+     114             : /* EOF */
+     115             : /* EOF */
+     116             : /* EOF */
+     117             : /* EOF */
+     118             : /* EOF */
+     119             : /* EOF */
+     120             : /* EOF */
+     121             : /* EOF */
+     122             : /* EOF */
+     123             : /* EOF */
+     124             : /* EOF */
+     125             : /* EOF */
+     126             : /* EOF */
+     127             : /* EOF */
+     128             : /* EOF */
+     129             : /* EOF */
+     130             : /* EOF */
+     131             : /* EOF */
+     132             : /* EOF */
+     133             : /* EOF */
+     134             : /* EOF */
+     135             : /* EOF */
+     136             : /* EOF */
+     137             : /* EOF */
+     138             : /* EOF */
+     139             : /* EOF */
+     140             : /* EOF */
+     141             : /* EOF */
+     142             : /* EOF */
+     143             : /* EOF */
+     144             : /* EOF */
+     145             : /* EOF */
+     146             : /* EOF */
+     147           0 : /* EOF */
+     148           0 : /* EOF */
+     149           0 : /* EOF */
+     150           0 : /* EOF */
+     151           0 : /* EOF */
+     152           0 : /* EOF */
+     153           0 : /* EOF */
+     154             : /* EOF */
+     155             : /* EOF */
+     156             : /* EOF */
+     157             : /* EOF */
+     158             : /* EOF */
+     159             : /* EOF */
+     160             : /* EOF */
+     161             : /* EOF */
+     162          90 : /* EOF */
+     163             : /* EOF */
+     164             : /* EOF */
+     165             : /* EOF */
+     166             : /* EOF */
+     167             : /* EOF */
+     168             : /* EOF */
+     169           0 : /* EOF */
+     170             : /* EOF */
+     171             : /* EOF */
+     172             : /* EOF */
+     173             : /* EOF */
+     174             : /* EOF */
+     175             : /* EOF */
+     176             : /* EOF */
+     177             : /* EOF */
+     178             : /* EOF */
+     179             : /* EOF */
+     180             : /* EOF */
+     181             : /* EOF */
+     182             : /* EOF */
+     183             : /* EOF */
+     184           0 : /* EOF */
+     185           0 : /* EOF */
+     186             : /* EOF */
+     187           0 : /* EOF */
+     188           0 : /* EOF */
+     189           0 : /* EOF */
+     190             : /* EOF */
+     191             : /* EOF */
+     192             : /* EOF */
+     193             : /* EOF */
+     194             : /* EOF */
+     195             : /* EOF */
+     196             : /* EOF */
+     197             : /* EOF */
+     198             : /* EOF */
+     199             : /* EOF */
+     200             : /* EOF */
+     201             : /* EOF */
+     202             : /* EOF */
+     203             : /* EOF */
+     204             : /* EOF */
+     205             : /* EOF */
+     206             : /* EOF */
+     207             : /* EOF */
+     208             : /* EOF */
+     209             : /* EOF */
+     210           0 : /* EOF */
+     211             : /* EOF */
+     212             : /* EOF */
+     213           0 : /* EOF */
+     214             : /* EOF */
+     215           0 : /* EOF */
+     216           0 : /* EOF */
+     217             : /* EOF */
+     218             : /* EOF */
+     219           0 : /* EOF */
+     220             : /* EOF */
+     221           0 : /* EOF */
+     222           0 : /* EOF */
+     223             : /* EOF */
+     224           0 : /* EOF */
+     225             : /* EOF */
+     226             : /* EOF */
+     227           0 : /* EOF */
+     228             : /* EOF */
+     229             : /* EOF */
+     230           0 : /* EOF */
+     231           0 : /* EOF */
+     232             : /* EOF */
+     233             : /* EOF */
+     234           0 : /* EOF */
+     235             : /* EOF */
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+     237           0 : /* EOF */
+     238             : /* EOF */
+     239           0 : /* EOF */
+     240             : /* EOF */
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+     242           0 : /* EOF */
+     243             : /* EOF */
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+     245           0 : /* EOF */
+     246           0 : /* EOF */
+     247             : /* EOF */
+     248           0 : /* EOF */
+     249             : /* EOF */
+     250           0 : /* EOF */
+     251           0 : /* EOF */
+     252           0 : /* EOF */
+     253             : /* EOF */
+     254           0 : /* EOF */
+     255             : /* EOF */
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+     257           0 : /* EOF */
+     258             : /* EOF */
+     259             : /* EOF */
+     260           0 : /* EOF */
+     261             : /* EOF */
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+     263           0 : /* EOF */
+     264             : /* EOF */
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+     266           0 : /* EOF */
+     267             : /* EOF */
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+     271             : /* EOF */
+     272           0 : /* EOF */
+     273             : /* EOF */
+     274           0 : /* EOF */
+     275             : /* EOF */
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+     278             : /* EOF */
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+     280           0 : /* EOF */
+     281             : /* EOF */
+     282             : /* EOF */
+     283             : /* EOF */
+     284             : /* EOF */
+     285             : /* EOF */
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+     287             : /* EOF */
+     288             : /* EOF */
+     289             : /* EOF */
+     290             : /* EOF */
+     291             : /* EOF */
+     292             : /* EOF */
+     293             : /* EOF */
+     294             : /* EOF */
+     295             : /* EOF */
+     296             : /* EOF */
+     297             : /* EOF */
+     298             : /* EOF */
+     299             : /* EOF */
+     300             : /* EOF */
+     301             : /* EOF */
+     302             : /* EOF */
+     303             : /* EOF */
+     304             : /* EOF */
+     305             : /* EOF */
+     306             : /* EOF */
+     307             : /* EOF */
+     308             : /* EOF */
+     309             : /* EOF */
+     310             : /* EOF */
+     311             : /* EOF */
+     312             : /* EOF */
+     313             : /* EOF */
+     314             : /* EOF */
+     315             : /* EOF */
+     316             : /* EOF */
+     317             : /* EOF */
+     318             : /* EOF */
+     319             : /* EOF */
+     320             : /* EOF */
+     321             : /* EOF */
+     322             : /* EOF */
+     323             : /* EOF */
+     324             : /* EOF */
+     325             : /* EOF */
+     326             : /* EOF */
+     327             : /* EOF */
+     328             : /* EOF */
+     329             : /* EOF */
+     330             : /* EOF */
+     331             : /* EOF */
+     332             : /* EOF */
+     333             : /* EOF */
+     334             : /* EOF */
+     335             : /* EOF */
+     336             : /* EOF */
+     337           0 : /* EOF */
+     338           0 : /* EOF */
+     339           0 : /* EOF */
+     340           0 : /* EOF */
+     341           0 : /* EOF */
+     342             : /* EOF */
+     343             : /* EOF */
+     344             : /* EOF */
+     345             : /* EOF */
+     346             : /* EOF */
+     347             : /* EOF */
+     348             : /* EOF */
+     349             : /* EOF */
+     350             : /* EOF */
+     351             : /* EOF */
+     352             : /* EOF */
+     353             : /* EOF */
+     354             : /* EOF */
+     355             : /* EOF */
+     356             : /* EOF */
+     357             : /* EOF */
+     358             : /* EOF */
+     359             : /* EOF */
+     360             : /* EOF */
+     361             : /* EOF */
+     362             : /* EOF */
+     363             : /* EOF */
+     364             : /* EOF */
+     365             : /* EOF */
+     366             : /* EOF */
+     367             : /* EOF */
+     368             : /* EOF */
+     369             : /* EOF */
+     370             : /* EOF */
+     371             : /* EOF */
+     372             : /* EOF */
+     373             : /* EOF */
+     374             : /* EOF */
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+     376             : /* EOF */
+     377             : /* EOF */
+     378             : /* EOF */
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+     380             : /* EOF */
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+     382           0 : /* EOF */
+     383           0 : /* EOF */
+     384             : /* EOF */
+     385           0 : /* EOF */
+     386             : /* EOF */
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+     388           0 : /* EOF */
+     389             : /* EOF */
+     390           0 : /* EOF */
+     391           0 : /* EOF */
+     392             : /* EOF */
+     393             : /* EOF */
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+     396           0 : /* EOF */
+     397           0 : /* EOF */
+     398             : /* EOF */
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+     400             : /* EOF */
+     401             : /* EOF */
+     402           0 : /* EOF */
+     403             : /* EOF */
+     404             : /* EOF */
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+     409           0 : /* EOF */
+     410             : /* EOF */
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+     412           0 : /* EOF */
+     413             : /* EOF */
+     414             : /* EOF */
+     415             : /* EOF */
+     416           0 : /* EOF */
+     417           0 : /* EOF */
+     418           0 : /* EOF */
+     419             : /* EOF */
+     420           0 : /* EOF */
+     421           0 : /* EOF */
+     422           0 : /* EOF */
+     423             : /* EOF */
+     424             : /* EOF */
+     425           0 : /* EOF */
+     426           0 : /* EOF */
+     427           0 : /* EOF */
+     428             : /* EOF */
+     429           0 : /* EOF */
+     430           0 : /* EOF */
+     431           0 : /* EOF */
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+     433           0 : /* EOF */
+     434             : /* EOF */
+     435             : /* EOF */
+     436           0 : /* EOF */
+     437           0 : /* EOF */
+     438           0 : /* EOF */
+     439             : /* EOF */
+     440           0 : /* EOF */
+     441             : /* EOF */
+     442           0 : /* EOF */
+     443           0 : /* EOF */
+     444           0 : /* EOF */
+     445             : /* EOF */
+     446             : /* EOF */
+     447             : /* EOF */
+     448           0 : /* EOF */
+     449             : /* EOF */
+     450             : /* EOF */
+     451           0 : /* EOF */
+     452             : /* EOF */
+     453           0 : /* EOF */
+     454           0 : /* EOF */
+     455             : /* EOF */
+     456           0 : /* EOF */
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+     458           0 : /* EOF */
+     459             : /* EOF */
+     460           0 : /* EOF */
+     461             : /* EOF */
+     462           0 : /* EOF */
+     463           0 : /* EOF */
+     464             : /* EOF */
+     465             : /* EOF */
+     466           0 : /* EOF */
+     467           0 : /* EOF */
+     468             : /* EOF */
+     469           0 : /* EOF */
+     470           0 : /* EOF */
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+     476           0 : /* EOF */
+     477             : /* EOF */
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+     479           0 : /* EOF */
+     480             : /* EOF */
+     481             : /* EOF */
+     482             : /* EOF */
+     483             : /* EOF */
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+     486           0 : /* EOF */
+     487             : /* EOF */
+     488             : /* EOF */
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+     490           0 : /* EOF */
+     491           0 : /* EOF */
+     492           0 : /* EOF */
+     493           0 : /* EOF */
+     494             : /* EOF */
+     495             : /* EOF */
+     496             : /* EOF */
+     497             : /* EOF */
+     498             : /* EOF */
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+     500           0 : /* EOF */
+     501           0 : /* EOF */
+     502             : /* EOF */
+     503           0 : /* EOF */
+     504             : /* EOF */
+     505             : /* EOF */
+     506           0 : /* EOF */
+     507             : /* EOF */
+     508             : /* EOF */
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+     510           0 : /* EOF */
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+     513             : /* EOF */
+     514           0 : /* EOF */
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+     516           0 : /* EOF */
+     517             : /* EOF */
+     518           0 : /* EOF */
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+     520           0 : /* EOF */
+     521             : /* EOF */
+     522             : /* EOF */
+     523           0 : /* EOF */
+     524             : /* EOF */
+     525             : /* EOF */
+     526             : /* EOF */
+     527             : /* EOF */
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+     529           0 : /* EOF */
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+     531           0 : /* EOF */
+     532             : /* EOF */
+     533           0 : /* EOF */
+     534           0 : /* EOF */
+     535             : /* EOF */
+     536           0 : /* EOF */
+     537             : /* EOF */
+     538             : /* EOF */
+     539           0 : /* EOF */
+     540             : /* EOF */
+     541           0 : /* EOF */
+     542           0 : /* EOF */
+     543             : /* EOF */
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+     545           0 : /* EOF */
+     546           0 : /* EOF */
+     547             : /* EOF */
+     548           0 : /* EOF */
+     549             : /* EOF */
+     550             : /* EOF */
+     551           0 : /* EOF */
+     552           0 : /* EOF */
+     553             : /* EOF */
+     554             : /* EOF */
+     555           0 : /* EOF */
+     556           0 : /* EOF */
+     557             : /* EOF */
+     558           0 : /* EOF */
+     559           0 : /* EOF */
+     560           0 : /* EOF */
+     561           0 : /* EOF */
+     562           0 : /* EOF */
+     563             : /* EOF */
+     564           0 : /* EOF */
+     565           0 : /* EOF */
+     566           0 : /* EOF */
+     567           0 : /* EOF */
+     568             : /* EOF */
+     569             : /* EOF */
+     570             : /* EOF */
+     571             : /* EOF */
+     572             : /* EOF */
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+     574           0 : /* EOF */
+     575           0 : /* EOF */
+     576             : /* EOF */
+     577           0 : /* EOF */
+     578             : /* EOF */
+     579             : /* EOF */
+     580           0 : /* EOF */
+     581             : /* EOF */
+     582             : /* EOF */
+     583             : /* EOF */
+     584             : /* EOF */
+     585           0 : /* EOF */
+     586           0 : /* EOF */
+     587           0 : /* EOF */
+     588           0 : /* EOF */
+     589           0 : /* EOF */
+     590           0 : /* EOF */
+     591             : /* EOF */
+     592             : /* EOF */
+     593             : /* EOF */
+     594           0 : /* EOF */
+     595           0 : /* EOF */
+     596             : /* EOF */
+     597             : /* EOF */
+     598           0 : /* EOF */
+     599           0 : /* EOF */
+     600           0 : /* EOF */
+     601           0 : /* EOF */
+     602             : /* EOF */
+     603           0 : /* EOF */
+     604           0 : /* EOF */
+     605           0 : /* EOF */
+     606           0 : /* EOF */
+     607           0 : /* EOF */
+     608             : /* EOF */
+     609             : /* EOF */
+     610           0 : /* EOF */
+     611           0 : /* EOF */
+     612             : /* EOF */
+     613           0 : /* EOF */
+     614           0 : /* EOF */
+     615           0 : /* EOF */
+     616           0 : /* EOF */
+     617           0 : /* EOF */
+     618             : /* EOF */
+     619             : /* EOF */
+     620           0 : /* EOF */
+     621           0 : /* EOF */
+     622             : /* EOF */
+     623           0 : /* EOF */
+     624           0 : /* EOF */
+     625           0 : /* EOF */
+     626           0 : /* EOF */
+     627             : /* EOF */
+     628           0 : /* EOF */
+     629             : /* EOF */
+     630           0 : /* EOF */
+     631           0 : /* EOF */
+     632             : /* EOF */
+     633             : /* EOF */
+     634           0 : /* EOF */
+     635           0 : /* EOF */
+     636             : /* EOF */
+     637           0 : /* EOF */
+     638           0 : /* EOF */
+     639           0 : /* EOF */
+     640           0 : /* EOF */
+     641           0 : /* EOF */
+     642             : /* EOF */
+     643           0 : /* EOF */
+     644           0 : /* EOF */
+     645             : /* EOF */
+     646             : /* EOF */
+     647           0 : /* EOF */
+     648             : /* EOF */
+     649             : /* EOF */
+     650             : /* EOF */
+     651           0 : /* EOF */
+     652           0 : /* EOF */
+     653           0 : /* EOF */
+     654           0 : /* EOF */
+     655             : /* EOF */
+     656             : /* EOF */
+     657             : /* EOF */
+     658           0 : /* EOF */
+     659           0 : /* EOF */
+     660           0 : /* EOF */
+     661           0 : /* EOF */
+     662           0 : /* EOF */
+     663             : /* EOF */
+     664           0 : /* EOF */
+     665           0 : /* EOF */
+     666           0 : /* EOF */
+     667             : /* EOF */
+     668           0 : /* EOF */
+     669             : /* EOF */
+     670           0 : /* EOF */
+     671           0 : /* EOF */
+     672           0 : /* EOF */
+     673             : /* EOF */
+     674           0 : /* EOF */
+     675             : /* EOF */
+     676           0 : /* EOF */
+     677           0 : /* EOF */
+     678           0 : /* EOF */
+     679           0 : /* EOF */
+     680             : /* EOF */
+     681           0 : /* EOF */
+     682           0 : /* EOF */
+     683           0 : /* EOF */
+     684           0 : /* EOF */
+     685             : /* EOF */
+     686           0 : /* EOF */
+     687           0 : /* EOF */
+     688           0 : /* EOF */
+     689           0 : /* EOF */
+     690             : /* EOF */
+     691           0 : /* EOF */
+     692           0 : /* EOF */
+     693           0 : /* EOF */
+     694           0 : /* EOF */
+     695             : /* EOF */
+     696           0 : /* EOF */
+     697           0 : /* EOF */
+     698           0 : /* EOF */
+     699           0 : /* EOF */
+     700             : /* EOF */
+     701             : /* EOF */
+     702             : /* EOF */
+     703           0 : /* EOF */
+     704           0 : /* EOF */
+     705           0 : /* EOF */
+     706             : /* EOF */
+     707           0 : /* EOF */
+     708           0 : /* EOF */
+     709             : /* EOF */
+     710           0 : /* EOF */
+     711           0 : /* EOF */
+     712             : /* EOF */
+     713           0 : /* EOF */
+     714           0 : /* EOF */
+     715           0 : /* EOF */
+     716           0 : /* EOF */
+     717             : /* EOF */
+     718           0 : /* EOF */
+     719           0 : /* EOF */
+     720             : /* EOF */
+     721           0 : /* EOF */
+     722           0 : /* EOF */
+     723           0 : /* EOF */
+     724           0 : /* EOF */
+     725             : /* EOF */
+     726             : /* EOF */
+     727           0 : /* EOF */
+     728           0 : /* EOF */
+     729           0 : /* EOF */
+     730             : /* EOF */
+     731           0 : /* EOF */
+     732           0 : /* EOF */
+     733           0 : /* EOF */
+     734           0 : /* EOF */
+     735             : /* EOF */
+     736           0 : /* EOF */
+     737           0 : /* EOF */
+     738           0 : /* EOF */
+     739             : /* EOF */
+     740             : /* EOF */
+     741           0 : /* EOF */
+     742             : /* EOF */
+     743             : /* EOF */
+     744             : /* EOF */
+     745             : /* EOF */
+     746           0 : /* EOF */
+     747           0 : /* EOF */
+     748           0 : /* EOF */
+     749           0 : /* EOF */
+     750           0 : /* EOF */
+     751           0 : /* EOF */
+     752             : /* EOF */
+     753             : /* EOF */
+     754           0 : /* EOF */
+     755             : /* EOF */
+     756             : /* EOF */
+     757             : /* EOF */
+     758           0 : /* EOF */
+     759             : /* EOF */
+     760           0 : /* EOF */
+     761           0 : /* EOF */
+     762             : /* EOF */
+     763           0 : /* EOF */
+     764             : /* EOF */
+     765           0 : /* EOF */
+     766           0 : /* EOF */
+     767           0 : /* EOF */
+     768           0 : /* EOF */
+     769             : /* EOF */
+     770           0 : /* EOF */
+     771           0 : /* EOF */
+     772           0 : /* EOF */
+     773           0 : /* EOF */
+     774             : /* EOF */
+     775           0 : /* EOF */
+     776           0 : /* EOF */
+     777           0 : /* EOF */
+     778           0 : /* EOF */
+     779           0 : /* EOF */
+     780             : /* EOF */
+     781           0 : /* EOF */
+     782           0 : /* EOF */
+     783           0 : /* EOF */
+     784           0 : /* EOF */
+     785             : /* EOF */
+     786           0 : /* EOF */
+     787           0 : /* EOF */
+     788           0 : /* EOF */
+     789           0 : /* EOF */
+     790             : /* EOF */
+     791           0 : /* EOF */
+     792           0 : /* EOF */
+     793           0 : /* EOF */
+     794           0 : /* EOF */
+     795             : /* EOF */
+     796           0 : /* EOF */
+     797             : /* EOF */
+     798           0 : /* EOF */
+     799           0 : /* EOF */
+     800           0 : /* EOF */
+     801           0 : /* EOF */
+     802             : /* EOF */
+     803           0 : /* EOF */
+     804           0 : /* EOF */
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Date:2020-06-30 17:34:44Functions:121392.3 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/configuration - Configuration.cpp (source / functions)HitTotalCoverage
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Date:2020-06-30 17:34:44Functions:121392.3 %
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Generated by: LCOV version 1.13
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:121392.3 %
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LCOV - code coverage report
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:33100.0 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/configuration - Configuration.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:55100.0 %
Date:2020-06-30 17:34:44Functions:33100.0 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:55100.0 %
Date:2020-06-30 17:34:44Functions:33100.0 %
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Date:2020-06-30 17:34:44Functions:6785.7 %
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:6785.7 %
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_ZNK11MemSpecDDR323getIntervalOnDataStrobeE7Command2660
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/configuration/memspec - MemSpecDDR3.cpp (source / functions)HitTotalCoverage
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Date:2020-06-30 17:34:44Functions:6785.7 %
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:020.0 %
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/configuration/memspec - MemSpecDDR3.h (source / functions)HitTotalCoverage
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
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_ZN11MemSpecDDR3D0Ev0
_ZN11MemSpecDDR3D2Ev0
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/configuration/memspec - MemSpecDDR3.h (source / functions)HitTotalCoverage
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp.func-sort-c.html b/html/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp.func-sort-c.html new file mode 100644 index 00000000..de51e881 --- /dev/null +++ b/html/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp.func-sort-c.html @@ -0,0 +1,105 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp - functions + + + + + + + + + + + + + + +
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Current view:top level - DRAMSys/library/src/configuration/memspec - MemSpecDDR4.cpp (source / functions)HitTotalCoverage
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Date:2020-06-30 17:34:44Functions:6785.7 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_ZNK11MemSpecDDR420getRefreshIntervalPBEv0
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/configuration/memspec - MemSpecDDR4.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:6785.7 %
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Function Name Sort by function nameHit count Sort by hit count
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:020.0 %
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:020.0 %
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Generated by: LCOV version 1.13
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
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_ZN12MemSpecGDDR5D0Ev0
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:020.0 %
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:2728.6 %
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Date:2020-06-30 17:34:44Functions:2728.6 %
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:2728.6 %
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/configuration/memspec - MemSpecGDDR5X.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/configuration/memspec - MemSpecGDDR5X.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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_ZN13MemSpecGDDR5XD0Ev0
_ZN13MemSpecGDDR5XD2Ev0
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+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h.gcov.html b/html/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h.gcov.html new file mode 100644 index 00000000..74587f73 --- /dev/null +++ b/html/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h.gcov.html @@ -0,0 +1,127 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h + + + + + + + + + + + + + + +
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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+
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:2728.6 %
Legend: Lines: + hit + not hit +
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Date:2020-06-30 17:34:44Functions:2728.6 %
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:2728.6 %
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/configuration/memspec - MemSpecGDDR6.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_ZN12MemSpecGDDR6D0Ev0
_ZN12MemSpecGDDR6D2Ev0
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/configuration/memspec - MemSpecGDDR6.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
+
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          Line data    Source code
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/configuration/memspec - MemSpecHBM2.cpp (source / functions)HitTotalCoverage
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Date:2020-06-30 17:34:44Functions:6785.7 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:6785.7 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Date:2020-06-30 17:34:44Functions:6785.7 %
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Generated by: LCOV version 1.13
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:020.0 %
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Generated by: LCOV version 1.13
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:020.0 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/configuration/memspec - MemSpecWideIO2.h (source / functions)HitTotalCoverage
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
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_ZN14MemSpecWideIO2D2Ev0
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/configuration/memspec - MemSpecWideIO2.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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_ZN14MemSpecWideIO2D0Ev0
_ZN14MemSpecWideIO2D2Ev0
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h.gcov.html b/html/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h.gcov.html new file mode 100644 index 00000000..6190b79b --- /dev/null +++ b/html/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h.gcov.html @@ -0,0 +1,127 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/configuration/memspec - MemSpecWideIO2.h (source / functions)HitTotalCoverage
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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          Line data    Source code
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/configuration/memspec/index-sort-f.html b/html/DRAMSys/library/src/configuration/memspec/index-sort-f.html new file mode 100644 index 00000000..cd1f2b8f --- /dev/null +++ b/html/DRAMSys/library/src/configuration/memspec/index-sort-f.html @@ -0,0 +1,293 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/configuration/memspec + + + + + + + + + + + + + + +
LCOV - code coverage report
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:388743.7 %
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
MemSpecDDR3.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecLPDDR4.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecHBM2.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecGDDR5X.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpec.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecWideIO.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecGDDR6.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecWideIO2.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecGDDR5.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecDDR4.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecWideIO.cpp +
1.2%1.2%
+ 		1.2 %1 / 8428.6 %2 / 7
MemSpecWideIO2.cpp +
1.4%1.4%
+ 		1.4 %1 / 6928.6 %2 / 7
MemSpecGDDR6.cpp +
1.2%1.2%
+ 		1.2 %1 / 8128.6 %2 / 7
MemSpecGDDR5.cpp +
1.3%1.3%
+ 		1.3 %1 / 7928.6 %2 / 7
MemSpecGDDR5X.cpp +
1.3%1.3%
+ 		1.3 %1 / 7928.6 %2 / 7
MemSpecDDR3.cpp +
90.8%90.8%
+ 		90.8 %69 / 7685.7 %6 / 7
MemSpecDDR4.cpp +
91.4%91.4%
+ 		91.4 %85 / 9385.7 %6 / 7
MemSpecLPDDR4.cpp +
92.9%92.9%
+ 		92.9 %78 / 8485.7 %6 / 7
MemSpecHBM2.cpp +
89.0%89.0%
+ 		89.0 %65 / 7385.7 %6 / 7
MemSpec.cpp +
100.0%
+ 		100.0 %17 / 17100.0 %4 / 4
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/configuration/memspec/index-sort-l.html b/html/DRAMSys/library/src/configuration/memspec/index-sort-l.html new file mode 100644 index 00000000..1588841f --- /dev/null +++ b/html/DRAMSys/library/src/configuration/memspec/index-sort-l.html @@ -0,0 +1,293 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/configuration/memspec + + + + + + + + + + + + + + +
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
MemSpecDDR3.h +
0.0%
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MemSpecLPDDR4.h +
0.0%
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MemSpecHBM2.h +
0.0%
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MemSpecGDDR5X.h +
0.0%
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MemSpec.h +
0.0%
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MemSpecWideIO.h +
0.0%
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MemSpecGDDR6.h +
0.0%
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MemSpecWideIO2.h +
0.0%
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MemSpecGDDR5.h +
0.0%
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MemSpecDDR4.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecWideIO.cpp +
1.2%1.2%
+ 		1.2 %1 / 8428.6 %2 / 7
MemSpecGDDR5.cpp +
1.3%1.3%
+ 		1.3 %1 / 7928.6 %2 / 7
MemSpecGDDR5X.cpp +
1.3%1.3%
+ 		1.3 %1 / 7928.6 %2 / 7
MemSpecGDDR6.cpp +
1.2%1.2%
+ 		1.2 %1 / 8128.6 %2 / 7
MemSpecWideIO2.cpp +
1.4%1.4%
+ 		1.4 %1 / 6928.6 %2 / 7
MemSpecHBM2.cpp +
89.0%89.0%
+ 		89.0 %65 / 7385.7 %6 / 7
MemSpecDDR3.cpp +
90.8%90.8%
+ 		90.8 %69 / 7685.7 %6 / 7
MemSpecDDR4.cpp +
91.4%91.4%
+ 		91.4 %85 / 9385.7 %6 / 7
MemSpecLPDDR4.cpp +
92.9%92.9%
+ 		92.9 %78 / 8485.7 %6 / 7
MemSpec.cpp +
100.0%
+ 		100.0 %17 / 17100.0 %4 / 4
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/configuration/memspec/index.html b/html/DRAMSys/library/src/configuration/memspec/index.html new file mode 100644 index 00000000..561d4bd6 --- /dev/null +++ b/html/DRAMSys/library/src/configuration/memspec/index.html @@ -0,0 +1,293 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/configuration/memspec + + + + + + + + + + + + + + +
LCOV - code coverage report
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:31974542.8 %
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
MemSpec.cpp +
100.0%
+ 		100.0 %17 / 17100.0 %4 / 4
MemSpec.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecDDR3.cpp +
90.8%90.8%
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MemSpecDDR3.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecDDR4.cpp +
91.4%91.4%
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MemSpecDDR4.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecGDDR5.cpp +
1.3%1.3%
+ 		1.3 %1 / 7928.6 %2 / 7
MemSpecGDDR5.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecGDDR5X.cpp +
1.3%1.3%
+ 		1.3 %1 / 7928.6 %2 / 7
MemSpecGDDR5X.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecGDDR6.cpp +
1.2%1.2%
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MemSpecGDDR6.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecHBM2.cpp +
89.0%89.0%
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MemSpecHBM2.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecLPDDR4.cpp +
92.9%92.9%
+ 		92.9 %78 / 8485.7 %6 / 7
MemSpecLPDDR4.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecWideIO.cpp +
1.2%1.2%
+ 		1.2 %1 / 8428.6 %2 / 7
MemSpecWideIO.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
MemSpecWideIO2.cpp +
1.4%1.4%
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MemSpecWideIO2.h +
0.0%
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+
+
+ + + + +
Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/controller/BankMachine.cpp.func-sort-c.html b/html/DRAMSys/library/src/controller/BankMachine.cpp.func-sort-c.html new file mode 100644 index 00000000..81786ff7 --- /dev/null +++ b/html/DRAMSys/library/src/controller/BankMachine.cpp.func-sort-c.html @@ -0,0 +1,161 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/BankMachine.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller - BankMachine.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:14916689.8 %
Date:2020-06-30 17:34:44Functions:192095.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_ZN11BankMachine7getRankEv0
_GLOBAL__sub_I__ZN11BankMachineC2EP11SchedulerIFP9CheckerIF4Bank30
_Z41__static_initialization_and_destruction_0ii30
_ZN15BankMachineOpenC2EP11SchedulerIFP9CheckerIF4Bank80
_ZN23BankMachineOpenAdaptiveC2EP11SchedulerIFP9CheckerIF4Bank96
_ZN25BankMachineClosedAdaptiveC2EP11SchedulerIFP9CheckerIF4Bank96
_ZN17BankMachineClosedC2EP11SchedulerIFP9CheckerIF4Bank224
_ZN11BankMachineC2EP11SchedulerIFP9CheckerIF4Bank496
_ZN11BankMachine6isIdleEv29802
_ZN15BankMachineOpen5startEv71650
_ZN11BankMachine12getBankGroupEv87408
_ZN11BankMachine5blockEv133592
_ZN11BankMachine11updateStateE7Command426310
_ZN11BankMachine10getOpenRowEv2541205
_ZN17BankMachineClosed5startEv3416112
_ZN23BankMachineOpenAdaptive5startEv4507416
_ZN25BankMachineClosedAdaptive5startEv5314560
_ZN11BankMachine8getStateEv5446696
_ZN11BankMachine14getNextCommandEv13032248
_ZN11BankMachine7getBankEv13390075
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+
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/BankMachine.cpp.func.html b/html/DRAMSys/library/src/controller/BankMachine.cpp.func.html new file mode 100644 index 00000000..96b534a6 --- /dev/null +++ b/html/DRAMSys/library/src/controller/BankMachine.cpp.func.html @@ -0,0 +1,161 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/BankMachine.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller - BankMachine.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:14916689.8 %
Date:2020-06-30 17:34:44Functions:192095.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN11BankMachineC2EP11SchedulerIFP9CheckerIF4Bank30
_Z41__static_initialization_and_destruction_0ii30
_ZN11BankMachine10getOpenRowEv2541205
_ZN11BankMachine11updateStateE7Command426310
_ZN11BankMachine12getBankGroupEv87408
_ZN11BankMachine14getNextCommandEv13032248
_ZN11BankMachine5blockEv133592
_ZN11BankMachine6isIdleEv29802
_ZN11BankMachine7getBankEv13390075
_ZN11BankMachine7getRankEv0
_ZN11BankMachine8getStateEv5446696
_ZN11BankMachineC2EP11SchedulerIFP9CheckerIF4Bank496
_ZN15BankMachineOpen5startEv71650
_ZN15BankMachineOpenC2EP11SchedulerIFP9CheckerIF4Bank80
_ZN17BankMachineClosed5startEv3416112
_ZN17BankMachineClosedC2EP11SchedulerIFP9CheckerIF4Bank224
_ZN23BankMachineOpenAdaptive5startEv4507416
_ZN23BankMachineOpenAdaptiveC2EP11SchedulerIFP9CheckerIF4Bank96
_ZN25BankMachineClosedAdaptive5startEv5314560
_ZN25BankMachineClosedAdaptiveC2EP11SchedulerIFP9CheckerIF4Bank96
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/BankMachine.cpp.gcov.html b/html/DRAMSys/library/src/controller/BankMachine.cpp.gcov.html new file mode 100644 index 00000000..abffb038 --- /dev/null +++ b/html/DRAMSys/library/src/controller/BankMachine.cpp.gcov.html @@ -0,0 +1,413 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/BankMachine.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller - BankMachine.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:14916689.8 %
Date:2020-06-30 17:34:44Functions:192095.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
+
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+
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/BankMachine.h.func-sort-c.html b/html/DRAMSys/library/src/controller/BankMachine.h.func-sort-c.html new file mode 100644 index 00000000..18d208df --- /dev/null +++ b/html/DRAMSys/library/src/controller/BankMachine.h.func-sort-c.html @@ -0,0 +1,113 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/BankMachine.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller - BankMachine.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:44100.0 %
Date:2020-06-30 17:34:44Functions:4850.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN15BankMachineOpenD2Ev0
_ZN17BankMachineClosedD2Ev0
_ZN23BankMachineOpenAdaptiveD2Ev0
_ZN25BankMachineClosedAdaptiveD2Ev0
_ZN15BankMachineOpenD0Ev80
_ZN23BankMachineOpenAdaptiveD0Ev96
_ZN25BankMachineClosedAdaptiveD0Ev96
_ZN17BankMachineClosedD0Ev224
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/BankMachine.h.func.html b/html/DRAMSys/library/src/controller/BankMachine.h.func.html new file mode 100644 index 00000000..3a74d303 --- /dev/null +++ b/html/DRAMSys/library/src/controller/BankMachine.h.func.html @@ -0,0 +1,113 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/BankMachine.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller - BankMachine.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:44100.0 %
Date:2020-06-30 17:34:44Functions:4850.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN15BankMachineOpenD0Ev80
_ZN15BankMachineOpenD2Ev0
_ZN17BankMachineClosedD0Ev224
_ZN17BankMachineClosedD2Ev0
_ZN23BankMachineOpenAdaptiveD0Ev96
_ZN23BankMachineOpenAdaptiveD2Ev0
_ZN25BankMachineClosedAdaptiveD0Ev96
_ZN25BankMachineClosedAdaptiveD2Ev0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/BankMachine.h.gcov.html b/html/DRAMSys/library/src/controller/BankMachine.h.gcov.html new file mode 100644 index 00000000..748e98a6 --- /dev/null +++ b/html/DRAMSys/library/src/controller/BankMachine.h.gcov.html @@ -0,0 +1,194 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/BankMachine.h + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller - BankMachine.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:44100.0 %
Date:2020-06-30 17:34:44Functions:4850.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
+
+       1             : /* EOF */
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+
+
+
+ + + + +
Generated by: LCOV version 1.13
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller - Command.cpp (source / functions)HitTotalCoverage
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Generated by: LCOV version 1.13
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:101376.9 %
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:00-
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Generated by: LCOV version 1.13
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Generated by: LCOV version 1.13
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+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/ControllerIF.h.func-sort-c.html b/html/DRAMSys/library/src/controller/ControllerIF.h.func-sort-c.html new file mode 100644 index 00000000..96c7f683 --- /dev/null +++ b/html/DRAMSys/library/src/controller/ControllerIF.h.func-sort-c.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/ControllerIF.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller - ControllerIF.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:4646100.0 %
Date:2020-06-30 17:34:44Functions:3475.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN12ControllerIFD0Ev0
_ZN12ControllerIFC2EN7sc_core14sc_module_nameE37
_ZN12ControllerIFD2Ev37
_ZN12ControllerIF17IdleTimeCollector3endEv97
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/ControllerIF.h.func.html b/html/DRAMSys/library/src/controller/ControllerIF.h.func.html new file mode 100644 index 00000000..526bbfb9 --- /dev/null +++ b/html/DRAMSys/library/src/controller/ControllerIF.h.func.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/ControllerIF.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller - ControllerIF.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:4646100.0 %
Date:2020-06-30 17:34:44Functions:3475.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN12ControllerIF17IdleTimeCollector3endEv97
_ZN12ControllerIFC2EN7sc_core14sc_module_nameE37
_ZN12ControllerIFD0Ev0
_ZN12ControllerIFD2Ev37
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/ControllerIF.h.gcov.html b/html/DRAMSys/library/src/controller/ControllerIF.h.gcov.html new file mode 100644 index 00000000..1d6c244d --- /dev/null +++ b/html/DRAMSys/library/src/controller/ControllerIF.h.gcov.html @@ -0,0 +1,186 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/ControllerIF.h + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller - ControllerIF.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:4646100.0 %
Date:2020-06-30 17:34:44Functions:3475.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
+
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+
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/ControllerRecordable.cpp.func-sort-c.html b/html/DRAMSys/library/src/controller/ControllerRecordable.cpp.func-sort-c.html new file mode 100644 index 00000000..e4745626 --- /dev/null +++ b/html/DRAMSys/library/src/controller/ControllerRecordable.cpp.func-sort-c.html @@ -0,0 +1,109 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/ControllerRecordable.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller - ControllerRecordable.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:252889.3 %
Date:2020-06-30 17:34:44Functions:6785.7 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN20ControllerRecordable15nb_transport_bwERN3tlm19tlm_generic_payloadERNS0_9tlm_phaseERN7sc_core7sc_timeE0
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerDDR3.h.func-sort-c.html b/html/DRAMSys/library/src/controller/checker/CheckerDDR3.h.func-sort-c.html new file mode 100644 index 00000000..6014d036 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerDDR3.h.func-sort-c.html @@ -0,0 +1,85 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerDDR3.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerDDR3.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN11CheckerDDR3D0Ev5
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerDDR3.h.func.html b/html/DRAMSys/library/src/controller/checker/CheckerDDR3.h.func.html new file mode 100644 index 00000000..26d34832 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerDDR3.h.func.html @@ -0,0 +1,85 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerDDR3.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerDDR3.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN11CheckerDDR3D0Ev5
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerDDR3.h.gcov.html b/html/DRAMSys/library/src/controller/checker/CheckerDDR3.h.gcov.html new file mode 100644 index 00000000..22766102 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerDDR3.h.gcov.html @@ -0,0 +1,129 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerDDR3.h + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerDDR3.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
+
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+
+
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp.func-sort-c.html b/html/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp.func-sort-c.html new file mode 100644 index 00000000..456641f3 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp.func-sort-c.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerDDR4.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerDDR4.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:18730860.7 %
Date:2020-06-30 17:34:44Functions:55100.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN11CheckerDDR4C2Ev30
_Z41__static_initialization_and_destruction_0ii30
_ZN11CheckerDDR46insertE7Command4Rank9BankGroup4Bank166614
_ZNK11CheckerDDR424timeToSatisfyConstraintsE7Command4Rank9BankGroup4Bank5298882
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp.func.html b/html/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp.func.html new file mode 100644 index 00000000..ae2e63bf --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp.func.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerDDR4.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerDDR4.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:18730860.7 %
Date:2020-06-30 17:34:44Functions:55100.0 %
Legend: Lines: + hit + not hit +
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+ +
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Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN11CheckerDDR4C2Ev30
_Z41__static_initialization_and_destruction_0ii30
_ZN11CheckerDDR46insertE7Command4Rank9BankGroup4Bank166614
_ZNK11CheckerDDR424timeToSatisfyConstraintsE7Command4Rank9BankGroup4Bank5298882
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp.gcov.html b/html/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp.gcov.html new file mode 100644 index 00000000..dc96b501 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp.gcov.html @@ -0,0 +1,547 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerDDR4.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerDDR4.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:18730860.7 %
Date:2020-06-30 17:34:44Functions:55100.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
+
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerDDR4.h.func-sort-c.html b/html/DRAMSys/library/src/controller/checker/CheckerDDR4.h.func-sort-c.html new file mode 100644 index 00000000..808fa173 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerDDR4.h.func-sort-c.html @@ -0,0 +1,85 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerDDR4.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerDDR4.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
Legend: Lines: + hit + not hit +
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+ +
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Function Name Sort by function nameHit count Sort by hit count
_ZN11CheckerDDR4D0Ev6
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerDDR4.h.func.html b/html/DRAMSys/library/src/controller/checker/CheckerDDR4.h.func.html new file mode 100644 index 00000000..a1ebbff8 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerDDR4.h.func.html @@ -0,0 +1,85 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerDDR4.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerDDR4.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN11CheckerDDR4D0Ev6
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerDDR4.h.gcov.html b/html/DRAMSys/library/src/controller/checker/CheckerDDR4.h.gcov.html new file mode 100644 index 00000000..d40679f5 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerDDR4.h.gcov.html @@ -0,0 +1,129 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerDDR4.h + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerDDR4.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp.func-sort-c.html b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp.func-sort-c.html new file mode 100644 index 00000000..d984585f --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp.func-sort-c.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerGDDR5.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:13700.3 %
Date:2020-06-30 17:34:44Functions:2540.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_ZN12CheckerGDDR56insertE7Command4Rank9BankGroup4Bank0
_ZNK12CheckerGDDR524timeToSatisfyConstraintsE7Command4Rank9BankGroup4Bank0
_GLOBAL__sub_I__ZN12CheckerGDDR5C2Ev30
_Z41__static_initialization_and_destruction_0ii30
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp.func.html b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp.func.html new file mode 100644 index 00000000..166bbf28 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp.func.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerGDDR5.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:13700.3 %
Date:2020-06-30 17:34:44Functions:2540.0 %
Legend: Lines: + hit + not hit +
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+ +
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Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN12CheckerGDDR5C2Ev30
_Z41__static_initialization_and_destruction_0ii30
_ZN12CheckerGDDR56insertE7Command4Rank9BankGroup4Bank0
_ZNK12CheckerGDDR524timeToSatisfyConstraintsE7Command4Rank9BankGroup4Bank0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp.gcov.html b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp.gcov.html new file mode 100644 index 00000000..4f3a4c50 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp.gcov.html @@ -0,0 +1,636 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerGDDR5.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:13700.3 %
Date:2020-06-30 17:34:44Functions:2540.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
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+
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+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerGDDR5.h.func-sort-c.html b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5.h.func-sort-c.html new file mode 100644 index 00000000..0d5c1e82 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5.h.func-sort-c.html @@ -0,0 +1,85 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerGDDR5.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerGDDR5.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN12CheckerGDDR5D0Ev0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerGDDR5.h.func.html b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5.h.func.html new file mode 100644 index 00000000..b92b3e8d --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5.h.func.html @@ -0,0 +1,85 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerGDDR5.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerGDDR5.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN12CheckerGDDR5D0Ev0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerGDDR5.h.gcov.html b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5.h.gcov.html new file mode 100644 index 00000000..ee020294 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5.h.gcov.html @@ -0,0 +1,129 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerGDDR5.h + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerGDDR5.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
+
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+
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+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp.func-sort-c.html b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp.func-sort-c.html new file mode 100644 index 00000000..d90fa150 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp.func-sort-c.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerGDDR5X.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:13700.3 %
Date:2020-06-30 17:34:44Functions:2540.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN13CheckerGDDR5X6insertE7Command4Rank9BankGroup4Bank0
_ZNK13CheckerGDDR5X24timeToSatisfyConstraintsE7Command4Rank9BankGroup4Bank0
_GLOBAL__sub_I__ZN13CheckerGDDR5XC2Ev30
_Z41__static_initialization_and_destruction_0ii30
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp.func.html b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp.func.html new file mode 100644 index 00000000..a89b2ed6 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp.func.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/checker - CheckerGDDR5X.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:13700.3 %
Date:2020-06-30 17:34:44Functions:2540.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN13CheckerGDDR5XC2Ev30
_Z41__static_initialization_and_destruction_0ii30
_ZN13CheckerGDDR5X6insertE7Command4Rank9BankGroup4Bank0
_ZNK13CheckerGDDR5X24timeToSatisfyConstraintsE7Command4Rank9BankGroup4Bank0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp.gcov.html b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp.gcov.html new file mode 100644 index 00000000..b7d0a57f --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp.gcov.html @@ -0,0 +1,636 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/checker - CheckerGDDR5X.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:13700.3 %
Date:2020-06-30 17:34:44Functions:2540.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
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+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h.func-sort-c.html b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h.func-sort-c.html new file mode 100644 index 00000000..aef249ed --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h.func-sort-c.html @@ -0,0 +1,85 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerGDDR5X.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/checker - CheckerGDDR5X.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
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Function Name Sort by function nameHit count Sort by hit count
_ZN13CheckerGDDR5XD0Ev0
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+
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h.func.html b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h.func.html new file mode 100644 index 00000000..49f39f2a --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h.func.html @@ -0,0 +1,85 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerGDDR5X.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerGDDR5X.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN13CheckerGDDR5XD0Ev0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h.gcov.html b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h.gcov.html new file mode 100644 index 00000000..3455df81 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h.gcov.html @@ -0,0 +1,129 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerGDDR5X.h + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerGDDR5X.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp.func-sort-c.html b/html/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp.func-sort-c.html new file mode 100644 index 00000000..78000dfe --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp.func-sort-c.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerGDDR6.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:13830.3 %
Date:2020-06-30 17:34:44Functions:2540.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_ZN12CheckerGDDR66insertE7Command4Rank9BankGroup4Bank0
_ZNK12CheckerGDDR624timeToSatisfyConstraintsE7Command4Rank9BankGroup4Bank0
_GLOBAL__sub_I__ZN12CheckerGDDR6C2Ev30
_Z41__static_initialization_and_destruction_0ii30
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+
+ + + +
Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp.func.html b/html/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp.func.html new file mode 100644 index 00000000..5300d12e --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp.func.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerGDDR6.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:13830.3 %
Date:2020-06-30 17:34:44Functions:2540.0 %
Legend: Lines: + hit + not hit +
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+ +
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Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN12CheckerGDDR6C2Ev30
_Z41__static_initialization_and_destruction_0ii30
_ZN12CheckerGDDR66insertE7Command4Rank9BankGroup4Bank0
_ZNK12CheckerGDDR624timeToSatisfyConstraintsE7Command4Rank9BankGroup4Bank0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp.gcov.html b/html/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp.gcov.html new file mode 100644 index 00000000..e6b0187c --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp.gcov.html @@ -0,0 +1,653 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerGDDR6.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:13830.3 %
Date:2020-06-30 17:34:44Functions:2540.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
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Date:2020-06-30 17:34:44Functions:020.0 %
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_ZN12CheckerGDDR6D0Ev0
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Generated by: LCOV version 1.13
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
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Function Name Sort by function nameHit count Sort by hit count
_ZN12CheckerGDDR6D0Ev0
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Generated by: LCOV version 1.13
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerHBM2.cpp (source / functions)HitTotalCoverage
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Generated by: LCOV version 1.13
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:55100.0 %
Legend: Lines: + hit + not hit +
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerHBM2.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:22100.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_ZN11CheckerHBM2D0Ev14
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerHBM2.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_ZN11CheckerHBM2D0Ev14
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerHBM2.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerLPDDR4.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:17734551.3 %
Date:2020-06-30 17:34:44Functions:55100.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
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_ZN13CheckerLPDDR46insertE7Command4Rank9BankGroup4Bank191436
_ZNK13CheckerLPDDR424timeToSatisfyConstraintsE7Command4Rank9BankGroup4Bank4496580
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerLPDDR4.cpp (source / functions)HitTotalCoverage
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Date:2020-06-30 17:34:44Functions:55100.0 %
Legend: Lines: + hit + not hit +
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_Z41__static_initialization_and_destruction_0ii30
_ZN13CheckerLPDDR46insertE7Command4Rank9BankGroup4Bank191436
_ZNK13CheckerLPDDR424timeToSatisfyConstraintsE7Command4Rank9BankGroup4Bank4496580
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Generated by: LCOV version 1.13
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:17734551.3 %
Date:2020-06-30 17:34:44Functions:55100.0 %
Legend: Lines: + hit + not hit +
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+
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h.func-sort-c.html b/html/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h.func-sort-c.html new file mode 100644 index 00000000..84c08e27 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h.func-sort-c.html @@ -0,0 +1,85 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerLPDDR4.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/checker - CheckerLPDDR4.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN13CheckerLPDDR4D0Ev12
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h.func.html b/html/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h.func.html new file mode 100644 index 00000000..77dc7ca6 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h.func.html @@ -0,0 +1,85 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerLPDDR4.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/checker - CheckerLPDDR4.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN13CheckerLPDDR4D0Ev12
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h.gcov.html b/html/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h.gcov.html new file mode 100644 index 00000000..1cb40aec --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h.gcov.html @@ -0,0 +1,129 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerLPDDR4.h + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/checker - CheckerLPDDR4.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
+
+       1             : /* EOF */
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+      44          36 : /* EOF */
+
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp.func-sort-c.html b/html/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp.func-sort-c.html new file mode 100644 index 00000000..3b0589c5 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp.func-sort-c.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerWideIO.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/checker - CheckerWideIO.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:12610.4 %
Date:2020-06-30 17:34:44Functions:2540.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN13CheckerWideIO6insertE7Command4Rank9BankGroup4Bank0
_ZNK13CheckerWideIO24timeToSatisfyConstraintsE7Command4Rank9BankGroup4Bank0
_GLOBAL__sub_I__ZN13CheckerWideIOC2Ev30
_Z41__static_initialization_and_destruction_0ii30
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp.func.html b/html/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp.func.html new file mode 100644 index 00000000..1fd9161f --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp.func.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerWideIO.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/checker - CheckerWideIO.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:12610.4 %
Date:2020-06-30 17:34:44Functions:2540.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN13CheckerWideIOC2Ev30
_Z41__static_initialization_and_destruction_0ii30
_ZN13CheckerWideIO6insertE7Command4Rank9BankGroup4Bank0
_ZNK13CheckerWideIO24timeToSatisfyConstraintsE7Command4Rank9BankGroup4Bank0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp.gcov.html b/html/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp.gcov.html new file mode 100644 index 00000000..3aac699e --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp.gcov.html @@ -0,0 +1,488 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerWideIO.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerWideIO.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:2540.0 %
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+ + + + + + + + +

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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerWideIO.h.func-sort-c.html b/html/DRAMSys/library/src/controller/checker/CheckerWideIO.h.func-sort-c.html new file mode 100644 index 00000000..3acc04e7 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerWideIO.h.func-sort-c.html @@ -0,0 +1,85 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerWideIO.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerWideIO.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_ZN13CheckerWideIOD0Ev0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerWideIO.h.func.html b/html/DRAMSys/library/src/controller/checker/CheckerWideIO.h.func.html new file mode 100644 index 00000000..8f353c6d --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerWideIO.h.func.html @@ -0,0 +1,85 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerWideIO.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/checker - CheckerWideIO.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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+ +
+ + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN13CheckerWideIOD0Ev0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerWideIO.h.gcov.html b/html/DRAMSys/library/src/controller/checker/CheckerWideIO.h.gcov.html new file mode 100644 index 00000000..1917edf2 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerWideIO.h.gcov.html @@ -0,0 +1,129 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerWideIO.h + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/checker - CheckerWideIO.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
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+
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+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp.func-sort-c.html b/html/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp.func-sort-c.html new file mode 100644 index 00000000..60ff6630 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp.func-sort-c.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerWideIO2.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:13200.3 %
Date:2020-06-30 17:34:44Functions:2540.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_ZN14CheckerWideIO26insertE7Command4Rank9BankGroup4Bank0
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_GLOBAL__sub_I__ZN14CheckerWideIO2C2Ev30
_Z41__static_initialization_and_destruction_0ii30
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp.func.html b/html/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp.func.html new file mode 100644 index 00000000..6eb0f810 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp.func.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerWideIO2.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:13200.3 %
Date:2020-06-30 17:34:44Functions:2540.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp.gcov.html b/html/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp.gcov.html new file mode 100644 index 00000000..552203ae --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp.gcov.html @@ -0,0 +1,566 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerWideIO2.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:13200.3 %
Date:2020-06-30 17:34:44Functions:2540.0 %
Legend: Lines: + hit + not hit +
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+ + + + + + + + +

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+
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+ + + + +
Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerWideIO2.h.func-sort-c.html b/html/DRAMSys/library/src/controller/checker/CheckerWideIO2.h.func-sort-c.html new file mode 100644 index 00000000..eb04eac0 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerWideIO2.h.func-sort-c.html @@ -0,0 +1,85 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerWideIO2.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/checker - CheckerWideIO2.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN14CheckerWideIO2D0Ev0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerWideIO2.h.func.html b/html/DRAMSys/library/src/controller/checker/CheckerWideIO2.h.func.html new file mode 100644 index 00000000..285aafb5 --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerWideIO2.h.func.html @@ -0,0 +1,85 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerWideIO2.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/checker - CheckerWideIO2.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN14CheckerWideIO2D0Ev0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/checker/CheckerWideIO2.h.gcov.html b/html/DRAMSys/library/src/controller/checker/CheckerWideIO2.h.gcov.html new file mode 100644 index 00000000..2f4b5d0d --- /dev/null +++ b/html/DRAMSys/library/src/controller/checker/CheckerWideIO2.h.gcov.html @@ -0,0 +1,129 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerWideIO2.h + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/controller/checker - CheckerWideIO2.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:386360.3 %
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
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0.3%0.3%
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CheckerGDDR5.cpp +
0.3%0.3%
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CheckerWideIO2.cpp +
0.3%0.3%
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CheckerGDDR6.cpp +
0.3%0.3%
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CheckerWideIO.cpp +
0.4%0.4%
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CheckerDDR4.h +
100.0%
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100.0%
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CheckerHBM2.h +
100.0%
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100.0%
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CheckerDDR4.cpp +
60.7%60.7%
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CheckerDDR3.cpp +
89.7%89.7%
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CheckerLPDDR4.cpp +
51.3%51.3%
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CheckerHBM2.cpp +
51.9%51.9%
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+
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Generated by: LCOV version 1.13
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
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0.3%0.3%
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0.3%0.3%
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0.3%0.3%
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CheckerWideIO.cpp +
0.4%0.4%
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CheckerWideIO2.cpp +
0.3%0.3%
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51.3%51.3%
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51.9%51.9%
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60.7%60.7%
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CheckerDDR3.cpp +
89.7%89.7%
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100.0%
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CheckerLPDDR4.h +
100.0%
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100.0%
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100.0%
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+
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Generated by: LCOV version 1.13
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
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89.7%89.7%
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100.0%
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60.7%60.7%
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100.0%
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0.3%0.3%
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0.3%0.3%
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0.3%0.3%
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51.9%51.9%
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100.0%
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51.3%51.3%
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CheckerLPDDR4.h +
100.0%
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0.4%0.4%
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0.0%
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0.3%0.3%
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0.0%
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:33100.0 %
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/controller/cmdmux - CmdMuxOldest.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:33100.0 %
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Function Name Sort by function nameHit count Sort by hit count
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/controller/cmdmux - CmdMuxOldest.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:33100.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/controller/cmdmux - CmdMuxOldest.h (source / functions)HitTotalCoverage
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Date:2020-06-30 17:34:44Functions:1250.0 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/cmdmux - CmdMuxOldest.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:1250.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/controller/cmdmux - CmdMuxOldest.h (source / functions)HitTotalCoverage
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Legend: Lines: + hit + not hit +
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100.0%
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100.0%
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100.0%
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100.0%
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72.0%72.0%
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89.3%89.3%
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100.0%
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100.0%
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100.0%
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Generated by: LCOV version 1.13
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BankMachine.cpp +
89.8%89.8%
+ 		89.8 %149 / 16695.0 %19 / 20
BankMachine.h +
100.0%
+ 		100.0 %4 / 450.0 %4 / 8
Command.cpp +
72.0%72.0%
+ 		72.0 %18 / 2576.9 %10 / 13
Command.h +
100.0%
+ 		100.0 %24 / 24-0 / 0
Controller.cpp +
87.3%87.3%
+ 		87.3 %192 / 22073.3 %11 / 15
ControllerIF.h +
100.0%
+ 		100.0 %46 / 4675.0 %3 / 4
ControllerRecordable.cpp +
89.3%89.3%
+ 		89.3 %25 / 2885.7 %6 / 7
ControllerRecordable.h +
100.0%
+ 		100.0 %3 / 366.7 %2 / 3
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+
+ + + + +
Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp.func-sort-c.html b/html/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp.func-sort-c.html new file mode 100644 index 00000000..0e700a88 --- /dev/null +++ b/html/DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp.func-sort-c.html @@ -0,0 +1,93 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/powerdown - PowerDownManagerDummy.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:55100.0 %
Date:2020-06-30 17:34:44Functions:44100.0 %
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_ZN21PowerDownManagerDummy14getNextCommandEv1085867
_ZN21PowerDownManagerDummy5startEv2171734
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/controller/powerdown - PowerDownManagerDummy.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:55100.0 %
Date:2020-06-30 17:34:44Functions:44100.0 %
Legend: Lines: + hit + not hit +
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_ZN21PowerDownManagerDummy14getNextCommandEv1085867
_ZN21PowerDownManagerDummy5startEv2171734
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/controller/powerdown - PowerDownManagerDummy.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:55100.0 %
Date:2020-06-30 17:34:44Functions:44100.0 %
Legend: Lines: + hit + not hit +
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          Line data    Source code
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/controller/powerdown - PowerDownManagerDummy.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:5683.3 %
Legend: Lines: + hit + not hit +
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_ZN21PowerDownManagerDummy11updateStateE7Command416430
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Generated by: LCOV version 1.13
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:66100.0 %
Date:2020-06-30 17:34:44Functions:5683.3 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
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_ZN21PowerDownManagerDummyD2Ev0
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/controller/powerdown - PowerDownManagerDummy.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:66100.0 %
Date:2020-06-30 17:34:44Functions:5683.3 %
Legend: Lines: + hit + not hit +
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+
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/powerdown - PowerDownManagerStaggered.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:899296.7 %
Date:2020-06-30 17:34:44Functions:99100.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_ZN25PowerDownManagerStaggeredC2E4RankP9CheckerIF10
_ZN25PowerDownManagerStaggered11triggerExitEv20
_GLOBAL__sub_I__ZN25PowerDownManagerStaggeredC2E4RankP9CheckerIF30
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_ZN25PowerDownManagerStaggered14getNextCommandEv8790
_ZN25PowerDownManagerStaggered5startEv17580
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp.func.html b/html/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp.func.html new file mode 100644 index 00000000..8f756f4d --- /dev/null +++ b/html/DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp.func.html @@ -0,0 +1,117 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/powerdown - PowerDownManagerStaggered.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:899296.7 %
Date:2020-06-30 17:34:44Functions:99100.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN25PowerDownManagerStaggeredC2E4RankP9CheckerIF30
_Z41__static_initialization_and_destruction_0ii30
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_ZN25PowerDownManagerStaggered5startEv17580
_ZN25PowerDownManagerStaggeredC2E4RankP9CheckerIF10
+
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:99100.0 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/powerdown - PowerDownManagerStaggered.h (source / functions)HitTotalCoverage
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Date:2020-06-30 17:34:44Functions:1250.0 %
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/controller/powerdown - PowerDownManagerStaggered.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:1250.0 %
Legend: Lines: + hit + not hit +
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_ZN25PowerDownManagerStaggeredD2Ev0
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/controller/powerdown - PowerDownManagerStaggered.h (source / functions)HitTotalCoverage
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Date:2020-06-30 17:34:44Functions:1250.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:192190.5 %
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
PowerDownManagerStaggered.h +
100.0%
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100.0%
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PowerDownManagerDummy.cpp +
100.0%
+ 		100.0 %5 / 5100.0 %4 / 4
PowerDownManagerStaggered.cpp +
96.7%96.7%
+ 		96.7 %89 / 92100.0 %9 / 9
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+
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Generated by: LCOV version 1.13
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
PowerDownManagerStaggered.cpp +
96.7%96.7%
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PowerDownManagerStaggered.h +
100.0%
+ 		100.0 %1 / 150.0 %1 / 2
PowerDownManagerDummy.cpp +
100.0%
+ 		100.0 %5 / 5100.0 %4 / 4
PowerDownManagerDummy.h +
100.0%
+ 		100.0 %6 / 683.3 %5 / 6
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/powerdown/index.html b/html/DRAMSys/library/src/controller/powerdown/index.html new file mode 100644 index 00000000..315dfdbd --- /dev/null +++ b/html/DRAMSys/library/src/controller/powerdown/index.html @@ -0,0 +1,133 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/powerdown + + + + + + + + + + + + + + +
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
PowerDownManagerDummy.cpp +
100.0%
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PowerDownManagerDummy.h +
100.0%
+ 		100.0 %6 / 683.3 %5 / 6
PowerDownManagerStaggered.cpp +
96.7%96.7%
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PowerDownManagerStaggered.h +
100.0%
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/refresh - RefreshManagerBankwise.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:66100.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
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Generated by: LCOV version 1.13
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Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h.func-sort-c.html b/html/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h.func-sort-c.html new file mode 100644 index 00000000..549375c0 --- /dev/null +++ b/html/DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h.func-sort-c.html @@ -0,0 +1,85 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/refresh - RefreshManagerBankwise.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
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Function Name Sort by function nameHit count Sort by hit count
_ZN22RefreshManagerBankwiseD0Ev12
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Generated by: LCOV version 1.13
+
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/refresh - RefreshManagerBankwise.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_ZN22RefreshManagerBankwiseD0Ev12
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Generated by: LCOV version 1.13
+
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/refresh - RefreshManagerBankwise.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
+
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/refresh - RefreshManagerDummy.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:2450.0 %
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Function Name Sort by function nameHit count Sort by hit count
_ZN19RefreshManagerDummy14getNextCommandEv0
_ZN19RefreshManagerDummy5startEv0
_GLOBAL__sub_I__ZN19RefreshManagerDummy14getNextCommandEv30
+
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Generated by: LCOV version 1.13
+
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LCOV - code coverage report
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:2450.0 %
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_GLOBAL__sub_I__ZN19RefreshManagerDummy14getNextCommandEv30
_ZN19RefreshManagerDummy14getNextCommandEv0
_ZN19RefreshManagerDummy5startEv0
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/refresh - RefreshManagerDummy.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:1520.0 %
Date:2020-06-30 17:34:44Functions:2450.0 %
Legend: Lines: + hit + not hit +
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+
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h.func-sort-c.html b/html/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h.func-sort-c.html new file mode 100644 index 00000000..a81ee993 --- /dev/null +++ b/html/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h.func-sort-c.html @@ -0,0 +1,93 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/refresh - RefreshManagerDummy.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:020.0 %
Date:2020-06-30 17:34:44Functions:030.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_ZN19RefreshManagerDummy11updateStateE7CommandPN3tlm19tlm_generic_payloadE0
_ZN19RefreshManagerDummyD0Ev0
_ZN19RefreshManagerDummyD2Ev0
+
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+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h.func.html b/html/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h.func.html new file mode 100644 index 00000000..ecb0768f --- /dev/null +++ b/html/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h.func.html @@ -0,0 +1,93 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/refresh - RefreshManagerDummy.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:020.0 %
Date:2020-06-30 17:34:44Functions:030.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_ZN19RefreshManagerDummy11updateStateE7CommandPN3tlm19tlm_generic_payloadE0
_ZN19RefreshManagerDummyD0Ev0
_ZN19RefreshManagerDummyD2Ev0
+
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+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h.gcov.html b/html/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h.gcov.html new file mode 100644 index 00000000..ef9e8387 --- /dev/null +++ b/html/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h.gcov.html @@ -0,0 +1,134 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/refresh - RefreshManagerDummy.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:020.0 %
Date:2020-06-30 17:34:44Functions:030.0 %
Legend: Lines: + hit + not hit +
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+
          Line data    Source code
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.cpp.func-sort-c.html b/html/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.cpp.func-sort-c.html new file mode 100644 index 00000000..b35975e2 --- /dev/null +++ b/html/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.cpp.func-sort-c.html @@ -0,0 +1,101 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/refresh - RefreshManagerRankwise.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:66100.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
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_ZN22RefreshManagerRankwise14getNextCommandEv546133
_ZN22RefreshManagerRankwise5startEv1092466
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.cpp.func.html b/html/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.cpp.func.html new file mode 100644 index 00000000..d9fbc1ac --- /dev/null +++ b/html/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.cpp.func.html @@ -0,0 +1,101 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/refresh - RefreshManagerRankwise.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:798197.5 %
Date:2020-06-30 17:34:44Functions:66100.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
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_ZN22RefreshManagerRankwise11updateStateE7CommandPN3tlm19tlm_generic_payloadE227269
_ZN22RefreshManagerRankwise14getNextCommandEv546133
_ZN22RefreshManagerRankwise5startEv1092466
_ZN22RefreshManagerRankwiseC2ERSt6vectorIP11BankMachineSaIS2_EEP18PowerDownManagerIF4RankP9CheckerIF30
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.cpp.gcov.html b/html/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.cpp.gcov.html new file mode 100644 index 00000000..75be20c8 --- /dev/null +++ b/html/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.cpp.gcov.html @@ -0,0 +1,274 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:798197.5 %
Date:2020-06-30 17:34:44Functions:66100.0 %
Legend: Lines: + hit + not hit +
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          Line data    Source code
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:1250.0 %
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+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.h.func.html b/html/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.h.func.html new file mode 100644 index 00000000..2c30bcdc --- /dev/null +++ b/html/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.h.func.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/refresh - RefreshManagerRankwise.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:1250.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_ZN22RefreshManagerRankwiseD0Ev30
_ZN22RefreshManagerRankwiseD2Ev0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.h.gcov.html b/html/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.h.gcov.html new file mode 100644 index 00000000..49d05306 --- /dev/null +++ b/html/DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.h.gcov.html @@ -0,0 +1,129 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.h + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/refresh - RefreshManagerRankwise.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:1250.0 %
Legend: Lines: + hit + not hit +
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          Line data    Source code
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+
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+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/refresh/index-sort-f.html b/html/DRAMSys/library/src/controller/refresh/index-sort-f.html new file mode 100644 index 00000000..3e870329 --- /dev/null +++ b/html/DRAMSys/library/src/controller/refresh/index-sort-f.html @@ -0,0 +1,153 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/refresh + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - /DRAMSys/library/src/controller/refreshHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:172373.9 %
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
RefreshManagerDummy.h +
0.0%
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RefreshManagerRankwise.h +
100.0%
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20.0%20.0%
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RefreshManagerBankwise.h +
100.0%
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RefreshManagerRankwise.cpp +
97.5%97.5%
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RefreshManagerBankwise.cpp +
84.5%84.5%
+ 		84.5 %82 / 97100.0 %6 / 6
+
+
+ + + + +
Generated by: LCOV version 1.13
+
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Current view:top level - /DRAMSys/library/src/controller/refreshHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:172373.9 %
Legend: Rating: + low: < 75 % + medium: >= 75 % + high: >= 90 % +
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
RefreshManagerDummy.h +
0.0%
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20.0%20.0%
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RefreshManagerBankwise.cpp +
84.5%84.5%
+ 		84.5 %82 / 97100.0 %6 / 6
RefreshManagerRankwise.cpp +
97.5%97.5%
+ 		97.5 %79 / 81100.0 %6 / 6
RefreshManagerRankwise.h +
100.0%
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RefreshManagerBankwise.h +
100.0%
+ 		100.0 %1 / 1100.0 %2 / 2
+
+
+ + + + +
Generated by: LCOV version 1.13
+
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LCOV - code coverage report
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Current view:top level - /DRAMSys/library/src/controller/refreshHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:16418787.7 %
Date:2020-06-30 17:34:44Functions:172373.9 %
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
RefreshManagerBankwise.cpp +
84.5%84.5%
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100.0%
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20.0%20.0%
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0.0%
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RefreshManagerRankwise.cpp +
97.5%97.5%
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RefreshManagerRankwise.h +
100.0%
+ 		100.0 %1 / 150.0 %1 / 2
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/controller/respqueue/RespQueueFifo.cpp.func-sort-c.html b/html/DRAMSys/library/src/controller/respqueue/RespQueueFifo.cpp.func-sort-c.html new file mode 100644 index 00000000..b2415132 --- /dev/null +++ b/html/DRAMSys/library/src/controller/respqueue/RespQueueFifo.cpp.func-sort-c.html @@ -0,0 +1,101 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/respqueue/RespQueueFifo.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/respqueue - RespQueueFifo.cpp (source / functions)HitTotalCoverage
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Date:2020-06-30 17:34:44Functions:55100.0 %
Legend: Lines: + hit + not hit +
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_ZNK13RespQueueFifo14getTriggerTimeEv984087
+
+
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Generated by: LCOV version 1.13
+
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Current view:top level - DRAMSys/library/src/controller/respqueue - RespQueueFifo.cpp (source / functions)HitTotalCoverage
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Date:2020-06-30 17:34:44Functions:55100.0 %
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_ZNK13RespQueueFifo14getTriggerTimeEv984087
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:55100.0 %
Legend: Lines: + hit + not hit +
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100.0%
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100.0%
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100.0%
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Generated by: LCOV version 1.13
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
SchedulerFifo.cpp +
100.0%
+ 		100.0 %27 / 27100.0 %9 / 9
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100.0%
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SchedulerFrFcfs.cpp +
89.5%89.5%
+ 		89.5 %34 / 3888.9 %8 / 9
SchedulerFrFcfs.h +
100.0%
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SchedulerFrFcfsGrp.cpp +
78.7%78.7%
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SchedulerFrFcfsGrp.h +
100.0%
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+
+
+ + + + +
Generated by: LCOV version 1.13
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LCOV - code coverage report
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/error/ECC - Bit.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:1520.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:00-
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Date:2020-06-30 17:34:44Functions:00-
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:080.0 %
Date:2020-06-30 17:34:44Functions:00-
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Generated by: LCOV version 1.13
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:080.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:2450.0 %
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/error - eccbaseclass.h (source / functions)HitTotalCoverage
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:070.0 %
Date:2020-06-30 17:34:44Functions:030.0 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Date:2020-06-30 17:34:44Functions:030.0 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Date:2020-06-30 17:34:44Functions:030.0 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Date:2020-06-30 17:34:44Functions:2540.0 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/error - ecchamming.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:2540.0 %
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:2540.0 %
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/error - ecchamming.h (source / functions)HitTotalCoverage
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Date:2020-06-30 17:34:44Functions:030.0 %
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_ZN10ECCHammingD0Ev0
_ZN10ECCHammingD2Ev0
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Date:2020-06-30 17:34:44Functions:030.0 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/error - ecchamming.h (source / functions)HitTotalCoverage
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Date:2020-06-30 17:34:44Functions:030.0 %
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:13090.3 %
Date:2020-06-30 17:34:44Functions:21910.5 %
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Date:2020-06-30 17:34:44Functions:00-
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:00-
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Date:2020-06-30 17:34:44Functions:00-
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LCOV - code coverage report
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:113234.4 %
Date:2020-06-30 17:34:44Functions:3475.0 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation - TemperatureController.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:113234.4 %
Date:2020-06-30 17:34:44Functions:3475.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:113234.4 %
Date:2020-06-30 17:34:44Functions:3475.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - Dram.cpp (source / functions)HitTotalCoverage
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Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
+
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LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - Dram.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
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+
+
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Generated by: LCOV version 1.13
+
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - Dram.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:197425.7 %
Date:2020-06-30 17:34:44Functions:5862.5 %
Legend: Lines: + hit + not hit +
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LCOV - code coverage report
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:22100.0 %
Date:2020-06-30 17:34:44Functions:00-
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Generated by: LCOV version 1.13
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:22100.0 %
Date:2020-06-30 17:34:44Functions:00-
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LCOV - code coverage report
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:22100.0 %
Date:2020-06-30 17:34:44Functions:00-
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramDDR3.cpp (source / functions)HitTotalCoverage
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Date:2020-06-30 17:34:44Functions:33100.0 %
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/simulation/dram - DramDDR3.cpp (source / functions)HitTotalCoverage
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Date:2020-06-30 17:34:44Functions:33100.0 %
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_Z41__static_initialization_and_destruction_0ii30
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramDDR3.cpp (source / functions)HitTotalCoverage
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Date:2020-06-30 17:34:44Functions:33100.0 %
Legend: Lines: + hit + not hit +
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+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramDDR3.h.func-sort-c.html b/html/DRAMSys/library/src/simulation/dram/DramDDR3.h.func-sort-c.html new file mode 100644 index 00000000..381353ec --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramDDR3.h.func-sort-c.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramDDR3.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramDDR3.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:020.0 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramDDR3.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramDDR3.h.gcov.html b/html/DRAMSys/library/src/simulation/dram/DramDDR3.h.gcov.html new file mode 100644 index 00000000..0d1cb033 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramDDR3.h.gcov.html @@ -0,0 +1,132 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramDDR3.h + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - DramDDR3.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramDDR4.cpp.func-sort-c.html b/html/DRAMSys/library/src/simulation/dram/DramDDR4.cpp.func-sort-c.html new file mode 100644 index 00000000..15cee2e9 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramDDR4.cpp.func-sort-c.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramDDR4.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramDDR4.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:33100.0 %
Legend: Lines: + hit + not hit +
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Date:2020-06-30 17:34:44Functions:33100.0 %
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Date:2020-06-30 17:34:44Functions:33100.0 %
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Date:2020-06-30 17:34:44Functions:020.0 %
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+
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/simulation/dram - DramDDR4.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
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_ZN8DramDDR4D0Ev0
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+
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/simulation/dram - DramDDR4.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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+
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp.func-sort-c.html b/html/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp.func-sort-c.html new file mode 100644 index 00000000..bf10502d --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp.func-sort-c.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramGDDR5.cpp - functions + + + + + + + + + + + + + + +
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Current view:top level - DRAMSys/library/src/simulation/dram - DramGDDR5.cpp (source / functions)HitTotalCoverage
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Date:2020-06-30 17:34:44Functions:2366.7 %
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_GLOBAL__sub_I__ZN9DramGDDR5C2EN7sc_core14sc_module_nameE30
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Generated by: LCOV version 1.13
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramGDDR5.h.func-sort-c.html b/html/DRAMSys/library/src/simulation/dram/DramGDDR5.h.func-sort-c.html new file mode 100644 index 00000000..5a2d6d38 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramGDDR5.h.func-sort-c.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramGDDR5.h - functions + + + + + + + + + + + + + + +
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Current view:top level - DRAMSys/library/src/simulation/dram - DramGDDR5.h (source / functions)HitTotalCoverage
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Date:2020-06-30 17:34:44Functions:020.0 %
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/simulation/dram - DramGDDR5.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/simulation/dram - DramGDDR5.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:020.0 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramGDDR5X.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:2366.7 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramGDDR5X.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:1616.7 %
Date:2020-06-30 17:34:44Functions:2366.7 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
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_ZN10DramGDDR5XC2EN7sc_core14sc_module_nameE0
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp.gcov.html b/html/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp.gcov.html new file mode 100644 index 00000000..b7b9b970 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp.gcov.html @@ -0,0 +1,135 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramGDDR5X.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:1616.7 %
Date:2020-06-30 17:34:44Functions:2366.7 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramGDDR5X.h.func-sort-c.html b/html/DRAMSys/library/src/simulation/dram/DramGDDR5X.h.func-sort-c.html new file mode 100644 index 00000000..81e9eba0 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramGDDR5X.h.func-sort-c.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramGDDR5X.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramGDDR5X.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramGDDR5X.h.func.html b/html/DRAMSys/library/src/simulation/dram/DramGDDR5X.h.func.html new file mode 100644 index 00000000..53b2125c --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramGDDR5X.h.func.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramGDDR5X.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramGDDR5X.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_ZN10DramGDDR5XD0Ev0
_ZN10DramGDDR5XD2Ev0
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramGDDR5X.h.gcov.html b/html/DRAMSys/library/src/simulation/dram/DramGDDR5X.h.gcov.html new file mode 100644 index 00000000..8ef7b3f9 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramGDDR5X.h.gcov.html @@ -0,0 +1,132 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramGDDR5X.h + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramGDDR5X.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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+
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+
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp.func-sort-c.html b/html/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp.func-sort-c.html new file mode 100644 index 00000000..060b21fa --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp.func-sort-c.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramGDDR6.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramGDDR6.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:2366.7 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_ZN9DramGDDR6C2EN7sc_core14sc_module_nameE0
_GLOBAL__sub_I__ZN9DramGDDR6C2EN7sc_core14sc_module_nameE30
+
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp.func.html b/html/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp.func.html new file mode 100644 index 00000000..045bd470 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp.func.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramGDDR6.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramGDDR6.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:2366.7 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN9DramGDDR6C2EN7sc_core14sc_module_nameE30
_ZN9DramGDDR6C2EN7sc_core14sc_module_nameE0
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp.gcov.html b/html/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp.gcov.html new file mode 100644 index 00000000..81473d06 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp.gcov.html @@ -0,0 +1,135 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramGDDR6.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramGDDR6.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:2366.7 %
Legend: Lines: + hit + not hit +
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+
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramGDDR6.h.func-sort-c.html b/html/DRAMSys/library/src/simulation/dram/DramGDDR6.h.func-sort-c.html new file mode 100644 index 00000000..0a74b761 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramGDDR6.h.func-sort-c.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramGDDR6.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramGDDR6.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
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+
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramGDDR6.h.func.html b/html/DRAMSys/library/src/simulation/dram/DramGDDR6.h.func.html new file mode 100644 index 00000000..c76ad537 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramGDDR6.h.func.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramGDDR6.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramGDDR6.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/simulation/dram - DramGDDR6.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramHBM2.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:33100.0 %
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/simulation/dram - DramHBM2.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:4666.7 %
Date:2020-06-30 17:34:44Functions:33100.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/simulation/dram - DramHBM2.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:33100.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramHBM2.h.func-sort-c.html b/html/DRAMSys/library/src/simulation/dram/DramHBM2.h.func-sort-c.html new file mode 100644 index 00000000..c21a8b9c --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramHBM2.h.func-sort-c.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramHBM2.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramHBM2.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:020.0 %
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramHBM2.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramHBM2.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp.func-sort-c.html b/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp.func-sort-c.html new file mode 100644 index 00000000..08117f53 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp.func-sort-c.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramLPDDR4.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:33100.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramLPDDR4.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:33100.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
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_ZN10DramLPDDR4C2EN7sc_core14sc_module_nameE12
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Generated by: LCOV version 1.13
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+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp.gcov.html b/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp.gcov.html new file mode 100644 index 00000000..85777181 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp.gcov.html @@ -0,0 +1,135 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramLPDDR4.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:33100.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramLPDDR4.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:020.0 %
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.h.func.html b/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.h.func.html new file mode 100644 index 00000000..ad07bbbd --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.h.func.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramLPDDR4.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - DramLPDDR4.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_ZN10DramLPDDR4D0Ev0
_ZN10DramLPDDR4D2Ev0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.h.gcov.html b/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.h.gcov.html new file mode 100644 index 00000000..50773866 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramLPDDR4.h.gcov.html @@ -0,0 +1,132 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramLPDDR4.h + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - DramLPDDR4.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
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+      47          12 : /* EOF */
+
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramRecordable.cpp.func-sort-c.html b/html/DRAMSys/library/src/simulation/dram/DramRecordable.cpp.func-sort-c.html new file mode 100644 index 00000000..a23591b0 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramRecordable.cpp.func-sort-c.html @@ -0,0 +1,269 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramRecordable.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - DramRecordable.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:233860.5 %
Date:2020-06-30 17:34:44Functions:144729.8 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_ZN14DramRecordableI10DramGDDR5XE11powerWindowEv0
_ZN14DramRecordableI10DramGDDR5XE11recordPhaseERN3tlm19tlm_generic_payloadENS2_9tlm_phaseEN7sc_core7sc_timeE0
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_ZN14DramRecordableI9DramGDDR5EC2EN7sc_core14sc_module_nameEP11TlmRecorder0
_ZN14DramRecordableI9DramGDDR6E11powerWindowEv0
_ZN14DramRecordableI9DramGDDR6E11recordPhaseERN3tlm19tlm_generic_payloadENS2_9tlm_phaseEN7sc_core7sc_timeE0
_ZN14DramRecordableI9DramGDDR6E11reportPowerEv0
_ZN14DramRecordableI9DramGDDR6E15nb_transport_fwERN3tlm19tlm_generic_payloadERNS2_9tlm_phaseERN7sc_core7sc_timeE0
_ZN14DramRecordableI9DramGDDR6EC2EN7sc_core14sc_module_nameEP11TlmRecorder0
_ZN14DramRecordableI8DramDDR3EC2EN7sc_core14sc_module_nameEP11TlmRecorder5
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_ZN14DramRecordableI8DramHBM2EC2EN7sc_core14sc_module_nameEP11TlmRecorder14
_GLOBAL__sub_I_DramRecordable.cpp30
_Z41__static_initialization_and_destruction_0ii30
_ZN14DramRecordableI8DramDDR3E11recordPhaseERN3tlm19tlm_generic_payloadENS2_9tlm_phaseEN7sc_core7sc_timeE2275
_ZN14DramRecordableI8DramDDR3E15nb_transport_fwERN3tlm19tlm_generic_payloadERNS2_9tlm_phaseERN7sc_core7sc_timeE2275
_ZN14DramRecordableI8DramHBM2E11recordPhaseERN3tlm19tlm_generic_payloadENS2_9tlm_phaseEN7sc_core7sc_timeE58380
_ZN14DramRecordableI8DramHBM2E15nb_transport_fwERN3tlm19tlm_generic_payloadERNS2_9tlm_phaseERN7sc_core7sc_timeE58380
_ZN14DramRecordableI8DramDDR4E11recordPhaseERN3tlm19tlm_generic_payloadENS2_9tlm_phaseEN7sc_core7sc_timeE166614
_ZN14DramRecordableI8DramDDR4E15nb_transport_fwERN3tlm19tlm_generic_payloadERNS2_9tlm_phaseERN7sc_core7sc_timeE166614
_ZN14DramRecordableI10DramLPDDR4E11recordPhaseERN3tlm19tlm_generic_payloadENS2_9tlm_phaseEN7sc_core7sc_timeE191436
_ZN14DramRecordableI10DramLPDDR4E15nb_transport_fwERN3tlm19tlm_generic_payloadERNS2_9tlm_phaseERN7sc_core7sc_timeE191436
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramRecordable.cpp.func.html b/html/DRAMSys/library/src/simulation/dram/DramRecordable.cpp.func.html new file mode 100644 index 00000000..07eba4a0 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramRecordable.cpp.func.html @@ -0,0 +1,269 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramRecordable.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - DramRecordable.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:233860.5 %
Date:2020-06-30 17:34:44Functions:144729.8 %
Legend: Lines: + hit + not hit +
+
+ +
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Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I_DramRecordable.cpp30
_Z41__static_initialization_and_destruction_0ii30
_ZN14DramRecordableI10DramGDDR5XE11powerWindowEv0
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_ZN14DramRecordableI10DramGDDR5XE15nb_transport_fwERN3tlm19tlm_generic_payloadERNS2_9tlm_phaseERN7sc_core7sc_timeE0
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_ZN14DramRecordableI10DramLPDDR4E11recordPhaseERN3tlm19tlm_generic_payloadENS2_9tlm_phaseEN7sc_core7sc_timeE191436
_ZN14DramRecordableI10DramLPDDR4E11reportPowerEv0
_ZN14DramRecordableI10DramLPDDR4E15nb_transport_fwERN3tlm19tlm_generic_payloadERNS2_9tlm_phaseERN7sc_core7sc_timeE191436
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_ZN14DramRecordableI8DramDDR4E11powerWindowEv0
_ZN14DramRecordableI8DramDDR4E11recordPhaseERN3tlm19tlm_generic_payloadENS2_9tlm_phaseEN7sc_core7sc_timeE166614
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_ZN14DramRecordableI8DramDDR4E15nb_transport_fwERN3tlm19tlm_generic_payloadERNS2_9tlm_phaseERN7sc_core7sc_timeE166614
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_ZN14DramRecordableI8DramHBM2E11powerWindowEv0
_ZN14DramRecordableI8DramHBM2E11recordPhaseERN3tlm19tlm_generic_payloadENS2_9tlm_phaseEN7sc_core7sc_timeE58380
_ZN14DramRecordableI8DramHBM2E11reportPowerEv0
_ZN14DramRecordableI8DramHBM2E15nb_transport_fwERN3tlm19tlm_generic_payloadERNS2_9tlm_phaseERN7sc_core7sc_timeE58380
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_ZN14DramRecordableI9DramGDDR5E11powerWindowEv0
_ZN14DramRecordableI9DramGDDR5E11recordPhaseERN3tlm19tlm_generic_payloadENS2_9tlm_phaseEN7sc_core7sc_timeE0
_ZN14DramRecordableI9DramGDDR5E11reportPowerEv0
_ZN14DramRecordableI9DramGDDR5E15nb_transport_fwERN3tlm19tlm_generic_payloadERNS2_9tlm_phaseERN7sc_core7sc_timeE0
_ZN14DramRecordableI9DramGDDR5EC2EN7sc_core14sc_module_nameEP11TlmRecorder0
_ZN14DramRecordableI9DramGDDR6E11powerWindowEv0
_ZN14DramRecordableI9DramGDDR6E11recordPhaseERN3tlm19tlm_generic_payloadENS2_9tlm_phaseEN7sc_core7sc_timeE0
_ZN14DramRecordableI9DramGDDR6E11reportPowerEv0
_ZN14DramRecordableI9DramGDDR6E15nb_transport_fwERN3tlm19tlm_generic_payloadERNS2_9tlm_phaseERN7sc_core7sc_timeE0
_ZN14DramRecordableI9DramGDDR6EC2EN7sc_core14sc_module_nameEP11TlmRecorder0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramRecordable.cpp.gcov.html b/html/DRAMSys/library/src/simulation/dram/DramRecordable.cpp.gcov.html new file mode 100644 index 00000000..09eab6e2 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramRecordable.cpp.gcov.html @@ -0,0 +1,241 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramRecordable.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - DramRecordable.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:233860.5 %
Date:2020-06-30 17:34:44Functions:144729.8 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
+
+       1             : /* EOF */
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+
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramRecordable.h.func-sort-c.html b/html/DRAMSys/library/src/simulation/dram/DramRecordable.h.func-sort-c.html new file mode 100644 index 00000000..e8fbee4f --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramRecordable.h.func-sort-c.html @@ -0,0 +1,189 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramRecordable.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramRecordable.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:3560.0 %
Date:2020-06-30 17:34:44Functions:42714.8 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramRecordable.h.func.html b/html/DRAMSys/library/src/simulation/dram/DramRecordable.h.func.html new file mode 100644 index 00000000..5e486f62 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramRecordable.h.func.html @@ -0,0 +1,189 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramRecordable.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramRecordable.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:3560.0 %
Date:2020-06-30 17:34:44Functions:42714.8 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
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_ZN14DramRecordableI9DramGDDR6ED2Ev0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramRecordable.h.gcov.html b/html/DRAMSys/library/src/simulation/dram/DramRecordable.h.gcov.html new file mode 100644 index 00000000..6e959c25 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramRecordable.h.gcov.html @@ -0,0 +1,155 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramRecordable.h + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramRecordable.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:3560.0 %
Date:2020-06-30 17:34:44Functions:42714.8 %
Legend: Lines: + hit + not hit +
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+
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+
+
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramWideIO.cpp.func-sort-c.html b/html/DRAMSys/library/src/simulation/dram/DramWideIO.cpp.func-sort-c.html new file mode 100644 index 00000000..ab47771e --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramWideIO.cpp.func-sort-c.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramWideIO.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - DramWideIO.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11190.8 %
Date:2020-06-30 17:34:44Functions:2633.3 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
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+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramWideIO.cpp.func.html b/html/DRAMSys/library/src/simulation/dram/DramWideIO.cpp.func.html new file mode 100644 index 00000000..839e14aa --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramWideIO.cpp.func.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramWideIO.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - DramWideIO.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11190.8 %
Date:2020-06-30 17:34:44Functions:2633.3 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
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_Z41__static_initialization_and_destruction_0ii30
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+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramWideIO.cpp.gcov.html b/html/DRAMSys/library/src/simulation/dram/DramWideIO.cpp.gcov.html new file mode 100644 index 00000000..0a4b3a53 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramWideIO.cpp.gcov.html @@ -0,0 +1,304 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramWideIO.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/simulation/dram - DramWideIO.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11190.8 %
Date:2020-06-30 17:34:44Functions:2633.3 %
Legend: Lines: + hit + not hit +
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+ + + + + + + + +

+
          Line data    Source code
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp.func-sort-c.html b/html/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp.func-sort-c.html new file mode 100644 index 00000000..a26a0761 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp.func-sort-c.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation/dram/DramWideIO2.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/library/src/simulation/dram - DramWideIO2.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:2366.7 %
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Current view:top level - DRAMSys/library/src/simulation/dram - DramWideIO2.cpp (source / functions)HitTotalCoverage
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:1616.7 %
Date:2020-06-30 17:34:44Functions:2366.7 %
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Function Name Sort by function nameHit count Sort by hit count
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:2366.7 %
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/simulation/dram - DramWideIO2.h (source / functions)HitTotalCoverage
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Date:2020-06-30 17:34:44Functions:020.0 %
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Generated by: LCOV version 1.13
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Current view:top level - DRAMSys/library/src/simulation/dram - DramWideIO2.h (source / functions)HitTotalCoverage
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Date:2020-06-30 17:34:44Functions:020.0 %
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Generated by: LCOV version 1.13
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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Generated by: LCOV version 1.13
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Current view:top level - /DRAMSys/library/src/simulation/dramHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:7244816.1 %
Date:2020-06-30 17:34:44Functions:4512835.2 %
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
DramWideIO2.h +
0.0%
+ 		0.0 %0 / 10.0 %0 / 2
DramDDR4.h +
100.0%
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DramHBM2.h +
100.0%
+ 		100.0 %1 / 10.0 %0 / 2
DramLPDDR4.h +
100.0%
+ 		100.0 %1 / 10.0 %0 / 2
DramGDDR6.h +
0.0%
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DramDDR3.h +
100.0%
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DramGDDR5.h +
0.0%
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DramGDDR5X.h +
0.0%
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DramRecordable.h +
60.0%60.0%
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DramRecordable.cpp +
60.5%60.5%
+ 		60.5 %23 / 3829.8 %14 / 47
DramWideIO.cpp +
0.8%0.8%
+ 		0.8 %1 / 11933.3 %2 / 6
Dram.cpp +
25.7%25.7%
+ 		25.7 %19 / 7462.5 %5 / 8
DramGDDR5X.cpp +
16.7%16.7%
+ 		16.7 %1 / 666.7 %2 / 3
DramGDDR5.cpp +
16.7%16.7%
+ 		16.7 %1 / 666.7 %2 / 3
DramGDDR6.cpp +
16.7%16.7%
+ 		16.7 %1 / 666.7 %2 / 3
DramWideIO2.cpp +
16.7%16.7%
+ 		16.7 %1 / 666.7 %2 / 3
Dram.h +
100.0%
+ 		100.0 %2 / 2-0 / 0
DramDDR3.cpp +
4.8%4.8%
+ 		4.8 %4 / 83100.0 %3 / 3
DramDDR4.cpp +
4.8%4.8%
+ 		4.8 %4 / 83100.0 %3 / 3
DramHBM2.cpp +
66.7%66.7%
+ 		66.7 %4 / 6100.0 %3 / 3
DramLPDDR4.cpp +
66.7%66.7%
+ 		66.7 %4 / 6100.0 %3 / 3
+
+
+ + + + +
Generated by: LCOV version 1.13
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LCOV - code coverage report
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:7244816.1 %
Date:2020-06-30 17:34:44Functions:4512835.2 %
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
DramWideIO2.h +
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0.0%
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0.0%
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DramGDDR5X.h +
0.0%
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DramWideIO.cpp +
0.8%0.8%
+ 		0.8 %1 / 11933.3 %2 / 6
DramDDR3.cpp +
4.8%4.8%
+ 		4.8 %4 / 83100.0 %3 / 3
DramDDR4.cpp +
4.8%4.8%
+ 		4.8 %4 / 83100.0 %3 / 3
DramGDDR5X.cpp +
16.7%16.7%
+ 		16.7 %1 / 666.7 %2 / 3
DramGDDR5.cpp +
16.7%16.7%
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DramGDDR6.cpp +
16.7%16.7%
+ 		16.7 %1 / 666.7 %2 / 3
DramWideIO2.cpp +
16.7%16.7%
+ 		16.7 %1 / 666.7 %2 / 3
Dram.cpp +
25.7%25.7%
+ 		25.7 %19 / 7462.5 %5 / 8
DramRecordable.h +
60.0%60.0%
+ 		60.0 %3 / 514.8 %4 / 27
DramRecordable.cpp +
60.5%60.5%
+ 		60.5 %23 / 3829.8 %14 / 47
DramHBM2.cpp +
66.7%66.7%
+ 		66.7 %4 / 6100.0 %3 / 3
DramLPDDR4.cpp +
66.7%66.7%
+ 		66.7 %4 / 6100.0 %3 / 3
DramDDR4.h +
100.0%
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DramHBM2.h +
100.0%
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DramLPDDR4.h +
100.0%
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DramDDR3.h +
100.0%
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Dram.h +
100.0%
+ 		100.0 %2 / 2-0 / 0
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+
+ + + + +
Generated by: LCOV version 1.13
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LCOV - code coverage report
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:7244816.1 %
Date:2020-06-30 17:34:44Functions:4512835.2 %
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
Dram.cpp +
25.7%25.7%
+ 		25.7 %19 / 7462.5 %5 / 8
Dram.h +
100.0%
+ 		100.0 %2 / 2-0 / 0
DramDDR3.cpp +
4.8%4.8%
+ 		4.8 %4 / 83100.0 %3 / 3
DramDDR3.h +
100.0%
+ 		100.0 %1 / 10.0 %0 / 2
DramDDR4.cpp +
4.8%4.8%
+ 		4.8 %4 / 83100.0 %3 / 3
DramDDR4.h +
100.0%
+ 		100.0 %1 / 10.0 %0 / 2
DramGDDR5.cpp +
16.7%16.7%
+ 		16.7 %1 / 666.7 %2 / 3
DramGDDR5.h +
0.0%
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DramGDDR5X.cpp +
16.7%16.7%
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DramGDDR5X.h +
0.0%
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DramGDDR6.cpp +
16.7%16.7%
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DramGDDR6.h +
0.0%
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DramHBM2.cpp +
66.7%66.7%
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DramHBM2.h +
100.0%
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DramLPDDR4.cpp +
66.7%66.7%
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DramLPDDR4.h +
100.0%
+ 		100.0 %1 / 10.0 %0 / 2
DramRecordable.cpp +
60.5%60.5%
+ 		60.5 %23 / 3829.8 %14 / 47
DramRecordable.h +
60.0%60.0%
+ 		60.0 %3 / 514.8 %4 / 27
DramWideIO.cpp +
0.8%0.8%
+ 		0.8 %1 / 11933.3 %2 / 6
DramWideIO2.cpp +
16.7%16.7%
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DramWideIO2.h +
0.0%
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+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/index-sort-f.html b/html/DRAMSys/library/src/simulation/index-sort-f.html new file mode 100644 index 00000000..0fdafaea --- /dev/null +++ b/html/DRAMSys/library/src/simulation/index-sort-f.html @@ -0,0 +1,153 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - /DRAMSys/library/src/simulationHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:20737555.2 %
Date:2020-06-30 17:34:44Functions:304369.8 %
Legend: Rating: + low: < 75 % + medium: >= 75 % + high: >= 90 % +
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+ +
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
TemperatureController.cpp +
2.3%2.3%
+ 		2.3 %1 / 4425.0 %2 / 8
DRAMSys.cpp +
40.2%40.2%
+ 		40.2 %47 / 11758.3 %7 / 12
TemperatureController.h +
34.4%34.4%
+ 		34.4 %11 / 3275.0 %3 / 4
Arbiter.cpp +
89.0%89.0%
+ 		89.0 %81 / 9187.5 %7 / 8
Arbiter.h +
100.0%
+ 		100.0 %1 / 1100.0 %2 / 2
DRAMSysRecordable.cpp +
73.3%73.3%
+ 		73.3 %66 / 90100.0 %9 / 9
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/index-sort-l.html b/html/DRAMSys/library/src/simulation/index-sort-l.html new file mode 100644 index 00000000..6ca1a79a --- /dev/null +++ b/html/DRAMSys/library/src/simulation/index-sort-l.html @@ -0,0 +1,153 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - /DRAMSys/library/src/simulationHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:20737555.2 %
Date:2020-06-30 17:34:44Functions:304369.8 %
Legend: Rating: + low: < 75 % + medium: >= 75 % + high: >= 90 % +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
TemperatureController.cpp +
2.3%2.3%
+ 		2.3 %1 / 4425.0 %2 / 8
TemperatureController.h +
34.4%34.4%
+ 		34.4 %11 / 3275.0 %3 / 4
DRAMSys.cpp +
40.2%40.2%
+ 		40.2 %47 / 11758.3 %7 / 12
DRAMSysRecordable.cpp +
73.3%73.3%
+ 		73.3 %66 / 90100.0 %9 / 9
Arbiter.cpp +
89.0%89.0%
+ 		89.0 %81 / 9187.5 %7 / 8
Arbiter.h +
100.0%
+ 		100.0 %1 / 1100.0 %2 / 2
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/library/src/simulation/index.html b/html/DRAMSys/library/src/simulation/index.html new file mode 100644 index 00000000..e66e6881 --- /dev/null +++ b/html/DRAMSys/library/src/simulation/index.html @@ -0,0 +1,153 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/simulation + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - /DRAMSys/library/src/simulationHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:20737555.2 %
Date:2020-06-30 17:34:44Functions:304369.8 %
Legend: Rating: + low: < 75 % + medium: >= 75 % + high: >= 90 % +
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+ +
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Filename Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
Arbiter.cpp +
89.0%89.0%
+ 		89.0 %81 / 9187.5 %7 / 8
Arbiter.h +
100.0%
+ 		100.0 %1 / 1100.0 %2 / 2
DRAMSys.cpp +
40.2%40.2%
+ 		40.2 %47 / 11758.3 %7 / 12
DRAMSysRecordable.cpp +
73.3%73.3%
+ 		73.3 %66 / 90100.0 %9 / 9
TemperatureController.cpp +
2.3%2.3%
+ 		2.3 %1 / 4425.0 %2 / 8
TemperatureController.h +
34.4%34.4%
+ 		34.4 %11 / 3275.0 %3 / 4
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/MemoryManager.cpp.func-sort-c.html b/html/DRAMSys/simulator/MemoryManager.cpp.func-sort-c.html new file mode 100644 index 00000000..2b15610b --- /dev/null +++ b/html/DRAMSys/simulator/MemoryManager.cpp.func-sort-c.html @@ -0,0 +1,109 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/MemoryManager.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/simulator - MemoryManager.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:182475.0 %
Date:2020-06-30 17:34:44Functions:5771.4 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
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_ZN13MemoryManagerD2Ev0
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_Z41__static_initialization_and_destruction_0ii30
_ZN13MemoryManagerC2Ev37
_ZN13MemoryManager4freeEPN3tlm19tlm_generic_payloadE252908
_ZN13MemoryManager8allocateEv252938
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/MemoryManager.cpp.func.html b/html/DRAMSys/simulator/MemoryManager.cpp.func.html new file mode 100644 index 00000000..e2f47a87 --- /dev/null +++ b/html/DRAMSys/simulator/MemoryManager.cpp.func.html @@ -0,0 +1,109 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/MemoryManager.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/simulator - MemoryManager.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:182475.0 %
Date:2020-06-30 17:34:44Functions:5771.4 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN13MemoryManagerC2Ev30
_Z41__static_initialization_and_destruction_0ii30
_ZN13MemoryManager4freeEPN3tlm19tlm_generic_payloadE252908
_ZN13MemoryManager8allocateEv252938
_ZN13MemoryManagerC2Ev37
_ZN13MemoryManagerD0Ev0
_ZN13MemoryManagerD2Ev0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/MemoryManager.cpp.gcov.html b/html/DRAMSys/simulator/MemoryManager.cpp.gcov.html new file mode 100644 index 00000000..fffe284f --- /dev/null +++ b/html/DRAMSys/simulator/MemoryManager.cpp.gcov.html @@ -0,0 +1,169 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/MemoryManager.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/simulator - MemoryManager.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:182475.0 %
Date:2020-06-30 17:34:44Functions:5771.4 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
+
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+
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/StlPlayer.h.func-sort-c.html b/html/DRAMSys/simulator/StlPlayer.h.func-sort-c.html new file mode 100644 index 00000000..efbec1ae --- /dev/null +++ b/html/DRAMSys/simulator/StlPlayer.h.func-sort-c.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/StlPlayer.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/simulator - StlPlayer.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:486277.4 %
Date:2020-06-30 17:34:44Functions:2825.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN9StlPlayerILb0EED0Ev0
_ZN9StlPlayerILb0EED2Ev0
_ZN9StlPlayerILb1EED0Ev0
_ZN9StlPlayerILb1EED2Ev0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/StlPlayer.h.func.html b/html/DRAMSys/simulator/StlPlayer.h.func.html new file mode 100644 index 00000000..c8a95420 --- /dev/null +++ b/html/DRAMSys/simulator/StlPlayer.h.func.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/StlPlayer.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/simulator - StlPlayer.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:486277.4 %
Date:2020-06-30 17:34:44Functions:2825.0 %
Legend: Lines: + hit + not hit +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + +

Function Name Sort by function nameHit count Sort by hit count
_ZN9StlPlayerILb0EED0Ev0
_ZN9StlPlayerILb0EED2Ev0
_ZN9StlPlayerILb1EED0Ev0
_ZN9StlPlayerILb1EED2Ev0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/StlPlayer.h.gcov.html b/html/DRAMSys/simulator/StlPlayer.h.gcov.html new file mode 100644 index 00000000..945ea4ec --- /dev/null +++ b/html/DRAMSys/simulator/StlPlayer.h.gcov.html @@ -0,0 +1,259 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/StlPlayer.h + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/simulator - StlPlayer.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:486277.4 %
Date:2020-06-30 17:34:44Functions:2825.0 %
Legend: Lines: + hit + not hit +
+
+ + + + + + + + +

+
          Line data    Source code
+
+       1             : /* EOF */
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/TracePlayer.cpp.func-sort-c.html b/html/DRAMSys/simulator/TracePlayer.cpp.func-sort-c.html new file mode 100644 index 00000000..ac38a8c5 --- /dev/null +++ b/html/DRAMSys/simulator/TracePlayer.cpp.func-sort-c.html @@ -0,0 +1,125 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/TracePlayer.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/simulator - TracePlayer.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Date:2020-06-30 17:34:44Functions:101190.9 %
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Function Name Sort by function nameHit count Sort by hit count
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+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/TracePlayer.cpp.func.html b/html/DRAMSys/simulator/TracePlayer.cpp.func.html new file mode 100644 index 00000000..c4e8801f --- /dev/null +++ b/html/DRAMSys/simulator/TracePlayer.cpp.func.html @@ -0,0 +1,125 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/TracePlayer.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/simulator - TracePlayer.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:475388.7 %
Date:2020-06-30 17:34:44Functions:101190.9 %
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Function Name Sort by function nameHit count Sort by hit count
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_Z41__static_initialization_and_destruction_0ii30
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+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/TracePlayer.cpp.gcov.html b/html/DRAMSys/simulator/TracePlayer.cpp.gcov.html new file mode 100644 index 00000000..915a4953 --- /dev/null +++ b/html/DRAMSys/simulator/TracePlayer.cpp.gcov.html @@ -0,0 +1,217 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/TracePlayer.cpp + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/simulator - TracePlayer.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:475388.7 %
Date:2020-06-30 17:34:44Functions:101190.9 %
Legend: Lines: + hit + not hit +
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+
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/TracePlayer.h.func-sort-c.html b/html/DRAMSys/simulator/TracePlayer.h.func-sort-c.html new file mode 100644 index 00000000..c10aea59 --- /dev/null +++ b/html/DRAMSys/simulator/TracePlayer.h.func-sort-c.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/TracePlayer.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/simulator - TracePlayer.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_ZN11TracePlayerD0Ev0
_ZN11TracePlayerD2Ev0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/TracePlayer.h.func.html b/html/DRAMSys/simulator/TracePlayer.h.func.html new file mode 100644 index 00000000..77f8ef2e --- /dev/null +++ b/html/DRAMSys/simulator/TracePlayer.h.func.html @@ -0,0 +1,89 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/TracePlayer.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/simulator - TracePlayer.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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Function Name Sort by function nameHit count Sort by hit count
_ZN11TracePlayerD0Ev0
_ZN11TracePlayerD2Ev0
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/TracePlayer.h.gcov.html b/html/DRAMSys/simulator/TracePlayer.h.gcov.html new file mode 100644 index 00000000..4d90f103 --- /dev/null +++ b/html/DRAMSys/simulator/TracePlayer.h.gcov.html @@ -0,0 +1,139 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/TracePlayer.h + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/simulator - TracePlayer.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:020.0 %
Legend: Lines: + hit + not hit +
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+
          Line data    Source code
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+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/TracePlayerListener.h.func-sort-c.html b/html/DRAMSys/simulator/TracePlayerListener.h.func-sort-c.html new file mode 100644 index 00000000..c5bfab09 --- /dev/null +++ b/html/DRAMSys/simulator/TracePlayerListener.h.func-sort-c.html @@ -0,0 +1,81 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/TracePlayerListener.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/simulator - TracePlayerListener.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:00-
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Function Name Sort by function nameHit count Sort by hit count
+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/TracePlayerListener.h.func.html b/html/DRAMSys/simulator/TracePlayerListener.h.func.html new file mode 100644 index 00000000..25396818 --- /dev/null +++ b/html/DRAMSys/simulator/TracePlayerListener.h.func.html @@ -0,0 +1,81 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/TracePlayerListener.h - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/simulator - TracePlayerListener.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:00-
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Function Name Sort by function nameHit count Sort by hit count
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/TracePlayerListener.h.gcov.html b/html/DRAMSys/simulator/TracePlayerListener.h.gcov.html new file mode 100644 index 00000000..6ca827c0 --- /dev/null +++ b/html/DRAMSys/simulator/TracePlayerListener.h.gcov.html @@ -0,0 +1,131 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/TracePlayerListener.h + + + + + + + + + + + + + + +
LCOV - code coverage report
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Current view:top level - DRAMSys/simulator - TracePlayerListener.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:010.0 %
Date:2020-06-30 17:34:44Functions:00-
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/TraceSetup.cpp.func-sort-c.html b/html/DRAMSys/simulator/TraceSetup.cpp.func-sort-c.html new file mode 100644 index 00000000..72a4a8e6 --- /dev/null +++ b/html/DRAMSys/simulator/TraceSetup.cpp.func-sort-c.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/TraceSetup.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/simulator - TraceSetup.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:374386.0 %
Date:2020-06-30 17:34:44Functions:55100.0 %
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Function Name Sort by function nameHit count Sort by hit count
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+
+
+ + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/DRAMSys/simulator/TraceSetup.cpp.func.html b/html/DRAMSys/simulator/TraceSetup.cpp.func.html new file mode 100644 index 00000000..3d339549 --- /dev/null +++ b/html/DRAMSys/simulator/TraceSetup.cpp.func.html @@ -0,0 +1,97 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/simulator/TraceSetup.cpp - functions + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top level - DRAMSys/simulator - TraceSetup.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:374386.0 %
Date:2020-06-30 17:34:44Functions:55100.0 %
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Generated by: LCOV version 1.13
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Generated by: LCOV version 1.13
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Date:2020-06-30 17:34:44Functions:1250.0 %
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Generated by: LCOV version 1.13
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Generated by: LCOV version 1.13
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100.0%
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Generated by: LCOV version 1.13
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_Z41__static_initialization_and_destruction_1ii30
main30
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Generated by: LCOV version 1.13
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_Z41__static_initialization_and_destruction_1ii30
main30
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Generated by: LCOV version 1.13
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Generated by: LCOV version 1.13
+
+ + + diff --git a/html/gcov.css b/html/gcov.css new file mode 100644 index 00000000..bfd0a83e --- /dev/null +++ b/html/gcov.css @@ -0,0 +1,519 @@ +/* All views: initial background and text color */ +body +{ + color: #000000; + background-color: #FFFFFF; +} + +/* All views: standard link format*/ +a:link +{ + color: #284FA8; + text-decoration: underline; +} + +/* All views: standard link - visited format */ +a:visited +{ + color: #00CB40; + text-decoration: underline; +} + +/* All views: standard link - activated format */ +a:active +{ + color: #FF0040; + text-decoration: underline; +} + +/* All views: main title format */ +td.title +{ + text-align: center; + padding-bottom: 10px; + font-family: sans-serif; + font-size: 20pt; + font-style: italic; + font-weight: bold; +} + +/* All views: header item format */ +td.headerItem +{ + text-align: right; + padding-right: 6px; + font-family: sans-serif; + font-weight: bold; + vertical-align: top; + white-space: nowrap; +} + +/* All views: header item value format */ +td.headerValue +{ + text-align: left; + color: #284FA8; + font-family: sans-serif; + font-weight: bold; + white-space: nowrap; +} + +/* All views: header item coverage table heading */ +td.headerCovTableHead +{ + text-align: center; + padding-right: 6px; + padding-left: 6px; + padding-bottom: 0px; + font-family: sans-serif; + font-size: 80%; + white-space: nowrap; +} + +/* All views: header item coverage table entry */ +td.headerCovTableEntry +{ + text-align: right; + color: #284FA8; + font-family: sans-serif; + font-weight: bold; + white-space: nowrap; + padding-left: 12px; + padding-right: 4px; + background-color: #DAE7FE; +} + +/* All views: header item coverage table entry for high coverage rate */ +td.headerCovTableEntryHi +{ + text-align: right; + color: #000000; + font-family: sans-serif; + font-weight: bold; + white-space: nowrap; + padding-left: 12px; + padding-right: 4px; + background-color: #A7FC9D; +} + +/* All views: header item coverage table entry for medium coverage rate */ +td.headerCovTableEntryMed +{ + text-align: right; + color: #000000; + font-family: sans-serif; + font-weight: bold; + white-space: nowrap; + padding-left: 12px; + padding-right: 4px; + background-color: #FFEA20; +} + +/* All views: header item coverage table entry for ow coverage rate */ +td.headerCovTableEntryLo +{ + text-align: right; + color: #000000; + font-family: sans-serif; + font-weight: bold; + white-space: nowrap; + padding-left: 12px; + padding-right: 4px; + background-color: #FF0000; +} + +/* All views: header legend value for legend entry */ +td.headerValueLeg +{ + text-align: left; + color: #000000; + font-family: sans-serif; + font-size: 80%; + white-space: nowrap; + padding-top: 4px; +} + +/* All views: color of horizontal ruler */ +td.ruler +{ + background-color: #6688D4; +} + +/* All views: version string format */ +td.versionInfo +{ + text-align: center; + padding-top: 2px; + font-family: sans-serif; + font-style: italic; +} + +/* Directory view/File view (all)/Test case descriptions: + table headline format */ +td.tableHead +{ + text-align: center; + color: #FFFFFF; + background-color: #6688D4; + font-family: sans-serif; + font-size: 120%; + font-weight: bold; + white-space: nowrap; + padding-left: 4px; + padding-right: 4px; +} + +span.tableHeadSort +{ + padding-right: 4px; +} + +/* Directory view/File view (all): filename entry format */ +td.coverFile +{ + text-align: left; + padding-left: 10px; + padding-right: 20px; + color: #284FA8; + background-color: #DAE7FE; + font-family: monospace; +} + +/* Directory view/File view (all): bar-graph entry format*/ +td.coverBar +{ + padding-left: 10px; + padding-right: 10px; + background-color: #DAE7FE; +} + +/* Directory view/File view (all): bar-graph outline color */ +td.coverBarOutline +{ + background-color: #000000; +} + +/* Directory view/File view (all): percentage entry for files with + high coverage rate */ +td.coverPerHi +{ + text-align: right; + padding-left: 10px; + padding-right: 10px; + background-color: #A7FC9D; + font-weight: bold; + font-family: sans-serif; +} + +/* Directory view/File view (all): line count entry for files with + high coverage rate */ +td.coverNumHi +{ + text-align: right; + padding-left: 10px; + padding-right: 10px; + background-color: #A7FC9D; + white-space: nowrap; + font-family: sans-serif; +} + +/* Directory view/File view (all): percentage entry for files with + medium coverage rate */ +td.coverPerMed +{ + text-align: right; + padding-left: 10px; + padding-right: 10px; + background-color: #FFEA20; + font-weight: bold; + font-family: sans-serif; +} + +/* Directory view/File view (all): line count entry for files with + medium coverage rate */ +td.coverNumMed +{ + text-align: right; + padding-left: 10px; + padding-right: 10px; + background-color: #FFEA20; + white-space: nowrap; + font-family: sans-serif; +} + +/* Directory view/File view (all): percentage entry for files with + low coverage rate */ +td.coverPerLo +{ + text-align: right; + padding-left: 10px; + padding-right: 10px; + background-color: #FF0000; + font-weight: bold; + font-family: sans-serif; +} + +/* Directory view/File view (all): line count entry for files with + low coverage rate */ +td.coverNumLo +{ + text-align: right; + padding-left: 10px; + padding-right: 10px; + background-color: #FF0000; + white-space: nowrap; + font-family: sans-serif; +} + +/* File view (all): "show/hide details" link format */ +a.detail:link +{ + color: #B8D0FF; + font-size:80%; +} + +/* File view (all): "show/hide details" link - visited format */ +a.detail:visited +{ + color: #B8D0FF; + font-size:80%; +} + +/* File view (all): "show/hide details" link - activated format */ +a.detail:active +{ + color: #FFFFFF; + font-size:80%; +} + +/* File view (detail): test name entry */ +td.testName +{ + text-align: right; + padding-right: 10px; + background-color: #DAE7FE; + font-family: sans-serif; +} + +/* File view (detail): test percentage entry */ +td.testPer +{ + text-align: right; + padding-left: 10px; + padding-right: 10px; + background-color: #DAE7FE; + font-family: sans-serif; +} + +/* File view (detail): test lines count entry */ +td.testNum +{ + text-align: right; + padding-left: 10px; + padding-right: 10px; + background-color: #DAE7FE; + font-family: sans-serif; +} + +/* Test case descriptions: test name format*/ +dt +{ + font-family: sans-serif; + font-weight: bold; +} + +/* Test case descriptions: description table body */ +td.testDescription +{ + padding-top: 10px; + padding-left: 30px; + padding-bottom: 10px; + padding-right: 30px; + background-color: #DAE7FE; +} + +/* Source code view: function entry */ +td.coverFn +{ + text-align: left; + padding-left: 10px; + padding-right: 20px; + color: #284FA8; + background-color: #DAE7FE; + font-family: monospace; +} + +/* Source code view: function entry zero count*/ +td.coverFnLo +{ + text-align: right; + padding-left: 10px; + padding-right: 10px; + background-color: #FF0000; + font-weight: bold; + font-family: sans-serif; +} + +/* Source code view: function entry nonzero count*/ +td.coverFnHi +{ + text-align: right; + padding-left: 10px; + padding-right: 10px; + background-color: #DAE7FE; + font-weight: bold; + font-family: sans-serif; +} + +/* Source code view: source code format */ +pre.source +{ + font-family: monospace; + white-space: pre; + margin-top: 2px; +} + +/* Source code view: line number format */ +span.lineNum +{ + background-color: #EFE383; +} + +/* Source code view: format for lines which were executed */ +td.lineCov, +span.lineCov +{ + background-color: #CAD7FE; +} + +/* Source code view: format for Cov legend */ +span.coverLegendCov +{ + padding-left: 10px; + padding-right: 10px; + padding-bottom: 2px; + background-color: #CAD7FE; +} + +/* Source code view: format for lines which were not executed */ +td.lineNoCov, +span.lineNoCov +{ + background-color: #FF6230; +} + +/* Source code view: format for NoCov legend */ +span.coverLegendNoCov +{ + padding-left: 10px; + padding-right: 10px; + padding-bottom: 2px; + background-color: #FF6230; +} + +/* Source code view (function table): standard link - visited format */ +td.lineNoCov > a:visited, +td.lineCov > a:visited +{ + color: black; + text-decoration: underline; +} + +/* Source code view: format for lines which were executed only in a + previous version */ +span.lineDiffCov +{ + background-color: #B5F7AF; +} + +/* Source code view: format for branches which were executed + * and taken */ +span.branchCov +{ + background-color: #CAD7FE; +} + +/* Source code view: format for branches which were executed + * but not taken */ +span.branchNoCov +{ + background-color: #FF6230; +} + +/* Source code view: format for branches which were not executed */ +span.branchNoExec +{ + background-color: #FF6230; +} + +/* Source code view: format for the source code heading line */ +pre.sourceHeading +{ + white-space: pre; + font-family: monospace; + font-weight: bold; + margin: 0px; +} + +/* All views: header legend value for low rate */ +td.headerValueLegL +{ + font-family: sans-serif; + text-align: center; + white-space: nowrap; + padding-left: 4px; + padding-right: 2px; + background-color: #FF0000; + font-size: 80%; +} + +/* All views: header legend value for med rate */ +td.headerValueLegM +{ + font-family: sans-serif; + text-align: center; + white-space: nowrap; + padding-left: 2px; + padding-right: 2px; + background-color: #FFEA20; + font-size: 80%; +} + +/* All views: header legend value for hi rate */ +td.headerValueLegH +{ + font-family: sans-serif; + text-align: center; + white-space: nowrap; + padding-left: 2px; + padding-right: 4px; + background-color: #A7FC9D; + font-size: 80%; +} + +/* All views except source code view: legend format for low coverage */ +span.coverLegendCovLo +{ + padding-left: 10px; + padding-right: 10px; + padding-top: 2px; + background-color: #FF0000; +} + +/* All views except source code view: legend format for med coverage */ +span.coverLegendCovMed +{ + padding-left: 10px; + padding-right: 10px; + padding-top: 2px; + background-color: #FFEA20; +} + +/* All views except source code view: legend format for hi coverage */ +span.coverLegendCovHi +{ + padding-left: 10px; + padding-right: 10px; + padding-top: 2px; + background-color: #A7FC9D; +} diff --git a/html/index-sort-f.html b/html/index-sort-f.html new file mode 100644 index 00000000..d9eeb09a --- /dev/null +++ b/html/index-sort-f.html @@ -0,0 +1,243 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top levelHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:3137765241.0 %
Date:2020-06-30 17:34:44Functions:40274753.8 %
Legend: Rating: + low: < 75 % + medium: >= 75 % + high: >= 90 % +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Directory Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
/DRAMSys/library/src/error/ECC +
1.4%1.4%
+ 		1.4 %2 / 1427.1 %2 / 28
/DRAMSys/library/src/error +
0.7%0.7%
+ 		0.7 %3 / 40417.6 %6 / 34
/DRAMSys/library/src/simulation/dram +
16.1%16.1%
+ 		16.1 %72 / 44835.2 %45 / 128
/DRAMSys/library/src/configuration/memspec +
42.8%42.8%
+ 		42.8 %319 / 74543.7 %38 / 87
/DRAMSys/library/src/common +
44.1%44.1%
+ 		44.1 %500 / 113547.1 %65 / 138
/DRAMSys/library/src/controller/checker +
26.8%26.8%
+ 		26.8 %802 / 298760.3 %38 / 63
/DRAMSys/simulator +
79.3%79.3%
+ 		79.3 %184 / 23268.3 %28 / 41
/DRAMSys/library/src/simulation +
55.2%55.2%
+ 		55.2 %207 / 37569.8 %30 / 43
/DRAMSys/library/src/controller/respqueue +
50.0%50.0%
+ 		50.0 %17 / 3470.0 %7 / 10
/DRAMSys/library/src/controller/refresh +
87.7%87.7%
+ 		87.7 %164 / 18773.9 %17 / 23
/DRAMSys/library/src/controller +
89.3%89.3%
+ 		89.3 %461 / 51678.6 %55 / 70
/DRAMSys/library/src/controller/cmdmux +
100.0%
+ 		100.0 %26 / 2680.0 %8 / 10
/DRAMSys/library/src/controller/scheduler +
87.8%87.8%
+ 		87.8 %101 / 11581.8 %27 / 33
/DRAMSys/library/src/controller/powerdown +
97.1%97.1%
+ 		97.1 %101 / 10490.5 %19 / 21
/DRAMSys/library/src/configuration +
88.1%88.1%
+ 		88.1 %178 / 20294.4 %17 / 18
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/index-sort-l.html b/html/index-sort-l.html new file mode 100644 index 00000000..26f46bba --- /dev/null +++ b/html/index-sort-l.html @@ -0,0 +1,243 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top levelHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:3137765241.0 %
Date:2020-06-30 17:34:44Functions:40274753.8 %
Legend: Rating: + low: < 75 % + medium: >= 75 % + high: >= 90 % +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Directory Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
/DRAMSys/library/src/error +
0.7%0.7%
+ 		0.7 %3 / 40417.6 %6 / 34
/DRAMSys/library/src/error/ECC +
1.4%1.4%
+ 		1.4 %2 / 1427.1 %2 / 28
/DRAMSys/library/src/simulation/dram +
16.1%16.1%
+ 		16.1 %72 / 44835.2 %45 / 128
/DRAMSys/library/src/controller/checker +
26.8%26.8%
+ 		26.8 %802 / 298760.3 %38 / 63
/DRAMSys/library/src/configuration/memspec +
42.8%42.8%
+ 		42.8 %319 / 74543.7 %38 / 87
/DRAMSys/library/src/common +
44.1%44.1%
+ 		44.1 %500 / 113547.1 %65 / 138
/DRAMSys/library/src/controller/respqueue +
50.0%50.0%
+ 		50.0 %17 / 3470.0 %7 / 10
/DRAMSys/library/src/simulation +
55.2%55.2%
+ 		55.2 %207 / 37569.8 %30 / 43
/DRAMSys/simulator +
79.3%79.3%
+ 		79.3 %184 / 23268.3 %28 / 41
/DRAMSys/library/src/controller/refresh +
87.7%87.7%
+ 		87.7 %164 / 18773.9 %17 / 23
/DRAMSys/library/src/controller/scheduler +
87.8%87.8%
+ 		87.8 %101 / 11581.8 %27 / 33
/DRAMSys/library/src/configuration +
88.1%88.1%
+ 		88.1 %178 / 20294.4 %17 / 18
/DRAMSys/library/src/controller +
89.3%89.3%
+ 		89.3 %461 / 51678.6 %55 / 70
/DRAMSys/library/src/controller/powerdown +
97.1%97.1%
+ 		97.1 %101 / 10490.5 %19 / 21
/DRAMSys/library/src/controller/cmdmux +
100.0%
+ 		100.0 %26 / 2680.0 %8 / 10
+
+
+ + + + +
Generated by: LCOV version 1.13
+
+ + + diff --git a/html/index.html b/html/index.html new file mode 100644 index 00000000..e46e0fb3 --- /dev/null +++ b/html/index.html @@ -0,0 +1,243 @@ + + + + + + + LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 +commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 + + + + + + + + + + + + + + +
LCOV - code coverage report
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Current view:top levelHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:3137765241.0 %
Date:2020-06-30 17:34:44Functions:40274753.8 %
Legend: Rating: + low: < 75 % + medium: >= 75 % + high: >= 90 % +
+
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Directory Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
/DRAMSys/library/src/common +
44.1%44.1%
+ 		44.1 %500 / 113547.1 %65 / 138
/DRAMSys/library/src/configuration +
88.1%88.1%
+ 		88.1 %178 / 20294.4 %17 / 18
/DRAMSys/library/src/configuration/memspec +
42.8%42.8%
+ 		42.8 %319 / 74543.7 %38 / 87
/DRAMSys/library/src/controller +
89.3%89.3%
+ 		89.3 %461 / 51678.6 %55 / 70
/DRAMSys/library/src/controller/checker +
26.8%26.8%
+ 		26.8 %802 / 298760.3 %38 / 63
/DRAMSys/library/src/controller/cmdmux +
100.0%
+ 		100.0 %26 / 2680.0 %8 / 10
/DRAMSys/library/src/controller/powerdown +
97.1%97.1%
+ 		97.1 %101 / 10490.5 %19 / 21
/DRAMSys/library/src/controller/refresh +
87.7%87.7%
+ 		87.7 %164 / 18773.9 %17 / 23
/DRAMSys/library/src/controller/respqueue +
50.0%50.0%
+ 		50.0 %17 / 3470.0 %7 / 10
/DRAMSys/library/src/controller/scheduler +
87.8%87.8%
+ 		87.8 %101 / 11581.8 %27 / 33
/DRAMSys/library/src/error +
0.7%0.7%
+ 		0.7 %3 / 40417.6 %6 / 34
/DRAMSys/library/src/error/ECC +
1.4%1.4%
+ 		1.4 %2 / 1427.1 %2 / 28
/DRAMSys/library/src/simulation +
55.2%55.2%
+ 		55.2 %207 / 37569.8 %30 / 43
/DRAMSys/library/src/simulation/dram +
16.1%16.1%
+ 		16.1 %72 / 44835.2 %45 / 128
/DRAMSys/simulator +
79.3%79.3%
+ 		79.3 %184 / 23268.3 %28 / 41
+
+
+ + + + +
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Date:2020-06-30 17:34:44Functions:215736.8 %
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/common - dramExtensions.cpp (source / functions)HitTotalCoverage
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:4713235.6 %
Date:2020-06-30 17:34:44Functions:215736.8 %
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LCOV - code coverage report
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Current view:top level - DRAMSys/library/src/common - dramExtensions.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:1818100.0 %
Date:2020-06-30 17:34:44Functions:2450.0 %
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- - - diff --git a/html/DRAMSys/library/src/common/tlm2_base_protocol_checker.h.func.html b/html/DRAMSys/library/src/common/tlm2_base_protocol_checker.h.func.html deleted file mode 100644 index c55a87b4..00000000 --- a/html/DRAMSys/library/src/common/tlm2_base_protocol_checker.h.func.html +++ /dev/null @@ -1,181 +0,0 @@ - - - - - - - LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 -commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/common/tlm2_base_protocol_checker.h - functions - - - - - - - - - - - - - - -
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/common - tlm2_base_protocol_checker.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:14720.2 %
Date:2020-06-30 17:34:44Functions:0280.0 %
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Function Name Sort by function nameHit count Sort by hit count
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_ZN9tlm_utils26tlm2_base_protocol_checkerILj32EE26nb_transport_fw_pre_checksERN3tlm19tlm_generic_payloadERNS2_9tlm_phaseERN7sc_core7sc_timeE0
_ZN9tlm_utils26tlm2_base_protocol_checkerILj32EE28nb_transport_response_checksERN3tlm19tlm_generic_payloadERNS2_9tlm_phaseERN7sc_core7sc_timeEPKcSB_SB_0
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_ZN9tlm_utils26tlm2_base_protocol_checkerILj32EED1Ev0
_ZN9tlm_utils6path_tC2Ev0
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Generated by: LCOV version 1.13
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- - - diff --git a/html/DRAMSys/library/src/common/tlm2_base_protocol_checker.h.gcov.html b/html/DRAMSys/library/src/common/tlm2_base_protocol_checker.h.gcov.html deleted file mode 100644 index b3cf78ce..00000000 --- a/html/DRAMSys/library/src/common/tlm2_base_protocol_checker.h.gcov.html +++ /dev/null @@ -1,1128 +0,0 @@ - - - - - - - LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 -commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/common/tlm2_base_protocol_checker.h - - - - - - - - - - - - - - -
LCOV - code coverage report
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Current view:top level - DRAMSys/library/src/common - tlm2_base_protocol_checker.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:14720.2 %
Date:2020-06-30 17:34:44Functions:0280.0 %
Legend: Lines: - hit - not hit -
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Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerDDR4.cpp (source / functions)HitTotalCoverage
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commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:18730860.7 %
Date:2020-06-30 17:34:44Functions:55100.0 %
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Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN11CheckerDDR4C2Ev30
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Generated by: LCOV version 1.13
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerDDR4.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:18730860.7 %
Date:2020-06-30 17:34:44Functions:55100.0 %
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Function Name Sort by function nameHit count Sort by hit count
_GLOBAL__sub_I__ZN11CheckerDDR4C2Ev30
_Z41__static_initialization_and_destruction_0ii30
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_ZNK11CheckerDDR424timeToSatisfyConstraintsE7Command4Rank9BankGroup4Bank5298882
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Generated by: LCOV version 1.13
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- - - diff --git a/html/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp.gcov.html b/html/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp.gcov.html deleted file mode 100644 index dc96b501..00000000 --- a/html/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp.gcov.html +++ /dev/null @@ -1,547 +0,0 @@ - - - - - - - LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 -commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerDDR4.cpp - - - - - - - - - - - - - - -
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerDDR4.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:18730860.7 %
Date:2020-06-30 17:34:44Functions:55100.0 %
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerDDR4.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
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LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerDDR4.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerHBM2.cpp (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:17633951.9 %
Date:2020-06-30 17:34:44Functions:55100.0 %
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Generated by: LCOV version 1.13
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- - - diff --git a/html/DRAMSys/library/src/controller/checker/CheckerHBM2.h.func-sort-c.html b/html/DRAMSys/library/src/controller/checker/CheckerHBM2.h.func-sort-c.html deleted file mode 100644 index 68ec3d7b..00000000 --- a/html/DRAMSys/library/src/controller/checker/CheckerHBM2.h.func-sort-c.html +++ /dev/null @@ -1,85 +0,0 @@ - - - - - - - LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 -commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerHBM2.h - functions - - - - - - - - - - - - - - -
LCOV - code coverage report
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Current view:top level - DRAMSys/library/src/controller/checker - CheckerHBM2.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
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Function Name Sort by function nameHit count Sort by hit count
_ZN11CheckerHBM2D0Ev14
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Generated by: LCOV version 1.13
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- - - diff --git a/html/DRAMSys/library/src/controller/checker/CheckerHBM2.h.func.html b/html/DRAMSys/library/src/controller/checker/CheckerHBM2.h.func.html deleted file mode 100644 index 45ac0a30..00000000 --- a/html/DRAMSys/library/src/controller/checker/CheckerHBM2.h.func.html +++ /dev/null @@ -1,85 +0,0 @@ - - - - - - - LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 -commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerHBM2.h - functions - - - - - - - - - - - - - - -
LCOV - code coverage report
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Current view:top level - DRAMSys/library/src/controller/checker - CheckerHBM2.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
Legend: Lines: - hit - not hit -
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Function Name Sort by function nameHit count Sort by hit count
_ZN11CheckerHBM2D0Ev14
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Generated by: LCOV version 1.13
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- - - diff --git a/html/DRAMSys/library/src/controller/checker/CheckerHBM2.h.gcov.html b/html/DRAMSys/library/src/controller/checker/CheckerHBM2.h.gcov.html deleted file mode 100644 index 4234ac88..00000000 --- a/html/DRAMSys/library/src/controller/checker/CheckerHBM2.h.gcov.html +++ /dev/null @@ -1,129 +0,0 @@ - - - - - - - LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 -commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - /DRAMSys/library/src/controller/checker/CheckerHBM2.h - - - - - - - - - - - - - - -
LCOV - code coverage report
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Current view:top level - DRAMSys/library/src/controller/checker - CheckerHBM2.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:11100.0 %
Date:2020-06-30 17:34:44Functions:22100.0 %
Legend: Lines: - hit - not hit -
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Current view:top level - DRAMSys/library/src/controller/powerdown - PowerDownManagerStaggered.h (source / functions)HitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
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Dram.h -
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-} - -/* Source code view: format for branches which were executed - * and taken */ -span.branchCov -{ - background-color: #CAD7FE; -} - -/* Source code view: format for branches which were executed - * but not taken */ -span.branchNoCov -{ - background-color: #FF6230; -} - -/* Source code view: format for branches which were not executed */ -span.branchNoExec -{ - background-color: #FF6230; -} - -/* Source code view: format for the source code heading line */ -pre.sourceHeading -{ - white-space: pre; - font-family: monospace; - font-weight: bold; - margin: 0px; -} - -/* All views: header legend value for low rate */ -td.headerValueLegL -{ - font-family: sans-serif; - text-align: center; - white-space: nowrap; - padding-left: 4px; - padding-right: 2px; - background-color: #FF0000; - font-size: 80%; -} - -/* All views: header legend value for med rate */ -td.headerValueLegM -{ - font-family: sans-serif; - text-align: center; - white-space: nowrap; - padding-left: 2px; - padding-right: 2px; - background-color: #FFEA20; - font-size: 80%; -} - -/* All views: header legend value for hi rate */ -td.headerValueLegH -{ - font-family: sans-serif; - text-align: center; - white-space: nowrap; - padding-left: 2px; - padding-right: 4px; - background-color: #A7FC9D; - font-size: 80%; -} - -/* All views except source code view: legend format for low coverage */ -span.coverLegendCovLo -{ - padding-left: 10px; - padding-right: 10px; - padding-top: 2px; - background-color: #FF0000; -} - -/* All views except source code view: legend format for med coverage */ -span.coverLegendCovMed -{ - padding-left: 10px; - padding-right: 10px; - padding-top: 2px; - background-color: #FFEA20; -} - -/* All views except source code view: legend format for hi coverage */ -span.coverLegendCovHi -{ - padding-left: 10px; - padding-right: 10px; - padding-top: 2px; - background-color: #A7FC9D; -} diff --git a/html/index-sort-f.html b/html/index-sort-f.html deleted file mode 100644 index d9eeb09a..00000000 --- a/html/index-sort-f.html +++ /dev/null @@ -1,243 +0,0 @@ - - - - - - - LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 -commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - - - - - - - - - - - - - - -
LCOV - code coverage report
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Current view:top levelHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:3137765241.0 %
Date:2020-06-30 17:34:44Functions:40274753.8 %
Legend: Rating: - low: < 75 % - medium: >= 75 % - high: >= 90 % -
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Directory Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
/DRAMSys/library/src/error/ECC -
1.4%1.4%
- 		1.4 %2 / 1427.1 %2 / 28
/DRAMSys/library/src/error -
0.7%0.7%
- 		0.7 %3 / 40417.6 %6 / 34
/DRAMSys/library/src/simulation/dram -
16.1%16.1%
- 		16.1 %72 / 44835.2 %45 / 128
/DRAMSys/library/src/configuration/memspec -
42.8%42.8%
- 		42.8 %319 / 74543.7 %38 / 87
/DRAMSys/library/src/common -
44.1%44.1%
- 		44.1 %500 / 113547.1 %65 / 138
/DRAMSys/library/src/controller/checker -
26.8%26.8%
- 		26.8 %802 / 298760.3 %38 / 63
/DRAMSys/simulator -
79.3%79.3%
- 		79.3 %184 / 23268.3 %28 / 41
/DRAMSys/library/src/simulation -
55.2%55.2%
- 		55.2 %207 / 37569.8 %30 / 43
/DRAMSys/library/src/controller/respqueue -
50.0%50.0%
- 		50.0 %17 / 3470.0 %7 / 10
/DRAMSys/library/src/controller/refresh -
87.7%87.7%
- 		87.7 %164 / 18773.9 %17 / 23
/DRAMSys/library/src/controller -
89.3%89.3%
- 		89.3 %461 / 51678.6 %55 / 70
/DRAMSys/library/src/controller/cmdmux -
100.0%
- 		100.0 %26 / 2680.0 %8 / 10
/DRAMSys/library/src/controller/scheduler -
87.8%87.8%
- 		87.8 %101 / 11581.8 %27 / 33
/DRAMSys/library/src/controller/powerdown -
97.1%97.1%
- 		97.1 %101 / 10490.5 %19 / 21
/DRAMSys/library/src/configuration -
88.1%88.1%
- 		88.1 %178 / 20294.4 %17 / 18
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-
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Generated by: LCOV version 1.13
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- - - diff --git a/html/index-sort-l.html b/html/index-sort-l.html deleted file mode 100644 index 26f46bba..00000000 --- a/html/index-sort-l.html +++ /dev/null @@ -1,243 +0,0 @@ - - - - - - - LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 -commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - - - - - - - - - - - - - - -
LCOV - code coverage report
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Current view:top levelHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:3137765241.0 %
Date:2020-06-30 17:34:44Functions:40274753.8 %
Legend: Rating: - low: < 75 % - medium: >= 75 % - high: >= 90 % -
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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Directory Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
/DRAMSys/library/src/error -
0.7%0.7%
- 		0.7 %3 / 40417.6 %6 / 34
/DRAMSys/library/src/error/ECC -
1.4%1.4%
- 		1.4 %2 / 1427.1 %2 / 28
/DRAMSys/library/src/simulation/dram -
16.1%16.1%
- 		16.1 %72 / 44835.2 %45 / 128
/DRAMSys/library/src/controller/checker -
26.8%26.8%
- 		26.8 %802 / 298760.3 %38 / 63
/DRAMSys/library/src/configuration/memspec -
42.8%42.8%
- 		42.8 %319 / 74543.7 %38 / 87
/DRAMSys/library/src/common -
44.1%44.1%
- 		44.1 %500 / 113547.1 %65 / 138
/DRAMSys/library/src/controller/respqueue -
50.0%50.0%
- 		50.0 %17 / 3470.0 %7 / 10
/DRAMSys/library/src/simulation -
55.2%55.2%
- 		55.2 %207 / 37569.8 %30 / 43
/DRAMSys/simulator -
79.3%79.3%
- 		79.3 %184 / 23268.3 %28 / 41
/DRAMSys/library/src/controller/refresh -
87.7%87.7%
- 		87.7 %164 / 18773.9 %17 / 23
/DRAMSys/library/src/controller/scheduler -
87.8%87.8%
- 		87.8 %101 / 11581.8 %27 / 33
/DRAMSys/library/src/configuration -
88.1%88.1%
- 		88.1 %178 / 20294.4 %17 / 18
/DRAMSys/library/src/controller -
89.3%89.3%
- 		89.3 %461 / 51678.6 %55 / 70
/DRAMSys/library/src/controller/powerdown -
97.1%97.1%
- 		97.1 %101 / 10490.5 %19 / 21
/DRAMSys/library/src/controller/cmdmux -
100.0%
- 		100.0 %26 / 2680.0 %8 / 10
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Generated by: LCOV version 1.13
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- - - diff --git a/html/index.html b/html/index.html deleted file mode 100644 index e46e0fb3..00000000 --- a/html/index.html +++ /dev/null @@ -1,243 +0,0 @@ - - - - - - - LCOV - commit 1b407b235a58a703f16d9ba60bf2738364073414 -commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127 - - - - - - - - - - - - - - -
LCOV - code coverage report
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Current view:top levelHitTotalCoverage
Test:commit 1b407b235a58a703f16d9ba60bf2738364073414
commit 46f4d1d61b3bdc54a5d40e7dff9ce320d3076127		Lines:3137765241.0 %
Date:2020-06-30 17:34:44Functions:40274753.8 %
Legend: Rating: - low: < 75 % - medium: >= 75 % - high: >= 90 % -
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Directory Sort by nameLine Coverage Sort by line coverageFunctions Sort by function coverage
/DRAMSys/library/src/common -
44.1%44.1%
- 		44.1 %500 / 113547.1 %65 / 138
/DRAMSys/library/src/configuration -
88.1%88.1%
- 		88.1 %178 / 20294.4 %17 / 18
/DRAMSys/library/src/configuration/memspec -
42.8%42.8%
- 		42.8 %319 / 74543.7 %38 / 87
/DRAMSys/library/src/controller -
89.3%89.3%
- 		89.3 %461 / 51678.6 %55 / 70
/DRAMSys/library/src/controller/checker -
26.8%26.8%
- 		26.8 %802 / 298760.3 %38 / 63
/DRAMSys/library/src/controller/cmdmux -
100.0%
- 		100.0 %26 / 2680.0 %8 / 10
/DRAMSys/library/src/controller/powerdown -
97.1%97.1%
- 		97.1 %101 / 10490.5 %19 / 21
/DRAMSys/library/src/controller/refresh -
87.7%87.7%
- 		87.7 %164 / 18773.9 %17 / 23
/DRAMSys/library/src/controller/respqueue -
50.0%50.0%
- 		50.0 %17 / 3470.0 %7 / 10
/DRAMSys/library/src/controller/scheduler -
87.8%87.8%
- 		87.8 %101 / 11581.8 %27 / 33
/DRAMSys/library/src/error -
0.7%0.7%
- 		0.7 %3 / 40417.6 %6 / 34
/DRAMSys/library/src/error/ECC -
1.4%1.4%
- 		1.4 %2 / 1427.1 %2 / 28
/DRAMSys/library/src/simulation -
55.2%55.2%
- 		55.2 %207 / 37569.8 %30 / 43
/DRAMSys/library/src/simulation/dram -
16.1%16.1%
- 		16.1 %72 / 44835.2 %45 / 128
/DRAMSys/simulator -
79.3%79.3%
- 		79.3 %184 / 23268.3 %28 / 41
-
-
- - - - -
Generated by: LCOV version 1.13
-
- - - From 56fa53b7848366ebe48daf4afec7df0a5835621e Mon Sep 17 00:00:00 2001 From: scorrea Date: Tue, 30 Jun 2020 19:02:22 +0200 Subject: [PATCH 33/34] export COVERAGE=true --- .gitlab-ci.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index bb478fa4..5540c9c6 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -20,6 +20,7 @@ build: - rm -rf build - mkdir -p build - cd build + - export COVERAGE=true - cmake ../DRAMSys - make -j 16 - find . -name "*.o" -type f -delete From aca89f7a079b6bf193a66d2c6f101efa865ba8f6 Mon Sep 17 00:00:00 2001 From: scorrea Date: Thu, 2 Jul 2020 12:38:47 +0200 Subject: [PATCH 34/34] power analysis enabled for ddr3 and ddr4 --- .../DDR4/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json | 2 +- DRAMSys/tests/DDR4/configs/simulator/ddr4.json | 2 +- DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/DRAMSys/tests/DDR4/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json b/DRAMSys/tests/DDR4/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json index adbfd117..38a5701a 100644 --- a/DRAMSys/tests/DDR4/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json +++ b/DRAMSys/tests/DDR4/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json @@ -65,4 +65,4 @@ "clkMhz": 933 } } -} \ No newline at end of file +} diff --git a/DRAMSys/tests/DDR4/configs/simulator/ddr4.json b/DRAMSys/tests/DDR4/configs/simulator/ddr4.json index 05cd86e2..c88964d3 100644 --- a/DRAMSys/tests/DDR4/configs/simulator/ddr4.json +++ b/DRAMSys/tests/DDR4/configs/simulator/ddr4.json @@ -8,7 +8,7 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "PowerAnalysis": false, + "PowerAnalysis": true, "SimulationName": "ddr4", "SimulationProgressBar": true, "StoreMode": "NoStorage", diff --git a/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json b/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json index 99ccdb45..1ade5aea 100644 --- a/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json +++ b/DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json @@ -8,7 +8,7 @@ "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, - "PowerAnalysis": false, + "PowerAnalysis": true, "SimulationName": "ddr3", "SimulationProgressBar": true, "StoreMode": "NoStorage",