a4fe32703c
Set up testing infrastructure for Cache
2023-04-13 11:21:36 +02:00
45e31f5b5a
First integration of Cache
2023-04-13 11:21:36 +02:00
c8e509a120
Add EccModule to simulator
2023-04-13 11:21:36 +02:00
2d0445d5a7
Introduce demonstrator for new simulator concept
2023-04-13 11:21:34 +02:00
d27a29ca80
Refactor configuration library
...
The configuration library has been refactored to make use of nlohmann
macros to reduce boilerplate code.
The nlohmann parser callback is used to decide whether to include
configuration json objects directly, or if they need to be loaded
from a sperate file.
2023-04-13 11:18:39 +02:00
Lukas Steiner
0d09222ab5
Implement cache into checker.
2023-04-13 11:07:55 +02:00
Lukas Steiner
65a20e9827
Remove checker from BM, RM and PDM.
2023-04-13 09:57:50 +02:00
Lukas Steiner
088621880c
Rename methods to evaluate and update.
2023-04-12 16:47:26 +02:00
Lukas Steiner
a95db95030
Merge branch 'work/DDR5' into 'develop'
...
Implement new DDR5 tCCD_M timings
See merge request ems/astdm/modeling.dram/dram.sys.5!13
2023-04-12 13:53:39 +00:00
Lukas Steiner
5f1c74790b
Remove duplicate checks in DDR5 checker.
2023-04-12 13:45:44 +00:00
507c1d32d6
Update tCCD_L_WR, tCCD_L_WR2 and tCCD_M_WR timings in DDR5 timing checker
2023-04-12 09:40:18 +02:00
949cf944bc
Update tCCD_M timings in memspecs for DDR5
2023-04-11 14:27:26 +02:00
60b2bcbffa
Fix DDR5 write-to-write delay in TimingChecker
2023-04-11 14:08:32 +02:00
49954df6ee
Add tCCD_M DDR5 timings, MemSpecs still incomplete
2023-04-06 10:38:48 +02:00
Lukas Steiner
daecc19252
Merge branch 'lpddr5' into 'develop'
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Add LPDDR5X configurations and separate tRCD into tRCDRD and tRCDWR
See merge request ems/astdm/modeling.dram/dram.sys.5!12
2023-03-30 13:12:30 +00:00
Lukas Steiner
b086fa985d
Change names of LPDDR5 timings from tRCDRD/tRCDWR to tRCD_L/tRCD_S.
2023-03-30 15:06:17 +02:00
5d7171e537
Add LPDDR5X configurations and separate tRCD into tRCDRD and tRCDWR
2023-03-29 16:49:15 +02:00
Lukas Steiner
b29c67481d
Merge branch 'fix/plots' into 'develop'
...
Update plots python script to new database layout
See merge request ems/astdm/modeling.dram/dram.sys.5!11
2023-03-24 13:24:49 +00:00
Lukas Steiner
964e4949cc
Merge branch 'bug/payload_id_github' into 'develop'
...
Increment nextChannelPayloadIDToAppend only once.
See merge request ems/astdm/modeling.dram/dram.sys.5!10
2023-03-24 08:50:04 +00:00
6cb2128612
Update plots python script to new database layout
2023-03-24 09:18:06 +01:00
Lukas Steiner
af386b4852
Increment nextChannelPayloadIDToAppend only once.
2023-03-23 10:27:48 +00:00
Lukas Steiner
28e62e3fa5
Merge branch 'linker_fix' into 'develop'
...
Fix test_dramsys linker error
See merge request ems/astdm/modeling.dram/dram.sys.5!9
2023-03-23 10:22:32 +00:00
Lukas Steiner
5621bd41b4
Decrease artifacts expiration to 1 hour.
2023-03-23 11:14:52 +01:00
Lukas Steiner
a36ce91225
Remove .a files from artifacts.
2023-03-23 10:52:32 +01:00
c51e21ea69
Fix test_dramsys linker error
2023-03-22 12:57:25 +01:00
Lukas Steiner
4bfd485069
Merge branch 'bug/lp5_r2r' into 'develop'
...
Add fix for LP5 rank2rank timings.
See merge request ems/astdm/modeling.dram/dram.sys.5!8
2023-03-22 09:52:25 +00:00
Lukas Steiner
e3b872446f
Merge branch 'work/b_transport' into 'develop'
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Implement b_transport and add tests
See merge request ems/astdm/modeling.dram/dram.sys.5!3
2023-03-22 09:51:17 +00:00
Lukas Steiner
d18778a40a
Minor refactor.
2023-03-22 10:44:48 +01:00
Lukas Steiner
04ca902cf4
Minor renaming and formatting.
2023-03-22 10:13:16 +01:00
Lukas Steiner
bb99b9e883
Add fix for LP5 rank2rank timings.
2023-03-20 16:51:36 +01:00
53d913c5f1
Make BlockingRead/WriteDelay configurable
2023-03-17 09:45:11 +01:00
Lukas Steiner
7621ac4a1d
Merge branch 'work/cmake_presets' into 'develop'
...
Run CTest in GitLab CI
See merge request ems/astdm/modeling.dram/dram.sys.5!7
2023-03-17 08:42:03 +00:00
Lukas Steiner
a16313b393
Merge branch 'python_caller' into 'develop'
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Revert the design choice of making the PythonCaller a static singleton
See merge request ems/astdm/modeling.dram/dram.sys.5!6
2023-03-13 13:59:33 +00:00
d7bc0f2d32
Use non-interactive frontend in GitLab CI
2023-03-10 13:39:39 +01:00
bd899a2104
Integrate regression tests with CTest
2023-03-10 13:32:55 +01:00
7ab71876d9
Run CTest in GitLab CI
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Change image to Ubuntu as at least CMake 5.19 is needed
2023-03-09 12:21:47 +01:00
aa0b8e9160
Use CMakePresets to define CI/CD configurations and introduce coverage target
2023-03-09 10:58:26 +01:00
b3277b2e52
Revert the design choice of making the PythonCaller a static singleton
2023-03-07 11:39:16 +01:00
Lukas Steiner
e00ee59631
Merge branch 'work/project_refactor' into 'develop'
...
Refactoring of complete repository structure, especially CMake.
See merge request ems/astdm/modeling.dram/dram.sys.5!4
2023-03-06 13:26:00 +00:00
ac9351c025
Implement b_transport and add tests for it
2023-03-06 14:10:56 +01:00
Lukas Steiner
0268350a8e
Merge branch 'junk/try_ci_needs' into 'work/project_refactor'
...
Reorganize config files, remove unused config.
See merge request ems/astdm/modeling.dram/dram.sys.5!2
2023-02-23 16:15:53 +00:00
Lukas Steiner
823d473d97
Fix path in CI script.
2023-02-23 17:09:33 +01:00
Lukas Steiner
c4ca3d71d7
Reorganize config files, remove unused config.
2023-02-23 17:02:21 +01:00
Lukas Steiner
bbf0cdf4a9
Merge branch 'junk/try_ci_needs' into 'work/project_refactor'
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Run CI tests in parallel.
See merge request ems/astdm/modeling.dram/dram.sys.5!1
2023-02-23 13:35:52 +00:00
Lukas Steiner
39b456d837
Use one stage for all tests.
2023-02-23 14:09:16 +01:00
Lukas Steiner
56b404b291
Fix job name for needs.
2023-02-23 13:59:35 +01:00
Lukas Steiner
ac04ae66ce
Retry CI needs with coverage.
2023-02-23 13:56:15 +01:00
Lukas Steiner
579106b13d
Fix coverage excludes.
2023-02-23 13:40:17 +01:00
Lukas Steiner
2d44f36d2e
Remove 3rd party modules from coverage report.
2023-02-23 13:23:47 +01:00
Lukas Steiner
661819f381
Path fix for DDR3 test.
2023-02-23 11:36:17 +01:00
