Lukas Steiner
|
b272baa6f9
|
Add length converter, add burst length checks.
|
2022-02-15 15:04:20 +01:00 |
|
Lukas Steiner
|
3e629edd29
|
Add asserts for illegal burst lengths.
|
2022-02-09 16:17:56 +01:00 |
|
Lukas Steiner
|
56e6fd31a3
|
Introduce new commands on simulator side.
|
2021-12-03 09:36:39 +01:00 |
|
Lukas Steiner
|
aba8398a2d
|
Replace deprecated headers "systemc.h" and "tlm.h".
|
2021-08-17 16:26:01 +02:00 |
|
Lukas Steiner
|
d6b8e73827
|
Change type of command from enum to class.
|
2021-05-31 15:19:48 +02:00 |
|
Lukas Steiner
|
1b58c916b0
|
Code refactoring.
|
2021-05-20 15:56:41 +02:00 |
|
Lukas Steiner
|
cb4455710d
|
Add config files for STT-MRAM.
|
2021-05-17 15:51:55 +02:00 |
|
Lukas Steiner
|
e38d0aae1f
|
Introduce burst length parameter.
|
2021-05-05 17:10:08 +02:00 |
|
Lukas Steiner
|
0f6611bacd
|
Use sc_max_time() instead of SC_ZERO_TIME in all checkers.
|
2021-01-20 17:19:20 +01:00 |
|
Lukas Steiner
|
020a01fd78
|
Only allow pointer to const for memspec.
|
2021-01-19 13:53:28 +01:00 |
|
Lukas Steiner
|
d2a90773eb
|
Add read and write preambles to DDR4.
|
2020-08-18 10:12:19 +02:00 |
|
Lukas Steiner
|
bacf0017ba
|
Resolve merge conflicts.
|
2020-07-06 17:57:04 +02:00 |
|
Lukas Steiner
|
0e0b80d646
|
Merge branch 'development'
# Conflicts:
# .gitlab-ci.yml
# DRAMSys/CMakeLists.txt
# DRAMSys/gem5/CMakeLists.txt
# DRAMSys/library/CMakeLists.txt
# DRAMSys/library/resources/configs/mcconfigs/fifo.json
# DRAMSys/library/resources/configs/mcconfigs/fifoStrict.json
# DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.json
# DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.json
# DRAMSys/library/resources/configs/memspecs/HBM2.json
# DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json
# DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json
# DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json
# DRAMSys/library/resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json
# DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json
# DRAMSys/library/resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json
# DRAMSys/library/resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json
# DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json
# DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json
# DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json
# DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json
# DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json
# DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json
# DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json
# DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json
# DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json
# DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json
# DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json
# DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json
# DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json
# DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json
# DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json
# DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json
# DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json
# DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json
# DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json
# DRAMSys/library/resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json
# DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json
# DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json
# DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json
# DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json
# DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json
# DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json
# DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json
# DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json
# DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json
# DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json
# DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json
# DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json
# DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json
# DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json
# DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json
# DRAMSys/library/resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json
# DRAMSys/library/resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json
# DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json
# DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json
# DRAMSys/library/resources/configs/memspecs/memspec_ranktest.json
# DRAMSys/library/resources/configs/simulator/ddr3.json
# DRAMSys/library/resources/configs/simulator/ddr3_ecc.json
# DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.json
# DRAMSys/library/resources/configs/simulator/ddr4.json
# DRAMSys/library/resources/configs/simulator/hbm2.json
# DRAMSys/library/resources/configs/simulator/lpddr4.json
# DRAMSys/library/resources/configs/simulator/wideio.json
# DRAMSys/library/resources/configs/simulator/wideio_ecc.json
# DRAMSys/library/resources/configs/simulator/wideio_thermal.json
# DRAMSys/library/src/common/TlmRecorder.cpp
# DRAMSys/library/src/common/utils.cpp
# DRAMSys/library/src/common/utils.h
# DRAMSys/library/src/configuration/Configuration.cpp
# DRAMSys/library/src/configuration/memspec/MemSpec.cpp
# DRAMSys/library/src/configuration/memspec/MemSpec.h
# DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp
# DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp
# DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp
# DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp
# DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp
# DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp
# DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp
# DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp
# DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp
# DRAMSys/library/src/controller/Controller.cpp
# DRAMSys/library/src/controller/ControllerRecordable.cpp
# DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp
# DRAMSys/library/src/simulation/Arbiter.cpp
# DRAMSys/library/src/simulation/DRAMSys.cpp
# DRAMSys/library/src/simulation/DRAMSysRecordable.cpp
# DRAMSys/library/src/simulation/Setup.h
# DRAMSys/library/src/simulation/dram/DramRecordable.cpp
# DRAMSys/pct/createPlatform.tcl
# DRAMSys/simulator/CMakeLists.txt
# DRAMSys/tests/DDR3/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml
# DRAMSys/tests/DDR3/configs/mcconfigs/fifoStrict.xml
# DRAMSys/tests/DDR3/configs/mcconfigs/fr_fcfs.xml
# DRAMSys/tests/DDR4/configs/simulator/ddr4.json
# DRAMSys/tests/ddr3_multirank/configs/simulator/ddr3.json
# DRAMSys/tests/lpddr4/configs/amconfigs/am_lpddr4_8Gbx16_brc.json
# README.md
|
2020-07-06 17:39:23 +02:00 |
|
Lukas Steiner
|
f0a5f07345
|
Rename TUK, add missing disclaimers.
|
2020-07-03 14:20:48 +02:00 |
|
Lukas Steiner
|
6383a1fce5
|
Revert "Merge branch 'opensource_splitting' into 'master'"
This reverts merge request !251
|
2020-06-05 16:26:29 +02:00 |
|
Lukas Steiner
|
8cabd35b2a
|
Code formatting.
|
2020-05-26 21:56:25 +02:00 |
|
Lukas Steiner
|
48a5f66450
|
Updated remaining timing checkers.
|
2020-05-26 11:35:30 +02:00 |
|
Lukas Steiner
|
e193fb3f74
|
Updated DDR3, DDR4, WIO1, WIO2.
|
2020-05-20 17:16:00 +02:00 |
|
Lukas Steiner
|
b75126f207
|
clk to tCK.
|
2020-03-31 11:33:31 +02:00 |
|
Lukas Steiner
|
42f38b5789
|
Changed RDA/WRA command execution times to correct values.
|
2020-03-31 10:19:57 +02:00 |
|
Lukas Steiner
|
6c590a298f
|
Renaming and minor changes in the memspec.
|
2020-03-30 15:34:28 +02:00 |
|
Lukas Steiner
|
234088c529
|
Moved from relative to absolute times in controller.
|
2020-03-24 16:51:13 +01:00 |
|
Lukas Steiner
|
400846505f
|
Bugfix for the creation of debug messages.
|
2020-03-19 15:06:57 +01:00 |
|
Lukas Steiner (2)
|
e970ad194e
|
Correction of timing dependency WR -<> RDA.
|
2019-10-17 15:47:27 +02:00 |
|
Lukas Steiner (2)
|
932027112e
|
Adapted timing checkers of DDR4 and WideIO to new refresh.
|
2019-10-07 15:37:23 +02:00 |
|
Lukas Steiner
|
aa6a205872
|
Implemented first version of flexible refresh (only REFA).
|
2019-10-04 21:46:29 +02:00 |
|
Lukas Steiner (2)
|
cfbce483bd
|
Included timing checker for DDR4.
|
2019-09-24 15:18:37 +02:00 |
|