Changed RDA/WRA command execution times to correct values.
This commit is contained in:
@@ -224,6 +224,8 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec
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XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
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memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz");
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memSpec->clk = sc_time(1.0 / memSpec->clkMHz, SC_US);
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memSpec->burstDuration = memSpec->clk * (memSpec->burstLength / memSpec->dataRate);
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}
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void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec)
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@@ -57,16 +57,6 @@ const std::vector<Bank> &MemSpec::getBanks() const
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return banks;
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}
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sc_time MemSpec::getReadAccessTime() const
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{
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return clk * (burstLength / dataRate);
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}
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sc_time MemSpec::getWriteAccessTime() const
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{
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return clk * (burstLength / dataRate);
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}
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sc_time MemSpec::getCommandLength(Command command) const
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{
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return clk * commandLengthInCycles[command];
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@@ -53,9 +53,6 @@ struct MemSpec
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const std::vector<Bank> &getBanks() const;
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sc_time getWriteAccessTime() const;
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sc_time getReadAccessTime() const;
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virtual sc_time getRefreshIntervalAB() const = 0;
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virtual sc_time getRefreshIntervalPB() const = 0;
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@@ -84,6 +81,8 @@ struct MemSpec
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double clkMHz;
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sc_time clk;
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sc_time burstDuration;
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// Command lengths on bus, usually one clock cycle
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std::vector<unsigned> commandLengthInCycles;
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};
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@@ -54,13 +54,13 @@ sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload
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else if (command == Command::ACT)
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return tRCD;
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else if (command == Command::RD)
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return tRL + getReadAccessTime();
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return tRL + burstDuration;
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else if (command == Command::RDA)
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return tRL + getReadAccessTime();
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return tRTP + tRP;
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else if (command == Command::WR)
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return tWL + getWriteAccessTime();
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return tWL + burstDuration;
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else if (command == Command::WRA)
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return tWL + getWriteAccessTime();
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return tWL + burstDuration + tWR + tRP;
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else if (command == Command::REFA)
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return tRFC;
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else
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@@ -74,9 +74,9 @@ sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload
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TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command) const
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{
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if (command == Command::RD || command == Command::RDA)
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return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + getReadAccessTime());
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return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + burstDuration);
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else if (command == Command::WR || command == Command::WRA)
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return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + getWriteAccessTime());
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return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + burstDuration);
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else
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{
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SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
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@@ -53,10 +53,14 @@ sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload
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return tRP;
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else if (command == Command::ACT)
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return tRCD;
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else if (command == Command::RD || command == Command::RDA)
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return tRL + getReadAccessTime();
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else if (command == Command::WR || command == Command::WRA)
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return tWL + getWriteAccessTime();
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else if (command == Command::RD)
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return tRL + burstDuration;
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else if (command == Command::RDA)
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return tRTP + tRP;
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else if (command == Command::WR)
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return tWL + burstDuration;
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else if (command == Command::WRA)
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return tWL + burstDuration + tWR + tRP;
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else if (command == Command::REFA)
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return tRFC;
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else
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@@ -70,9 +74,9 @@ sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload
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TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command) const
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{
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if (command == Command::RD || command == Command::RDA)
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return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + getReadAccessTime());
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return TimeInterval(sc_time_stamp() + tRL, sc_time_stamp() + tRL + burstDuration);
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else if (command == Command::WR || command == Command::WRA)
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return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + getWriteAccessTime());
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return TimeInterval(sc_time_stamp() + tWL, sc_time_stamp() + tWL + burstDuration);
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else
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{
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SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
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@@ -52,14 +52,18 @@ sc_time MemSpecGDDR5::getExecutionTime(Command command, const tlm_generic_payloa
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else if (command == Command::ACT)
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{
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if (payload.get_command() == TLM_READ_COMMAND)
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return tRCDRD + clk;
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return tRCDRD;
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else
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return tRCDWR + clk;
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return tRCDWR;
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}
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else if (command == Command::RD || command == Command::RDA)
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return tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + getReadAccessTime();
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else if (command == Command::WR || command == Command::WRA)
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return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + getWriteAccessTime();
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else if (command == Command::RD)
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return tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration;
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else if (command == Command::RDA)
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return tRTP + tRP;
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else if (command == Command::WR)
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return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration;
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else if (command == Command::WRA)
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return tWL + burstDuration + tWR + tRP;
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else if (command == Command::REFA)
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return tRFC;
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else if (command == Command::REFB)
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@@ -76,10 +80,10 @@ TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command) const
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{
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if (command == Command::RD || command == Command::RDA)
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return TimeInterval(sc_time_stamp() + tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO,
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sc_time_stamp() + tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + getReadAccessTime());
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sc_time_stamp() + tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration);
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else if (command == Command::WR || command == Command::WRA)
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return TimeInterval(sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI,
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sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + getWriteAccessTime());
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sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration);
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else
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{
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SC_REPORT_FATAL("MemSpecGDDR5", "Method was called with invalid argument");
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@@ -52,14 +52,18 @@ sc_time MemSpecGDDR5X::getExecutionTime(Command command, const tlm_generic_paylo
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else if (command == Command::ACT)
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{
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if (payload.get_command() == TLM_READ_COMMAND)
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return tRCDRD + clk;
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return tRCDRD;
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else
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return tRCDWR + clk;
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return tRCDWR;
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}
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else if (command == Command::RD || command == Command::RDA)
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return tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + getReadAccessTime();
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else if (command == Command::WR || command == Command::WRA)
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return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + getWriteAccessTime();
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else if (command == Command::RD)
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return tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration;
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else if (command == Command::RDA)
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return tRTP + tRP;
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else if (command == Command::WR)
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return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration;
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else if (command == Command::WRA)
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return tWL + burstDuration + tWR + tRP;
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else if (command == Command::REFA)
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return tRFC;
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else if (command == Command::REFB)
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@@ -76,10 +80,10 @@ TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command) const
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{
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if (command == Command::RD || command == Command::RDA)
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return TimeInterval(sc_time_stamp() + tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO,
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sc_time_stamp() + tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + getReadAccessTime());
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sc_time_stamp() + tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration);
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else if (command == Command::WR || command == Command::WRA)
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return TimeInterval(sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI,
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sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + getWriteAccessTime());
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sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration);
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else
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{
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SC_REPORT_FATAL("MemSpecGDDR5X", "Method was called with invalid argument");
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@@ -56,10 +56,14 @@ sc_time MemSpecGDDR6::getExecutionTime(Command command, const tlm_generic_payloa
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else
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return tRCDWR + clk;
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}
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else if (command == Command::RD || command == Command::RDA)
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return tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + getReadAccessTime();
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else if (command == Command::WR || command == Command::WRA)
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return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + getWriteAccessTime();
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else if (command == Command::RD)
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return tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration;
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else if (command == Command::RDA)
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return tRTP + tRP;
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else if (command == Command::WR)
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return tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration;
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else if (command == Command::WRA)
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return tWL + burstDuration + tWR + tRP;
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else if (command == Command::REFA)
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return tRFC;
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else if (command == Command::REFB)
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@@ -76,10 +80,10 @@ TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command) const
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{
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if (command == Command::RD || command == Command::RDA)
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return TimeInterval(sc_time_stamp() + tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO,
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sc_time_stamp() + tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + getReadAccessTime());
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sc_time_stamp() + tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration);
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else if (command == Command::WR || command == Command::WRA)
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return TimeInterval(sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI,
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sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + getWriteAccessTime());
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sc_time_stamp() + tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration);
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else
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{
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SC_REPORT_FATAL("MemSpecGDDR6", "Method was called with invalid argument");
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@@ -61,10 +61,14 @@ sc_time MemSpecHBM2::getExecutionTime(Command command, const tlm_generic_payload
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else
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return tRCDWR + clk;
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}
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else if (command == Command::RD || command == Command::RDA)
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return tRL + tDQSCK + getReadAccessTime();
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else if (command == Command::WR || command == Command::WRA)
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return tWL + getWriteAccessTime();
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else if (command == Command::RD)
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return tRL + tDQSCK + burstDuration;
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else if (command == Command::RDA)
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return tRTP + tRP;
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else if (command == Command::WR)
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return tWL + burstDuration;
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else if (command == Command::WRA)
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return tWL + burstDuration + tWR + tRP;
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else if (command == Command::REFA)
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return tRFC;
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else if (command == Command::REFB)
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@@ -81,10 +85,10 @@ TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command) const
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{
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if (command == Command::RD || command == Command::RDA)
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return TimeInterval(sc_time_stamp() + tRL + tDQSCK,
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sc_time_stamp() + tRL + tDQSCK + getReadAccessTime());
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sc_time_stamp() + tRL + tDQSCK + burstDuration);
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else if (command == Command::WR || command == Command::WRA)
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return TimeInterval(sc_time_stamp() + tWL,
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sc_time_stamp() + tWL + getWriteAccessTime());
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sc_time_stamp() + tWL + burstDuration);
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else
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{
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SC_REPORT_FATAL("MemSpecHBM2", "Method was called with invalid argument");
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@@ -68,10 +68,14 @@ sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_paylo
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return tRPab + clk;
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else if (command == Command::ACT)
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return tRCD + 3 * clk;
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else if (command == Command::RD || command == Command::RDA)
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return tRL + tDQSCK + getReadAccessTime() + 3 * clk;
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else if (command == Command::WR || command == Command::WRA)
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return tWL + tDQSS + tDQS2DQ + getWriteAccessTime() + 3 * clk;
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else if (command == Command::RD)
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return tRL + tDQSCK + burstDuration + 3 * clk;
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else if (command == Command::RDA)
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return burstDuration + tRTP - 5 * clk + tRPpb;
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else if (command == Command::WR)
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return tWL + tDQSS + tDQS2DQ + burstDuration + 3 * clk;
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else if (command == Command::WRA)
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return tWL + 4 * clk + burstDuration + tWR + tRPpb;
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else if (command == Command::REFA)
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return tRFCab + clk;
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else if (command == Command::REFB)
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@@ -88,10 +92,10 @@ TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command) const
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{
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if (command == Command::RD || command == Command::RDA)
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return TimeInterval(sc_time_stamp() + tRL + tDQSCK + 3 * clk,
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sc_time_stamp() + tRL + tDQSCK + getReadAccessTime() + 3 * clk);
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sc_time_stamp() + tRL + tDQSCK + burstDuration + 3 * clk);
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else if (command == Command::WR || command == Command::WRA)
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return TimeInterval(sc_time_stamp() + tWL + tDQSS + tDQS2DQ + 3 * clk,
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sc_time_stamp() + tWL + tDQSS + tDQS2DQ + getWriteAccessTime() + 3 * clk);
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sc_time_stamp() + tWL + tDQSS + tDQS2DQ + burstDuration + 3 * clk);
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else
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{
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SC_REPORT_FATAL("MemSpecLPDDR4", "Method was called with invalid argument");
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@@ -53,10 +53,14 @@ sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_paylo
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return tRP;
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else if (command == Command::ACT)
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return tRCD;
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else if (command == Command::RD || command == Command::RDA)
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return tRL + tAC + getReadAccessTime();
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else if (command == Command::WR || command == Command::WRA)
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return tWL + getWriteAccessTime();
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else if (command == Command::RD)
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return tRL + tAC + burstDuration;
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else if (command == Command::RDA)
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return burstDuration + tRP;
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else if (command == Command::WR)
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return tWL + burstDuration;
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else if (command == Command::WRA)
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return tWL + burstDuration - clk + tWR + tRP;
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else if (command == Command::REFA)
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return tRFC;
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else
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@@ -71,10 +75,10 @@ TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command) const
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{
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if (command == Command::RD || command == Command::RDA)
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return TimeInterval(sc_time_stamp() + tRL + tAC,
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sc_time_stamp() + tRL + tAC + getReadAccessTime());
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sc_time_stamp() + tRL + tAC + burstDuration);
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else if (command == Command::WR || command == Command::WRA)
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return TimeInterval(sc_time_stamp() + tWL,
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sc_time_stamp() + tWL + getWriteAccessTime());
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sc_time_stamp() + tWL + burstDuration);
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else
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{
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SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
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@@ -54,10 +54,14 @@ sc_time MemSpecWideIO2::getExecutionTime(Command command, const tlm_generic_payl
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return tRPab;
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else if (command == Command::ACT)
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return tRCD;
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else if (command == Command::RD || command == Command::RDA)
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return tRL + tDQSCK + getReadAccessTime();
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else if (command == Command::WR || command == Command::WRA)
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return tWL + tDQSS + getWriteAccessTime();
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else if (command == Command::RD)
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return tRL + tDQSCK + burstDuration;
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else if (command == Command::RDA)
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return burstDuration - 2 * clk + tRTP + tRPpb;
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else if (command == Command::WR)
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return tWL + tDQSS + burstDuration;
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else if (command == Command::WRA)
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return tWL + burstDuration + clk + tWR + tRPpb;
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else if (command == Command::REFA)
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return tRFCab;
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else if (command == Command::REFB)
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@@ -74,10 +78,10 @@ TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command) const
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{
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if (command == Command::RD || command == Command::RDA)
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return TimeInterval(sc_time_stamp() + tRL + tDQSCK,
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sc_time_stamp() + tRL + tDQSCK + getReadAccessTime());
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sc_time_stamp() + tRL + tDQSCK + burstDuration);
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else if (command == Command::WR || command == Command::WRA)
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return TimeInterval(sc_time_stamp() + tWL + tDQSS,
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sc_time_stamp() + tWL + tDQSS + getWriteAccessTime());
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sc_time_stamp() + tWL + tDQSS + burstDuration);
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else
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{
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SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
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@@ -48,8 +48,6 @@ CheckerDDR3::CheckerDDR3()
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lastScheduledByCommand = std::vector<sc_time>(numberOfCommands());
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lastActivates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
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burstClocks = (memSpec->burstLength / memSpec->dataRate) * memSpec->clk;
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}
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sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const
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@@ -66,7 +64,7 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGr
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lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
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if (lastCommandStart != SC_ZERO_TIME)
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earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -123,20 +121,20 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
lastCommandStart = lastScheduledByCommand[Command::WR];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWTR);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWTR);
|
||||
|
||||
if (command == Command::RDA)
|
||||
{
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR - memSpec->tRTP);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR - memSpec->tRTP);
|
||||
}
|
||||
|
||||
lastCommandStart = lastScheduledByCommand[Command::WRA];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWTR);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWTR);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -154,12 +152,12 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
lastCommandStart = lastScheduledByCommand[Command::RD];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tRL + burstClocks + 2 * memSpec->clk - memSpec->tWL);
|
||||
+ memSpec->tRL + memSpec->burstDuration + 2 * memSpec->clk - memSpec->tWL);
|
||||
|
||||
lastCommandStart = lastScheduledByCommand[Command::RDA];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tRL + burstClocks + 2 * memSpec->clk - memSpec->tWL);
|
||||
+ memSpec->tRL + memSpec->burstDuration + 2 * memSpec->clk - memSpec->tWL);
|
||||
|
||||
lastCommandStart = lastScheduledByCommand[Command::WR];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -189,7 +187,7 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -211,12 +209,12 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -235,7 +233,7 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -330,7 +328,7 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ std::max(memSpec->tWL + 5 * memSpec->clk + memSpec->tWR, memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP));
|
||||
+ std::max(memSpec->tWL + 5 * memSpec->clk + memSpec->tWR, memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP));
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
|
||||
@@ -58,8 +58,6 @@ private:
|
||||
|
||||
// Four activate window
|
||||
std::vector<std::queue<sc_time>> lastActivates;
|
||||
|
||||
sc_time burstClocks;
|
||||
};
|
||||
|
||||
#endif // CHECKERDDR3_H
|
||||
|
||||
@@ -50,8 +50,6 @@ CheckerDDR4::CheckerDDR4()
|
||||
lastScheduledByCommand = std::vector<sc_time>(numberOfCommands());
|
||||
|
||||
lastActivates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
|
||||
|
||||
burstClocks = (memSpec->burstLength / memSpec->dataRate) * memSpec->clk;
|
||||
}
|
||||
|
||||
sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const
|
||||
@@ -68,7 +66,7 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
|
||||
+ burstClocks + memSpec->tWR + memSpec->tRP);
|
||||
+ memSpec->burstDuration + memSpec->tWR + memSpec->tRP);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -121,30 +119,30 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
|
||||
+ burstClocks + memSpec->tWTR_L);
|
||||
+ memSpec->burstDuration + memSpec->tWTR_L);
|
||||
|
||||
if (command == Command::RDA)
|
||||
{
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR - memSpec->tRTP);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR - memSpec->tRTP);
|
||||
}
|
||||
|
||||
lastCommandStart = lastScheduledByCommand[Command::WR];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
|
||||
+ burstClocks + memSpec->tWTR_S);
|
||||
+ memSpec->burstDuration + memSpec->tWTR_S);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
|
||||
+ burstClocks + memSpec->tWTR_L);
|
||||
+ memSpec->burstDuration + memSpec->tWTR_L);
|
||||
|
||||
lastCommandStart = lastScheduledByCommand[Command::WRA];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
|
||||
+ burstClocks + memSpec->tWTR_S);
|
||||
+ memSpec->burstDuration + memSpec->tWTR_S);
|
||||
}
|
||||
else if (command == Command::WR || command == Command::WRA)
|
||||
{
|
||||
@@ -154,12 +152,12 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
lastCommandStart = lastScheduledByCommand[Command::RD];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL
|
||||
+ burstClocks + 2 * memSpec->clk - memSpec->tWL);
|
||||
+ memSpec->burstDuration + 2 * memSpec->clk - memSpec->tWL);
|
||||
|
||||
lastCommandStart = lastScheduledByCommand[Command::RDA];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL
|
||||
+ burstClocks + 2 * memSpec->clk - memSpec->tWL);
|
||||
+ memSpec->burstDuration + 2 * memSpec->clk - memSpec->tWL);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -189,7 +187,7 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
|
||||
+ burstClocks + memSpec->tWR);
|
||||
+ memSpec->burstDuration + memSpec->tWR);
|
||||
}
|
||||
else if (command == Command::PREA)
|
||||
{
|
||||
@@ -207,12 +205,12 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
|
||||
+ burstClocks + memSpec->tWR);
|
||||
+ memSpec->burstDuration + memSpec->tWR);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
|
||||
+ burstClocks + memSpec->tWR);
|
||||
+ memSpec->burstDuration + memSpec->tWR);
|
||||
}
|
||||
else if (command == Command::REFA)
|
||||
{
|
||||
@@ -227,7 +225,7 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
|
||||
+ burstClocks + memSpec->tWR + memSpec->tRP);
|
||||
+ memSpec->burstDuration + memSpec->tWR + memSpec->tRP);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
|
||||
@@ -59,8 +59,6 @@ private:
|
||||
|
||||
// Four activate window
|
||||
std::vector<std::queue<sc_time>> lastActivates;
|
||||
|
||||
sc_time burstClocks;
|
||||
};
|
||||
|
||||
#endif // CHECKERDDR4_H
|
||||
|
||||
@@ -51,8 +51,6 @@ CheckerGDDR5::CheckerGDDR5()
|
||||
|
||||
last4Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
|
||||
last32Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
|
||||
|
||||
burstClocks = (memSpec->burstLength / memSpec->dataRate) * memSpec->clk;
|
||||
}
|
||||
|
||||
sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const
|
||||
@@ -81,7 +79,7 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankG
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -133,30 +131,30 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankG
|
||||
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWTRL);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWTRL);
|
||||
|
||||
if (command == Command::RDA)
|
||||
{
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR - memSpec->tRTP);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR - memSpec->tRTP);
|
||||
}
|
||||
|
||||
lastCommandStart = lastScheduledByCommand[Command::WR];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWTRS);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWTRS);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWTRL);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWTRL);
|
||||
|
||||
lastCommandStart = lastScheduledByCommand[Command::WRA];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWTRS);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWTRS);
|
||||
}
|
||||
else if (command == Command::WR || command == Command::WRA)
|
||||
{
|
||||
@@ -199,7 +197,7 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankG
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -221,12 +219,12 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankG
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -245,7 +243,7 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankG
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -280,7 +278,7 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankG
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
|
||||
@@ -61,8 +61,6 @@ private:
|
||||
std::vector<std::queue<sc_time>> last4Activates;
|
||||
std::vector<std::queue<sc_time>> last32Activates;
|
||||
|
||||
sc_time burstClocks;
|
||||
|
||||
unsigned bankwiseRefreshCounter = 0;
|
||||
};
|
||||
|
||||
|
||||
@@ -51,8 +51,6 @@ CheckerGDDR5X::CheckerGDDR5X()
|
||||
|
||||
last4Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
|
||||
last32Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
|
||||
|
||||
burstClocks = (memSpec->burstLength / memSpec->dataRate) * memSpec->clk;
|
||||
}
|
||||
|
||||
sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const
|
||||
@@ -81,7 +79,7 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, Bank
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -133,30 +131,30 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, Bank
|
||||
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWTRL);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWTRL);
|
||||
|
||||
if (command == Command::RDA)
|
||||
{
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR - memSpec->tRTP);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR - memSpec->tRTP);
|
||||
}
|
||||
|
||||
lastCommandStart = lastScheduledByCommand[Command::WR];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWTRS);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWTRS);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWTRL);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWTRL);
|
||||
|
||||
lastCommandStart = lastScheduledByCommand[Command::WRA];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWTRS);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWTRS);
|
||||
}
|
||||
else if (command == Command::WR || command == Command::WRA)
|
||||
{
|
||||
@@ -199,7 +197,7 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, Bank
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -221,12 +219,12 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, Bank
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -245,7 +243,7 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, Bank
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -280,7 +278,7 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, Bank
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
|
||||
@@ -61,8 +61,6 @@ private:
|
||||
std::vector<std::queue<sc_time>> last4Activates;
|
||||
std::vector<std::queue<sc_time>> last32Activates;
|
||||
|
||||
sc_time burstClocks;
|
||||
|
||||
unsigned bankwiseRefreshCounter = 0;
|
||||
};
|
||||
|
||||
|
||||
@@ -50,8 +50,6 @@ CheckerGDDR6::CheckerGDDR6()
|
||||
lastScheduledByCommand = std::vector<sc_time>(numberOfCommands());
|
||||
|
||||
lastActivates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
|
||||
|
||||
burstClocks = (memSpec->burstLength / memSpec->dataRate) * memSpec->clk;
|
||||
}
|
||||
|
||||
sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const
|
||||
@@ -80,7 +78,7 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankG
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -129,30 +127,30 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankG
|
||||
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWTRL);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWTRL);
|
||||
|
||||
if (command == Command::RDA)
|
||||
{
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR - memSpec->tRTP);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR - memSpec->tRTP);
|
||||
}
|
||||
|
||||
lastCommandStart = lastScheduledByCommand[Command::WR];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWTRS);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWTRS);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWTRL);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWTRL);
|
||||
|
||||
lastCommandStart = lastScheduledByCommand[Command::WRA];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWTRS);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWTRS);
|
||||
}
|
||||
else if (command == Command::WR || command == Command::WRA)
|
||||
{
|
||||
@@ -195,7 +193,7 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankG
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -217,12 +215,12 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankG
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -241,7 +239,7 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankG
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -276,7 +274,7 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankG
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
|
||||
@@ -60,8 +60,6 @@ private:
|
||||
// four activate window
|
||||
std::vector<std::queue<sc_time>> lastActivates;
|
||||
|
||||
sc_time burstClocks;
|
||||
|
||||
unsigned bankwiseRefreshCounter = 0;
|
||||
};
|
||||
|
||||
|
||||
@@ -51,8 +51,6 @@ CheckerHBM2::CheckerHBM2()
|
||||
|
||||
lastActivates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
|
||||
bankwiseRefreshCounter = std::vector<unsigned>(memSpec->numberOfRanks);
|
||||
|
||||
burstClocks = (memSpec->burstLength / 2) * memSpec->clk;
|
||||
}
|
||||
|
||||
sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const
|
||||
@@ -82,7 +80,7 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP - memSpec->clk);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP - memSpec->clk);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -108,7 +106,7 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
earliestTimeToStart = std::max(earliestTimeToStart,
|
||||
lastActivates[rank.ID()].front() + memSpec->tFAW - memSpec->clk);
|
||||
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRASBus + memSpec->clk);
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->clk);
|
||||
}
|
||||
else if (command == Command::RD || command == Command::RDA)
|
||||
{
|
||||
@@ -134,32 +132,32 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWTRL);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWTRL);
|
||||
|
||||
if (command == Command::RDA)
|
||||
{
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR - memSpec->tRTP);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR - memSpec->tRTP);
|
||||
}
|
||||
|
||||
lastCommandStart = lastScheduledByCommand[Command::WR];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWTRS);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWTRS);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWTRL);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWTRL);
|
||||
|
||||
lastCommandStart = lastScheduledByCommand[Command::WRA];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWTRS);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWTRS);
|
||||
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCASBus + memSpec->clk);
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCasBus + memSpec->clk);
|
||||
}
|
||||
else if (command == Command::WR || command == Command::WRA)
|
||||
{
|
||||
@@ -190,7 +188,7 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS);
|
||||
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCASBus + memSpec->clk);
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCasBus + memSpec->clk);
|
||||
}
|
||||
else if (command == Command::PRE)
|
||||
{
|
||||
@@ -204,9 +202,9 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR);
|
||||
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRASBus + memSpec->clk);
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->clk);
|
||||
}
|
||||
else if (command == Command::PREA)
|
||||
{
|
||||
@@ -224,14 +222,14 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR);
|
||||
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRASBus + memSpec->clk);
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->clk);
|
||||
}
|
||||
else if (command == Command::REFA)
|
||||
{
|
||||
@@ -246,7 +244,7 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -260,7 +258,7 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC);
|
||||
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRASBus + memSpec->clk);
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->clk);
|
||||
}
|
||||
else if (command == Command::REFB)
|
||||
{
|
||||
@@ -283,7 +281,7 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks + memSpec->tWR + memSpec->tRP);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -305,7 +303,7 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr
|
||||
if (lastActivates[rank.ID()].size() == 4)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW);
|
||||
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRASBus + memSpec->clk);
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->clk);
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -326,17 +324,17 @@ void CheckerHBM2::insert(Command command, Rank rank, BankGroup bankgroup, Bank b
|
||||
lastScheduledByCommand[command] = sc_time_stamp();
|
||||
|
||||
if (isCasCommand(command))
|
||||
lastCommandOnCASBus = sc_time_stamp();
|
||||
lastCommandOnCasBus = sc_time_stamp();
|
||||
else if (command == Command::ACT)
|
||||
lastCommandOnRASBus = sc_time_stamp() + memSpec->clk;
|
||||
lastCommandOnRasBus = sc_time_stamp() + memSpec->clk;
|
||||
else
|
||||
lastCommandOnRASBus = sc_time_stamp();
|
||||
lastCommandOnRasBus = sc_time_stamp();
|
||||
|
||||
if (command == Command::ACT || command == Command::REFB)
|
||||
{
|
||||
if (lastActivates[rank.ID()].size() == 4)
|
||||
lastActivates[rank.ID()].pop();
|
||||
lastActivates[rank.ID()].push(lastCommandOnRASBus);
|
||||
lastActivates[rank.ID()].push(lastCommandOnRasBus);
|
||||
}
|
||||
|
||||
if (command == Command::REFB)
|
||||
|
||||
@@ -55,14 +55,12 @@ private:
|
||||
std::vector<std::vector<sc_time>> lastScheduledByCommandAndBankGroup;
|
||||
std::vector<std::vector<sc_time>> lastScheduledByCommandAndRank;
|
||||
std::vector<sc_time> lastScheduledByCommand;
|
||||
sc_time lastCommandOnRASBus;
|
||||
sc_time lastCommandOnCASBus;
|
||||
sc_time lastCommandOnRasBus;
|
||||
sc_time lastCommandOnCasBus;
|
||||
|
||||
// Four activate window
|
||||
std::vector<std::queue<sc_time>> lastActivates;
|
||||
std::vector<unsigned> bankwiseRefreshCounter;
|
||||
|
||||
sc_time burstClocks;
|
||||
};
|
||||
|
||||
#endif // CHECKERHBM2_H
|
||||
|
||||
@@ -63,7 +63,7 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, Bank
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->burstDuration
|
||||
+ memSpec->tWR + memSpec->clk + memSpec->tRPpb);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()];
|
||||
@@ -112,19 +112,19 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, Bank
|
||||
|
||||
lastCommandStart = lastScheduledByCommand[Command::WR];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->clk + memSpec->tCCD + memSpec->tWTR);
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->clk + memSpec->burstDuration + memSpec->tWTR);
|
||||
|
||||
if (command == Command::RDA)
|
||||
{
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + memSpec->clk + memSpec->tCCD + memSpec->tWR - memSpec->tRTP);
|
||||
+ memSpec->tWL + memSpec->clk + memSpec->burstDuration + memSpec->tWR - memSpec->tRTP);
|
||||
}
|
||||
|
||||
lastCommandStart = lastScheduledByCommand[Command::WRA];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->clk + memSpec->tCCD + memSpec->tWTR);
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->clk + memSpec->burstDuration + memSpec->tWTR);
|
||||
}
|
||||
else if (command == Command::WR || command == Command::WRA)
|
||||
{
|
||||
@@ -133,11 +133,11 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, Bank
|
||||
|
||||
lastCommandStart = lastScheduledByCommand[Command::RD];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL + memSpec->tDQSCK + memSpec->tCCD - memSpec->tWL + memSpec->tWPRE + memSpec->tRPST);
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL + memSpec->tDQSCK + memSpec->burstDuration - memSpec->tWL + memSpec->tWPRE + memSpec->tRPST);
|
||||
|
||||
lastCommandStart = lastScheduledByCommand[Command::RDA];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL + memSpec->tDQSCK + memSpec->tCCD - memSpec->tWL + memSpec->tWPRE + memSpec->tRPST);
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL + memSpec->tDQSCK + memSpec->burstDuration - memSpec->tWL + memSpec->tWPRE + memSpec->tRPST);
|
||||
|
||||
lastCommandStart = lastScheduledByCommand[Command::WR];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -154,11 +154,11 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, Bank
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD + memSpec->tRTP - 6 * memSpec->clk);
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration + memSpec->tRTP - 6 * memSpec->clk);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD + memSpec->tWR + 3 * memSpec->clk);
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + 3 * memSpec->clk);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -171,19 +171,19 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, Bank
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD + memSpec->tRTP - 6 * memSpec->clk);
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration + memSpec->tRTP - 6 * memSpec->clk);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD + memSpec->tRTP - 6 * memSpec->clk);
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration + memSpec->tRTP - 6 * memSpec->clk);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD + memSpec->tWR + 3 * memSpec->clk);
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + 3 * memSpec->clk);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD + memSpec->tWR + 3 * memSpec->clk);
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + 3 * memSpec->clk);
|
||||
|
||||
// lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()];
|
||||
// if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -205,7 +205,7 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, Bank
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->burstDuration
|
||||
+ memSpec->tWR + 3 * memSpec->clk + memSpec->tRPpb);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()];
|
||||
@@ -240,7 +240,7 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, Bank
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCCD
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->burstDuration
|
||||
+ memSpec->tWR + 3 * memSpec->clk + memSpec->tRPpb);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()];
|
||||
|
||||
@@ -48,8 +48,6 @@ CheckerWideIO::CheckerWideIO()
|
||||
lastScheduledByCommand = std::vector<sc_time>(numberOfCommands());
|
||||
|
||||
lastActivates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
|
||||
|
||||
burstClocks = memSpec->burstLength * memSpec->clk;
|
||||
}
|
||||
|
||||
sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const
|
||||
@@ -61,12 +59,12 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, Bank
|
||||
{
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + burstClocks + memSpec->tRP);
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration + memSpec->tRP);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
|
||||
+ burstClocks - memSpec->clk + memSpec->tWR + memSpec->tRP);
|
||||
+ memSpec->burstDuration - memSpec->clk + memSpec->tWR + memSpec->tRP);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -98,16 +96,16 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, Bank
|
||||
|
||||
lastCommandStart = lastScheduledByCommand[Command::RD];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + burstClocks);
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration);
|
||||
|
||||
lastCommandStart = lastScheduledByCommand[Command::RDA];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + burstClocks);
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration);
|
||||
|
||||
lastCommandStart = lastScheduledByCommand[Command::WR];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks - memSpec->clk + memSpec->tWTR);
|
||||
+ memSpec->tWL + memSpec->burstDuration - memSpec->clk + memSpec->tWTR);
|
||||
|
||||
if (command == Command::RDA)
|
||||
{
|
||||
@@ -120,7 +118,7 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, Bank
|
||||
lastCommandStart = lastScheduledByCommand[Command::WRA];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks - memSpec->clk + memSpec->tWTR);
|
||||
+ memSpec->tWL + memSpec->burstDuration - memSpec->clk + memSpec->tWTR);
|
||||
}
|
||||
else if (command == Command::WR || command == Command::WRA)
|
||||
{
|
||||
@@ -130,20 +128,20 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, Bank
|
||||
lastCommandStart = lastScheduledByCommand[Command::RD];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tRL + burstClocks + memSpec->clk);
|
||||
+ memSpec->tRL + memSpec->burstDuration + memSpec->clk);
|
||||
|
||||
lastCommandStart = lastScheduledByCommand[Command::RDA];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tRL + burstClocks + memSpec->clk);
|
||||
+ memSpec->tRL + memSpec->burstDuration + memSpec->clk);
|
||||
|
||||
lastCommandStart = lastScheduledByCommand[Command::WR];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + burstClocks);
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration);
|
||||
|
||||
lastCommandStart = lastScheduledByCommand[Command::WRA];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + burstClocks);
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration);
|
||||
}
|
||||
else if (command == Command::PRE)
|
||||
{
|
||||
@@ -152,12 +150,12 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, Bank
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + burstClocks);
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks - memSpec->clk + memSpec->tWR);
|
||||
+ memSpec->tWL + memSpec->burstDuration - memSpec->clk + memSpec->tWR);
|
||||
}
|
||||
else if (command == Command::PREA)
|
||||
{
|
||||
@@ -166,21 +164,21 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, Bank
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + burstClocks);
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + burstClocks);
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks - memSpec->clk + memSpec->tWR);
|
||||
+ memSpec->tWL + memSpec->burstDuration - memSpec->clk + memSpec->tWR);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks - memSpec->clk + memSpec->tWR);
|
||||
+ memSpec->tWL + memSpec->burstDuration - memSpec->clk + memSpec->tWR);
|
||||
}
|
||||
else if (command == Command::REFA)
|
||||
{
|
||||
@@ -190,12 +188,12 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, Bank
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + burstClocks + memSpec->tRP);
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration + memSpec->tRP);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + burstClocks - memSpec->clk + memSpec->tWR + memSpec->tRP);
|
||||
+ memSpec->tWL + memSpec->burstDuration - memSpec->clk + memSpec->tWR + memSpec->tRP);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
|
||||
@@ -58,8 +58,6 @@ private:
|
||||
|
||||
// Four activate window
|
||||
std::vector<std::queue<sc_time>> lastActivates;
|
||||
|
||||
sc_time burstClocks;
|
||||
};
|
||||
|
||||
#endif // CHECKERWIDEIO_H
|
||||
|
||||
@@ -68,12 +68,12 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, Ban
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tCCD + memSpec->tRTP - 2 * memSpec->clk + memSpec->tRPpb);
|
||||
+ memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->clk + memSpec->tRPpb);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->clk + memSpec->tRPpb);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->clk + memSpec->tRPpb);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -114,20 +114,20 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, Ban
|
||||
lastCommandStart = lastScheduledByCommand[Command::WR];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + memSpec->clk + memSpec->tCCD + memSpec->tWTR);
|
||||
+ memSpec->tWL + memSpec->clk + memSpec->burstDuration + memSpec->tWTR);
|
||||
|
||||
if (command == Command::RDA)
|
||||
{
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + memSpec->clk + memSpec->tCCD + memSpec->tWR - memSpec->tRTP);
|
||||
+ memSpec->tWL + memSpec->clk + memSpec->burstDuration + memSpec->tWR - memSpec->tRTP);
|
||||
}
|
||||
|
||||
lastCommandStart = lastScheduledByCommand[Command::WRA];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + memSpec->clk + memSpec->tCCD + memSpec->tWTR);
|
||||
+ memSpec->tWL + memSpec->clk + memSpec->burstDuration + memSpec->tWTR);
|
||||
}
|
||||
else if (command == Command::WR || command == Command::WRA)
|
||||
{
|
||||
@@ -137,12 +137,12 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, Ban
|
||||
lastCommandStart = lastScheduledByCommand[Command::RD];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tRL + memSpec->tDQSCK + memSpec->tCCD + memSpec->clk - memSpec->tWL);
|
||||
+ memSpec->tRL + memSpec->tDQSCK + memSpec->burstDuration + memSpec->clk - memSpec->tWL);
|
||||
|
||||
lastCommandStart = lastScheduledByCommand[Command::RDA];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tRL + memSpec->tDQSCK + memSpec->tCCD + memSpec->clk - memSpec->tWL);
|
||||
+ memSpec->tRL + memSpec->tDQSCK + memSpec->burstDuration + memSpec->clk - memSpec->tWL);
|
||||
|
||||
lastCommandStart = lastScheduledByCommand[Command::WR];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -160,12 +160,12 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, Ban
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tCCD + memSpec->tRTP - 2 * memSpec->clk);
|
||||
+ memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->clk);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->clk);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->clk);
|
||||
}
|
||||
else if (command == Command::PREA)
|
||||
{
|
||||
@@ -175,22 +175,22 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, Ban
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tCCD + memSpec->tRTP - 2 * memSpec->clk);
|
||||
+ memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->clk);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tCCD + memSpec->tRTP - 2 * memSpec->clk);
|
||||
+ memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->clk);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->clk);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->clk);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->clk);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->clk);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -205,12 +205,12 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, Ban
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tCCD + memSpec->tRTP - 2 * memSpec->clk + memSpec->tRPpb);
|
||||
+ memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->clk + memSpec->tRPpb);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->clk + memSpec->tRPpb);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->clk + memSpec->tRPpb);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
@@ -237,12 +237,12 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, Ban
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tCCD + memSpec->tRTP - 2 * memSpec->clk + memSpec->tRPpb);
|
||||
+ memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->clk + memSpec->tRPpb);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
|
||||
+ memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->clk + memSpec->tRPpb);
|
||||
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->clk + memSpec->tRPpb);
|
||||
|
||||
lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()];
|
||||
if (lastCommandStart != SC_ZERO_TIME)
|
||||
|
||||
Reference in New Issue
Block a user