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clk to tCK.

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This commit is contained in:
Lukas Steiner
2020-03-31 11:33:31 +02:00
parent 42f38b5789
commit b75126f207
30 changed files with 525 additions and 541 deletions
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4
DRAMSys/library/src/common/TlmRecorder.cpp
View File

@@ -329,7 +329,7 @@ void TlmRecorder::insertGeneralInfo()
sqlite3_bind_int(insertGeneralInfoStatement, 4,
Configuration::getInstance().memSpec->numberOfBanks);
sqlite3_bind_int(insertGeneralInfoStatement, 5,
Configuration::getInstance().memSpec->clk.value());
Configuration::getInstance().memSpec->tCK.value());
sqlite3_bind_text(insertGeneralInfoStatement, 6, "PS", 2, NULL);
sqlite3_bind_text(insertGeneralInfoStatement, 7, mcconfig.c_str(),
mcconfig.length(), NULL);
@@ -341,7 +341,7 @@ void TlmRecorder::insertGeneralInfo()
sqlite3_bind_int64(insertGeneralInfoStatement, 10, 0);
else
sqlite3_bind_int64(insertGeneralInfoStatement, 10,
(Configuration::getInstance().memSpec->clk *
(Configuration::getInstance().memSpec->tCK *
Configuration::getInstance().windowSize).value());
if ((Configuration::getInstance().refreshMaxPostponed > 0)
|| (Configuration::getInstance().refreshMaxPulledin > 0)) {

539
DRAMSys/library/src/configuration/ConfigurationLoader.cpp
View File

@@ -222,10 +222,10 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec
// Clock
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
memSpec->clkMHz = queryDoubleParameter(timings, "clkMhz");
memSpec->clk = sc_time(1.0 / memSpec->clkMHz, SC_US);
memSpec->fCKMHz = queryDoubleParameter(timings, "clkMhz");
memSpec->tCK = sc_time(1.0 / memSpec->fCKMHz, SC_US);
memSpec->burstDuration = memSpec->clk * (memSpec->burstLength / memSpec->dataRate);
memSpec->burstDuration = memSpec->tCK * (memSpec->burstLength / memSpec->dataRate);
}
void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec)
@@ -245,29 +245,28 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec)
// MemTimings specific for DDR3
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
sc_time clk = memSpec->clk;
memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR");
//memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
memSpec->tRC = clk * queryUIntParameter(timings, "RC");
memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
memSpec->tRL = clk * queryUIntParameter(timings, "RL");
memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
memSpec->tWL = clk * queryUIntParameter(timings, "WL");
memSpec->tWR = clk * queryUIntParameter(timings, "WR");
memSpec->tXP = clk * queryUIntParameter(timings, "XP");
memSpec->tXS = clk * queryUIntParameter(timings, "XS");
memSpec->tCCD = clk * queryUIntParameter(timings, "CCD");
memSpec->tFAW = clk * queryUIntParameter(timings, "FAW");
memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
memSpec->tRP = clk * queryUIntParameter(timings, "RP");
memSpec->tRRD = clk * queryUIntParameter(timings, "RRD");
memSpec->tWTR = clk * queryUIntParameter(timings, "WTR");
memSpec->tAL = clk * queryUIntParameter(timings, "AL");
memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL");
memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL");
memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE");
memSpec->tCKESR = memSpec->tCK * queryUIntParameter(timings, "CKESR");
//memSpec->tDQSCK = memSpec->tCK * queryUIntParameter(timings, "DQSCK");
memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS");
memSpec->tRC = memSpec->tCK * queryUIntParameter(timings, "RC");
memSpec->tRCD = memSpec->tCK * queryUIntParameter(timings, "RCD");
memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL");
memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP");
memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL");
memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR");
memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP");
memSpec->tXS = memSpec->tCK * queryUIntParameter(timings, "XS");
memSpec->tCCD = memSpec->tCK * queryUIntParameter(timings, "CCD");
memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW");
memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI");
memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC");
memSpec->tRP = memSpec->tCK * queryUIntParameter(timings, "RP");
memSpec->tRRD = memSpec->tCK * queryUIntParameter(timings, "RRD");
memSpec->tWTR = memSpec->tCK * queryUIntParameter(timings, "WTR");
memSpec->tAL = memSpec->tCK * queryUIntParameter(timings, "AL");
memSpec->tXPDLL = memSpec->tCK * queryUIntParameter(timings, "XPDLL");
memSpec->tXSDLL = memSpec->tCK * queryUIntParameter(timings, "XSDLL");
// Currents and voltages
XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec");
@@ -302,48 +301,47 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec)
// MemTimings specific for DDR4
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
sc_time clk = memSpec->clk;
memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR");
//memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
memSpec->tRC = clk * queryUIntParameter(timings, "RC");
memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
memSpec->tRL = clk * queryUIntParameter(timings, "RL");
memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
memSpec->tWL = clk * queryUIntParameter(timings, "WL");
memSpec->tWR = clk * queryUIntParameter(timings, "WR");
memSpec->tXP = clk * queryUIntParameter(timings, "XP");
memSpec->tXS = clk * queryUIntParameter(timings, "XS");
memSpec->tCCD_S = clk * queryUIntParameter(timings, "CCD_S");
memSpec->tCCD_L = clk * queryUIntParameter(timings, "CCD_L");
memSpec->tFAW = clk * queryUIntParameter(timings, "FAW");
memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE");
memSpec->tCKESR = memSpec->tCK * queryUIntParameter(timings, "CKESR");
//memSpec->tDQSCK = memSpec->tCK * queryUIntParameter(timings, "DQSCK");
memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS");
memSpec->tRC = memSpec->tCK * queryUIntParameter(timings, "RC");
memSpec->tRCD = memSpec->tCK * queryUIntParameter(timings, "RCD");
memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL");
memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP");
memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL");
memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR");
memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP");
memSpec->tXS = memSpec->tCK * queryUIntParameter(timings, "XS");
memSpec->tCCD_S = memSpec->tCK * queryUIntParameter(timings, "CCD_S");
memSpec->tCCD_L = memSpec->tCK * queryUIntParameter(timings, "CCD_L");
memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW");
unsigned refreshMode = Configuration::getInstance().refreshMode;
if (refreshMode == 1)
{
memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI");
memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC");
}
else if (refreshMode == 2)
{
memSpec->tREFI = clk * (queryUIntParameter(timings, "REFI") / 2);
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC2");
memSpec->tREFI = memSpec->tCK * (queryUIntParameter(timings, "REFI") / 2);
memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC2");
}
else if (refreshMode == 4)
{
memSpec->tREFI = clk * (queryUIntParameter(timings, "REFI") / 2);
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC4");
memSpec->tREFI = memSpec->tCK * (queryUIntParameter(timings, "REFI") / 2);
memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC4");
}
else
SC_REPORT_FATAL("ConfigurationLoader", "Refresh Mode not supported");
memSpec->tRP = clk * queryUIntParameter(timings, "RP");
memSpec->tRRD_S = clk * queryUIntParameter(timings, "RRD_S");
memSpec->tRRD_L = clk * queryUIntParameter(timings, "RRD_L");
memSpec->tWTR_S = clk * queryUIntParameter(timings, "WTR_S");
memSpec->tWTR_L = clk * queryUIntParameter(timings, "WTR_L");
memSpec->tAL = clk * queryUIntParameter(timings, "AL");
memSpec->tXPDLL = clk * queryUIntParameter(timings, "XPDLL");
memSpec->tXSDLL = clk * queryUIntParameter(timings, "XSDLL");
memSpec->tRP = memSpec->tCK * queryUIntParameter(timings, "RP");
memSpec->tRRD_S = memSpec->tCK * queryUIntParameter(timings, "RRD_S");
memSpec->tRRD_L = memSpec->tCK * queryUIntParameter(timings, "RRD_L");
memSpec->tWTR_S = memSpec->tCK * queryUIntParameter(timings, "WTR_S");
memSpec->tWTR_L = memSpec->tCK * queryUIntParameter(timings, "WTR_L");
memSpec->tAL = memSpec->tCK * queryUIntParameter(timings, "AL");
memSpec->tXPDLL = memSpec->tCK * queryUIntParameter(timings, "XPDLL");
memSpec->tXSDLL = memSpec->tCK * queryUIntParameter(timings, "XSDLL");
// Currents and voltages
XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec");
@@ -381,35 +379,34 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec)
// MemTimings specific for LPDDR4
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
sc_time clk = memSpec->clk;
memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
memSpec->tREFIpb = clk * queryUIntParameter(timings, "REFIPB");
memSpec->tRFCab = clk * queryUIntParameter(timings, "RFCAB");
memSpec->tRFCpb = clk * queryUIntParameter(timings, "RFCPB");
memSpec->tRPab = clk * queryUIntParameter(timings, "RPAB");
memSpec->tRPpb = clk * queryUIntParameter(timings, "RPPB");
memSpec->tPPD = clk * queryUIntParameter(timings, "PPD");
memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
memSpec->tFAW = clk * queryUIntParameter(timings, "FAW");
memSpec->tRRD = clk * queryUIntParameter(timings, "RRD");
memSpec->tCCD = clk * queryUIntParameter(timings, "CCD");
memSpec->tRL = clk * queryUIntParameter(timings, "RL");
memSpec->tRPST = clk * queryUIntParameter(timings, "RPST");
memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
memSpec->tWL = clk * queryUIntParameter(timings, "WL");
memSpec->tDQSS = clk * queryUIntParameter(timings, "DQSS");
memSpec->tDQS2DQ = clk * queryUIntParameter(timings, "DQS2DQ");
memSpec->tWR = clk * queryUIntParameter(timings, "WR");
memSpec->tWPRE = clk * queryUIntParameter(timings, "WPRE");
memSpec->tWTR = clk * queryUIntParameter(timings, "WTR");
memSpec->tXP = clk * queryUIntParameter(timings, "XP");
memSpec->tSR = clk * queryUIntParameter(timings, "SR");
memSpec->tXSR = clk * queryUIntParameter(timings, "XSR");
memSpec->tESCKE = clk * queryUIntParameter(timings, "ESCKE");
memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
memSpec->tCMDCKE = clk * queryUIntParameter(timings, "CMDCKE");
memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI");
memSpec->tREFIpb = memSpec->tCK * queryUIntParameter(timings, "REFIPB");
memSpec->tRFCab = memSpec->tCK * queryUIntParameter(timings, "RFCAB");
memSpec->tRFCpb = memSpec->tCK * queryUIntParameter(timings, "RFCPB");
memSpec->tRPab = memSpec->tCK * queryUIntParameter(timings, "RPAB");
memSpec->tRPpb = memSpec->tCK * queryUIntParameter(timings, "RPPB");
memSpec->tPPD = memSpec->tCK * queryUIntParameter(timings, "PPD");
memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS");
memSpec->tRCD = memSpec->tCK * queryUIntParameter(timings, "RCD");
memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW");
memSpec->tRRD = memSpec->tCK * queryUIntParameter(timings, "RRD");
memSpec->tCCD = memSpec->tCK * queryUIntParameter(timings, "CCD");
memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL");
memSpec->tRPST = memSpec->tCK * queryUIntParameter(timings, "RPST");
memSpec->tDQSCK = memSpec->tCK * queryUIntParameter(timings, "DQSCK");
memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP");
memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL");
memSpec->tDQSS = memSpec->tCK * queryUIntParameter(timings, "DQSS");
memSpec->tDQS2DQ = memSpec->tCK * queryUIntParameter(timings, "DQS2DQ");
memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR");
memSpec->tWPRE = memSpec->tCK * queryUIntParameter(timings, "WPRE");
memSpec->tWTR = memSpec->tCK * queryUIntParameter(timings, "WTR");
memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP");
memSpec->tSR = memSpec->tCK * queryUIntParameter(timings, "SR");
memSpec->tXSR = memSpec->tCK * queryUIntParameter(timings, "XSR");
memSpec->tESCKE = memSpec->tCK * queryUIntParameter(timings, "ESCKE");
memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE");
memSpec->tCMDCKE = memSpec->tCK * queryUIntParameter(timings, "CMDCKE");
// Currents and voltages
// TODO: to be completed
@@ -432,27 +429,26 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *xmlSpec)
// MemTimings specific for WideIO
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
sc_time clk = memSpec->clk;
memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR");
memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
memSpec->tAC = clk * queryUIntParameter(timings, "AC");
memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
memSpec->tRC = clk * queryUIntParameter(timings, "RC");
memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
memSpec->tRL = clk * queryUIntParameter(timings, "RL");
memSpec->tWL = clk * queryUIntParameter(timings, "WL");
memSpec->tWR = clk * queryUIntParameter(timings, "WR");
memSpec->tXP = clk * queryUIntParameter(timings, "XP");
memSpec->tXS = clk * queryUIntParameter(timings, "XS");
memSpec->tCCD_R = clk * queryUIntParameter(timings, "CCD_R");
memSpec->tCCD_W = clk * queryUIntParameter(timings, "CCD_W");
memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
memSpec->tRP = clk * queryUIntParameter(timings, "RP");
memSpec->tRRD = clk * queryUIntParameter(timings, "RRD");
memSpec->tTAW = clk * queryUIntParameter(timings, "TAW");
memSpec->tWTR = clk * queryUIntParameter(timings, "WTR");
memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE");
memSpec->tCKESR = memSpec->tCK * queryUIntParameter(timings, "CKESR");
memSpec->tDQSCK = memSpec->tCK * queryUIntParameter(timings, "DQSCK");
memSpec->tAC = memSpec->tCK * queryUIntParameter(timings, "AC");
memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS");
memSpec->tRC = memSpec->tCK * queryUIntParameter(timings, "RC");
memSpec->tRCD = memSpec->tCK * queryUIntParameter(timings, "RCD");
memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL");
memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL");
memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR");
memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP");
memSpec->tXS = memSpec->tCK * queryUIntParameter(timings, "XS");
memSpec->tCCD_R = memSpec->tCK * queryUIntParameter(timings, "CCD_R");
memSpec->tCCD_W = memSpec->tCK * queryUIntParameter(timings, "CCD_W");
memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI");
memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC");
memSpec->tRP = memSpec->tCK * queryUIntParameter(timings, "RP");
memSpec->tRRD = memSpec->tCK * queryUIntParameter(timings, "RRD");
memSpec->tTAW = memSpec->tCK * queryUIntParameter(timings, "TAW");
memSpec->tWTR = memSpec->tCK * queryUIntParameter(timings, "WTR");
// Currents and voltages
XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec");
@@ -499,31 +495,30 @@ void ConfigurationLoader::loadWideIO2(Configuration &config, XMLElement *xmlSpec
// MemTimings specific for WideIO
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
sc_time clk = memSpec->clk;
memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
memSpec->tDQSS = clk * queryUIntParameter(timings, "DQSS");
memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
memSpec->tRL = clk * queryUIntParameter(timings, "RL");
memSpec->tWL = clk * queryUIntParameter(timings, "WL");
memSpec->tRCpb = clk * queryUIntParameter(timings, "RCPB");
memSpec->tRCab = clk * queryUIntParameter(timings, "RCAB");
memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR");
memSpec->tXSR = clk * queryUIntParameter(timings, "XSR");
memSpec->tXP = clk * queryUIntParameter(timings, "XP");
memSpec->tCCD = clk * queryUIntParameter(timings, "CCD");
memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
memSpec->tRCD = clk * queryUIntParameter(timings, "RCD");
memSpec->tRPpb = clk * queryUIntParameter(timings, "RPPB");
memSpec->tRPab = clk * queryUIntParameter(timings, "RPAB");
memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
memSpec->tWR = clk * queryUIntParameter(timings, "WR");
memSpec->tWTR = clk * queryUIntParameter(timings, "WTR");
memSpec->tRRD = clk * queryUIntParameter(timings, "RRD");
memSpec->tFAW = clk * queryUIntParameter(timings, "FAW");
memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
memSpec->tREFIpb = clk * queryUIntParameter(timings, "REFIPB");
memSpec->tRFCab = clk * queryUIntParameter(timings, "RFCAB");
memSpec->tRFCpb = clk * queryUIntParameter(timings, "RFCPB");
memSpec->tDQSCK = memSpec->tCK * queryUIntParameter(timings, "DQSCK");
memSpec->tDQSS = memSpec->tCK * queryUIntParameter(timings, "DQSS");
memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE");
memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL");
memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL");
memSpec->tRCpb = memSpec->tCK * queryUIntParameter(timings, "RCPB");
memSpec->tRCab = memSpec->tCK * queryUIntParameter(timings, "RCAB");
memSpec->tCKESR = memSpec->tCK * queryUIntParameter(timings, "CKESR");
memSpec->tXSR = memSpec->tCK * queryUIntParameter(timings, "XSR");
memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP");
memSpec->tCCD = memSpec->tCK * queryUIntParameter(timings, "CCD");
memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP");
memSpec->tRCD = memSpec->tCK * queryUIntParameter(timings, "RCD");
memSpec->tRPpb = memSpec->tCK * queryUIntParameter(timings, "RPPB");
memSpec->tRPab = memSpec->tCK * queryUIntParameter(timings, "RPAB");
memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS");
memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR");
memSpec->tWTR = memSpec->tCK * queryUIntParameter(timings, "WTR");
memSpec->tRRD = memSpec->tCK * queryUIntParameter(timings, "RRD");
memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW");
memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI");
memSpec->tREFIpb = memSpec->tCK * queryUIntParameter(timings, "REFIPB");
memSpec->tRFCab = memSpec->tCK * queryUIntParameter(timings, "RFCAB");
memSpec->tRFCpb = memSpec->tCK * queryUIntParameter(timings, "RFCPB");
// Currents and voltages
// TODO: to be completed
@@ -546,46 +541,45 @@ void ConfigurationLoader::loadHBM2(Configuration &config, XMLElement *xmlSpec)
// MemTimings specific for HBM2
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
sc_time clk = memSpec->clk;
memSpec->tDQSCK = clk * queryUIntParameter(timings, "DQSCK");
// memSpec->tDQSQ = clk * queryUIntParameter(timings, "DQSQ");
memSpec->tRC = clk * queryUIntParameter(timings, "RC");
memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
memSpec->tRCDRD = clk * queryUIntParameter(timings, "RCDRD");
memSpec->tRCDWR = clk * queryUIntParameter(timings, "RCDWR");
memSpec->tRRDL = clk * queryUIntParameter(timings, "RRDL");
memSpec->tRRDS = clk * queryUIntParameter(timings, "RRDS");
memSpec->tFAW = clk * queryUIntParameter(timings, "FAW");
memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
memSpec->tRP = clk * queryUIntParameter(timings, "RP");
memSpec->tRL = clk * queryUIntParameter(timings, "RL");
memSpec->tWL = clk * queryUIntParameter(timings, "WL");
memSpec->tPL = clk * queryUIntParameter(timings, "PL");
memSpec->tWR = clk * queryUIntParameter(timings, "WR");
memSpec->tCCDL = clk * queryUIntParameter(timings, "CCDL");
memSpec->tCCDS = clk * queryUIntParameter(timings, "CCDS");
// memSpec->tCCDR = clk * queryUIntParameter(timings, "CCDR");
memSpec->tWTRL = clk * queryUIntParameter(timings, "WTRL");
memSpec->tWTRS = clk * queryUIntParameter(timings, "WTRS");
memSpec->tRTW = clk * queryUIntParameter(timings, "RTW");
memSpec->tXP = clk * queryUIntParameter(timings, "XP");
memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
memSpec->tDQSCK = memSpec->tCK * queryUIntParameter(timings, "DQSCK");
// memSpec->tDQSQ = memSpec->tCK * queryUIntParameter(timings, "DQSQ");
memSpec->tRC = memSpec->tCK * queryUIntParameter(timings, "RC");
memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS");
memSpec->tRCDRD = memSpec->tCK * queryUIntParameter(timings, "RCDRD");
memSpec->tRCDWR = memSpec->tCK * queryUIntParameter(timings, "RCDWR");
memSpec->tRRDL = memSpec->tCK * queryUIntParameter(timings, "RRDL");
memSpec->tRRDS = memSpec->tCK * queryUIntParameter(timings, "RRDS");
memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW");
memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP");
memSpec->tRP = memSpec->tCK * queryUIntParameter(timings, "RP");
memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL");
memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL");
memSpec->tPL = memSpec->tCK * queryUIntParameter(timings, "PL");
memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR");
memSpec->tCCDL = memSpec->tCK * queryUIntParameter(timings, "CCDL");
memSpec->tCCDS = memSpec->tCK * queryUIntParameter(timings, "CCDS");
// memSpec->tCCDR = memSpec->tCK * queryUIntParameter(timings, "CCDR");
memSpec->tWTRL = memSpec->tCK * queryUIntParameter(timings, "WTRL");
memSpec->tWTRS = memSpec->tCK * queryUIntParameter(timings, "WTRS");
memSpec->tRTW = memSpec->tCK * queryUIntParameter(timings, "RTW");
memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP");
memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE");
memSpec->tPD = memSpec->tCKE;
memSpec->tRDPDE = memSpec->tRL + memSpec->tPL
+ (memSpec->burstLength / memSpec->dataRate + 1) * memSpec->clk;
+ (memSpec->burstLength / memSpec->dataRate + 1) * memSpec->tCK;
memSpec->tWRPDE = memSpec->tWL + memSpec->tPL
+ (memSpec->burstLength / memSpec->dataRate + 1) * memSpec->clk + memSpec->tWR;
+ (memSpec->burstLength / memSpec->dataRate + 1) * memSpec->tCK + memSpec->tWR;
memSpec->tWRAPDE = memSpec->tWL + memSpec->tPL
+ (memSpec->burstLength / memSpec->dataRate + 1) * memSpec->clk + memSpec->tWR;
memSpec->tCKESR = memSpec->tCKE + memSpec->clk;
+ (memSpec->burstLength / memSpec->dataRate + 1) * memSpec->tCK + memSpec->tWR;
memSpec->tCKESR = memSpec->tCKE + memSpec->tCK;
memSpec->tRDSRE = memSpec->tRL + memSpec->tPL
+ (memSpec->burstLength / memSpec->dataRate + 1) * memSpec->clk;
memSpec->tXS = clk * queryUIntParameter(timings, "XS");
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
memSpec->tRFCSB = clk * queryUIntParameter(timings, "RFCSB");
memSpec->tRREFD = clk * queryUIntParameter(timings, "RREFD");
memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
memSpec->tREFISB = clk * queryUIntParameter(timings, "REFISB");
+ (memSpec->burstLength / memSpec->dataRate + 1) * memSpec->tCK;
memSpec->tXS = memSpec->tCK * queryUIntParameter(timings, "XS");
memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC");
memSpec->tRFCSB = memSpec->tCK * queryUIntParameter(timings, "RFCSB");
memSpec->tRREFD = memSpec->tCK * queryUIntParameter(timings, "RREFD");
memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI");
memSpec->tREFISB = memSpec->tCK * queryUIntParameter(timings, "REFISB");
// Currents and voltages
// TODO: to be completed
@@ -608,44 +602,43 @@ void ConfigurationLoader::loadGDDR5(Configuration &config, XMLElement *xmlSpec)
// MemTimings specific for GDDR5
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
sc_time clk = memSpec->clk;
memSpec->tRP = clk * queryUIntParameter(timings, "RP");
memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
memSpec->tRC = clk * queryUIntParameter(timings, "RC");
memSpec->tRCDRD = clk * queryUIntParameter(timings, "RCDRD");
memSpec->tRCDWR = clk * queryUIntParameter(timings, "RCDWR");
memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
memSpec->tRRDS = clk * queryUIntParameter(timings, "RRDS");
memSpec->tRRDL = clk * queryUIntParameter(timings, "RRDL");
memSpec->tCCDS = clk * queryUIntParameter(timings, "CCDS");
memSpec->tCCDL = clk * queryUIntParameter(timings, "CCDL");
memSpec->tCL = clk * queryUIntParameter(timings, "CL");
memSpec->tWCK2CKPIN = clk * queryUIntParameter(timings, "WCK2CKPIN");
memSpec->tWCK2CK = clk * queryUIntParameter(timings, "WCK2CK");
memSpec->tWCK2DQO = clk * queryUIntParameter(timings, "WCK2DQO");
memSpec->tRTW = clk * queryUIntParameter(timings, "RTW");
memSpec->tWL = clk * queryUIntParameter(timings, "WL");
memSpec->tWCK2DQI = clk * queryUIntParameter(timings, "WCK2DQI");
memSpec->tWR = clk * queryUIntParameter(timings, "WR");
memSpec->tWTRS = clk * queryUIntParameter(timings, "WTRS");
memSpec->tWTRL = clk * queryUIntParameter(timings, "WTRL");
memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
memSpec->tRP = memSpec->tCK * queryUIntParameter(timings, "RP");
memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS");
memSpec->tRC = memSpec->tCK * queryUIntParameter(timings, "RC");
memSpec->tRCDRD = memSpec->tCK * queryUIntParameter(timings, "RCDRD");
memSpec->tRCDWR = memSpec->tCK * queryUIntParameter(timings, "RCDWR");
memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP");
memSpec->tRRDS = memSpec->tCK * queryUIntParameter(timings, "RRDS");
memSpec->tRRDL = memSpec->tCK * queryUIntParameter(timings, "RRDL");
memSpec->tCCDS = memSpec->tCK * queryUIntParameter(timings, "CCDS");
memSpec->tCCDL = memSpec->tCK * queryUIntParameter(timings, "CCDL");
memSpec->tCL = memSpec->tCK * queryUIntParameter(timings, "CL");
memSpec->tWCK2CKPIN = memSpec->tCK * queryUIntParameter(timings, "WCK2CKPIN");
memSpec->tWCK2CK = memSpec->tCK * queryUIntParameter(timings, "WCK2CK");
memSpec->tWCK2DQO = memSpec->tCK * queryUIntParameter(timings, "WCK2DQO");
memSpec->tRTW = memSpec->tCK * queryUIntParameter(timings, "RTW");
memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL");
memSpec->tWCK2DQI = memSpec->tCK * queryUIntParameter(timings, "WCK2DQI");
memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR");
memSpec->tWTRS = memSpec->tCK * queryUIntParameter(timings, "WTRS");
memSpec->tWTRL = memSpec->tCK * queryUIntParameter(timings, "WTRL");
memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE");
memSpec->tPD = memSpec->tCKE;
memSpec->tXPN = clk * queryUIntParameter(timings, "XPN");
memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
memSpec->tREFIPB = clk * queryUIntParameter(timings, "REFIPB");
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB");
memSpec->tRREFD = clk * queryUIntParameter(timings, "RREFD");
memSpec->tXS = clk * queryUIntParameter(timings, "XS");
memSpec->tFAW = clk * queryUIntParameter(timings, "FAW");
memSpec->t32AW = clk * queryUIntParameter(timings, "32AW");
memSpec->tXPN = memSpec->tCK * queryUIntParameter(timings, "XPN");
memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI");
memSpec->tREFIPB = memSpec->tCK * queryUIntParameter(timings, "REFIPB");
memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC");
memSpec->tRFCPB = memSpec->tCK * queryUIntParameter(timings, "RFCPB");
memSpec->tRREFD = memSpec->tCK * queryUIntParameter(timings, "RREFD");
memSpec->tXS = memSpec->tCK * queryUIntParameter(timings, "XS");
memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW");
memSpec->t32AW = memSpec->tCK * queryUIntParameter(timings, "32AW");
memSpec->tRDSRE = memSpec->tCL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK
+ memSpec->tWCK2DQO + memSpec->burstLength / memSpec->dataRate * clk;
+ memSpec->tWCK2DQO + memSpec->burstLength / memSpec->dataRate * memSpec->tCK;
memSpec->tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK
+ memSpec->tWCK2DQI + memSpec->burstLength / memSpec->dataRate * clk;
memSpec->tPPD = clk * queryUIntParameter(timings, "PPD");
memSpec->tLK = clk * queryUIntParameter(timings, "LK");
+ memSpec->tWCK2DQI + memSpec->burstLength / memSpec->dataRate * memSpec->tCK;
memSpec->tPPD = memSpec->tCK * queryUIntParameter(timings, "PPD");
memSpec->tLK = memSpec->tCK * queryUIntParameter(timings, "LK");
// Currents and voltages
// TODO: to be completed
@@ -668,44 +661,43 @@ void ConfigurationLoader::loadGDDR5X(Configuration &config, XMLElement *xmlSpec)
// MemTimings specific for GDDR5X
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
sc_time clk = memSpec->clk;
memSpec->tRP = clk * queryUIntParameter(timings, "RP");
memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
memSpec->tRC = clk * queryUIntParameter(timings, "RC");
memSpec->tRCDRD = clk * queryUIntParameter(timings, "RCDRD");
memSpec->tRCDWR = clk * queryUIntParameter(timings, "RCDWR");
memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
memSpec->tRRDS = clk * queryUIntParameter(timings, "RRDS");
memSpec->tRRDL = clk * queryUIntParameter(timings, "RRDL");
memSpec->tCCDS = clk * queryUIntParameter(timings, "CCDS");
memSpec->tCCDL = clk * queryUIntParameter(timings, "CCDL");
memSpec->tRL = clk * queryUIntParameter(timings, "RL");
memSpec->tWCK2CKPIN = clk * queryUIntParameter(timings, "WCK2CKPIN");
memSpec->tWCK2CK = clk * queryUIntParameter(timings, "WCK2CK");
memSpec->tWCK2DQO = clk * queryUIntParameter(timings, "WCK2DQO");
memSpec->tRTW = clk * queryUIntParameter(timings, "RTW");
memSpec->tWL = clk * queryUIntParameter(timings, "WL");
memSpec->tWCK2DQI = clk * queryUIntParameter(timings, "WCK2DQI");
memSpec->tWR = clk * queryUIntParameter(timings, "WR");
memSpec->tWTRS = clk * queryUIntParameter(timings, "WTRS");
memSpec->tWTRL = clk * queryUIntParameter(timings, "WTRL");
memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
memSpec->tRP = memSpec->tCK * queryUIntParameter(timings, "RP");
memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS");
memSpec->tRC = memSpec->tCK * queryUIntParameter(timings, "RC");
memSpec->tRCDRD = memSpec->tCK * queryUIntParameter(timings, "RCDRD");
memSpec->tRCDWR = memSpec->tCK * queryUIntParameter(timings, "RCDWR");
memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP");
memSpec->tRRDS = memSpec->tCK * queryUIntParameter(timings, "RRDS");
memSpec->tRRDL = memSpec->tCK * queryUIntParameter(timings, "RRDL");
memSpec->tCCDS = memSpec->tCK * queryUIntParameter(timings, "CCDS");
memSpec->tCCDL = memSpec->tCK * queryUIntParameter(timings, "CCDL");
memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL");
memSpec->tWCK2CKPIN = memSpec->tCK * queryUIntParameter(timings, "WCK2CKPIN");
memSpec->tWCK2CK = memSpec->tCK * queryUIntParameter(timings, "WCK2CK");
memSpec->tWCK2DQO = memSpec->tCK * queryUIntParameter(timings, "WCK2DQO");
memSpec->tRTW = memSpec->tCK * queryUIntParameter(timings, "RTW");
memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL");
memSpec->tWCK2DQI = memSpec->tCK * queryUIntParameter(timings, "WCK2DQI");
memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR");
memSpec->tWTRS = memSpec->tCK * queryUIntParameter(timings, "WTRS");
memSpec->tWTRL = memSpec->tCK * queryUIntParameter(timings, "WTRL");
memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE");
memSpec->tPD = memSpec->tCKE;
memSpec->tXP = clk * queryUIntParameter(timings, "XP");
memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
memSpec->tREFIPB = clk * queryUIntParameter(timings, "REFIPB");
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB");
memSpec->tRREFD = clk * queryUIntParameter(timings, "RREFD");
memSpec->tXS = clk * queryUIntParameter(timings, "XS");
memSpec->tFAW = clk * queryUIntParameter(timings, "FAW");
memSpec->t32AW = clk * queryUIntParameter(timings, "32AW");
memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP");
memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI");
memSpec->tREFIPB = memSpec->tCK * queryUIntParameter(timings, "REFIPB");
memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC");
memSpec->tRFCPB = memSpec->tCK * queryUIntParameter(timings, "RFCPB");
memSpec->tRREFD = memSpec->tCK * queryUIntParameter(timings, "RREFD");
memSpec->tXS = memSpec->tCK * queryUIntParameter(timings, "XS");
memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW");
memSpec->t32AW = memSpec->tCK * queryUIntParameter(timings, "32AW");
memSpec->tRDSRE = memSpec->tRL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK
+ memSpec->tWCK2DQO + memSpec->burstLength / memSpec->dataRate * clk;
+ memSpec->tWCK2DQO + memSpec->burstLength / memSpec->dataRate * memSpec->tCK;
memSpec->tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK
+ memSpec->tWCK2DQI + memSpec->burstLength / memSpec->dataRate * clk;
memSpec->tPPD = clk * queryUIntParameter(timings, "PPD");
memSpec->tLK = clk * queryUIntParameter(timings, "LK");
+ memSpec->tWCK2DQI + memSpec->burstLength / memSpec->dataRate * memSpec->tCK;
memSpec->tPPD = memSpec->tCK * queryUIntParameter(timings, "PPD");
memSpec->tLK = memSpec->tCK * queryUIntParameter(timings, "LK");
// Currents and voltages
// TODO: to be completed
@@ -728,47 +720,46 @@ void ConfigurationLoader::loadGDDR6(Configuration &config, XMLElement *xmlSpec)
// MemTimings specific for GDDR6
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
sc_time clk = memSpec->clk;
memSpec->tRP = clk * queryUIntParameter(timings, "RP");
memSpec->tRAS = clk * queryUIntParameter(timings, "RAS");
memSpec->tRC = clk * queryUIntParameter(timings, "RC");
memSpec->tRCDRD = clk * queryUIntParameter(timings, "RCDRD");
memSpec->tRCDWR = clk * queryUIntParameter(timings, "RCDWR");
memSpec->tRTP = clk * queryUIntParameter(timings, "RTP");
memSpec->tRRDS = clk * queryUIntParameter(timings, "RRDS");
memSpec->tRRDL = clk * queryUIntParameter(timings, "RRDL");
memSpec->tCCDS = clk * queryUIntParameter(timings, "CCDS");
memSpec->tCCDL = clk * queryUIntParameter(timings, "CCDL");
memSpec->tRL = clk * queryUIntParameter(timings, "RL");
memSpec->tWCK2CKPIN = clk * queryUIntParameter(timings, "WCK2CKPIN");
memSpec->tWCK2CK = clk * queryUIntParameter(timings, "WCK2CK");
memSpec->tWCK2DQO = clk * queryUIntParameter(timings, "WCK2DQO");
memSpec->tRTW = clk * queryUIntParameter(timings, "RTW");
memSpec->tWL = clk * queryUIntParameter(timings, "WL");
memSpec->tWCK2DQI = clk * queryUIntParameter(timings, "WCK2DQI");
memSpec->tWR = clk * queryUIntParameter(timings, "WR");
memSpec->tWTRS = clk * queryUIntParameter(timings, "WTRS");
memSpec->tWTRL = clk * queryUIntParameter(timings, "WTRL");
memSpec->tCKE = clk * queryUIntParameter(timings, "CKE");
memSpec->tRP = memSpec->tCK * queryUIntParameter(timings, "RP");
memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS");
memSpec->tRC = memSpec->tCK * queryUIntParameter(timings, "RC");
memSpec->tRCDRD = memSpec->tCK * queryUIntParameter(timings, "RCDRD");
memSpec->tRCDWR = memSpec->tCK * queryUIntParameter(timings, "RCDWR");
memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP");
memSpec->tRRDS = memSpec->tCK * queryUIntParameter(timings, "RRDS");
memSpec->tRRDL = memSpec->tCK * queryUIntParameter(timings, "RRDL");
memSpec->tCCDS = memSpec->tCK * queryUIntParameter(timings, "CCDS");
memSpec->tCCDL = memSpec->tCK * queryUIntParameter(timings, "CCDL");
memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL");
memSpec->tWCK2CKPIN = memSpec->tCK * queryUIntParameter(timings, "WCK2CKPIN");
memSpec->tWCK2CK = memSpec->tCK * queryUIntParameter(timings, "WCK2CK");
memSpec->tWCK2DQO = memSpec->tCK * queryUIntParameter(timings, "WCK2DQO");
memSpec->tRTW = memSpec->tCK * queryUIntParameter(timings, "RTW");
memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL");
memSpec->tWCK2DQI = memSpec->tCK * queryUIntParameter(timings, "WCK2DQI");
memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR");
memSpec->tWTRS = memSpec->tCK * queryUIntParameter(timings, "WTRS");
memSpec->tWTRL = memSpec->tCK * queryUIntParameter(timings, "WTRL");
memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE");
memSpec->tPD = memSpec->tCKE;
memSpec->tCKESR = clk * queryUIntParameter(timings, "CKESR");
memSpec->tXP = clk * queryUIntParameter(timings, "XP");
memSpec->tREFI = clk * queryUIntParameter(timings, "REFI");
memSpec->tREFIPB = clk * queryUIntParameter(timings, "REFIPB");
memSpec->tRFC = clk * queryUIntParameter(timings, "RFC");
memSpec->tRFCPB = clk * queryUIntParameter(timings, "RFCPB");
memSpec->tRREFD = clk * queryUIntParameter(timings, "RREFD");
memSpec->tXS = clk * queryUIntParameter(timings, "XS");
memSpec->tFAW = clk * queryUIntParameter(timings, "FAW");
memSpec->tCKESR = memSpec->tCK * queryUIntParameter(timings, "CKESR");
memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP");
memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI");
memSpec->tREFIPB = memSpec->tCK * queryUIntParameter(timings, "REFIPB");
memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC");
memSpec->tRFCPB = memSpec->tCK * queryUIntParameter(timings, "RFCPB");
memSpec->tRREFD = memSpec->tCK * queryUIntParameter(timings, "RREFD");
memSpec->tXS = memSpec->tCK * queryUIntParameter(timings, "XS");
memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW");
memSpec->tRDSRE = memSpec->tRL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK
+ memSpec->tWCK2DQO + memSpec->burstLength / memSpec->dataRate * clk;
+ memSpec->tWCK2DQO + memSpec->burstLength / memSpec->dataRate * memSpec->tCK;
memSpec->tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK
+ memSpec->tWCK2DQI + memSpec->burstLength / memSpec->dataRate * clk;
memSpec->tPPD = clk * queryUIntParameter(timings, "PPD");
memSpec->tLK = clk * queryUIntParameter(timings, "LK");
memSpec->tACTPDE = clk * queryUIntParameter(timings, "ACTPDE");
memSpec->tPREPDE = clk * queryUIntParameter(timings, "PREPDE");
memSpec->tREFPDE = clk * queryUIntParameter(timings, "REFPDE");
+ memSpec->tWCK2DQI + memSpec->burstLength / memSpec->dataRate * memSpec->tCK;
memSpec->tPPD = memSpec->tCK * queryUIntParameter(timings, "PPD");
memSpec->tLK = memSpec->tCK * queryUIntParameter(timings, "LK");
memSpec->tACTPDE = memSpec->tCK * queryUIntParameter(timings, "ACTPDE");
memSpec->tPREPDE = memSpec->tCK * queryUIntParameter(timings, "PREPDE");
memSpec->tREFPDE = memSpec->tCK * queryUIntParameter(timings, "REFPDE");
// Currents and voltages
// TODO: to be completed

2
DRAMSys/library/src/configuration/memspec/MemSpec.cpp
View File

@@ -59,5 +59,5 @@ const std::vector<Bank> &MemSpec::getBanks() const
sc_time MemSpec::getCommandLength(Command command) const
{
return clk * commandLengthInCycles[command];
return tCK * commandLengthInCycles[command];
}

4
DRAMSys/library/src/configuration/memspec/MemSpec.h
View File

@@ -78,8 +78,8 @@ struct MemSpec
unsigned int groupsPerRank;
// Clock
double clkMHz;
sc_time clk;
double fCKMHz;
sc_time tCK;
sc_time burstDuration;

4
DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp
View File

@@ -52,9 +52,9 @@ sc_time MemSpecGDDR6::getExecutionTime(Command command, const tlm_generic_payloa
else if (command == Command::ACT)
{
if (payload.get_command() == TLM_READ_COMMAND)
return tRCDRD + clk;
return tRCDRD + tCK;
else
return tRCDWR + clk;
return tRCDWR + tCK;
}
else if (command == Command::RD)
return tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration;

4
DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp
View File

@@ -57,9 +57,9 @@ sc_time MemSpecHBM2::getExecutionTime(Command command, const tlm_generic_payload
else if (command == Command::ACT)
{
if (payload.get_command() == TLM_READ_COMMAND)
return tRCDRD + clk;
return tRCDRD + tCK;
else
return tRCDWR + clk;
return tRCDWR + tCK;
}
else if (command == Command::RD)
return tRL + tDQSCK + burstDuration;

10
DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h
View File

@@ -67,11 +67,11 @@ struct MemSpecHBM2 final : public MemSpec
sc_time tXP;
sc_time tCKE;
sc_time tPD; // = tCKE;
sc_time tRDPDE; // = tRL + tPL + (BurstLength / DataRate) * clk + clk;
sc_time tWRPDE; // = tWL + tPL + (BurstLength / DataRate) * clk + clk + tWR;
sc_time tWRAPDE; // = tWL + tPL + (BurstLength / DataRate) * clk + clk + tWR;
sc_time tCKESR; // = tCKE + clk;
sc_time tRDSRE; // = tRL + tPL + (BurstLength / DataRate) * clk + clk;
sc_time tRDPDE; // = tRL + tPL + (BurstLength / DataRate) * tCK + tCK;
sc_time tWRPDE; // = tWL + tPL + (BurstLength / DataRate) * tCK + tCK + tWR;
sc_time tWRAPDE; // = tWL + tPL + (BurstLength / DataRate) * tCK + tCK + tWR;
sc_time tCKESR; // = tCKE + tCK;
sc_time tRDSRE; // = tRL + tPL + (BurstLength / DataRate) * tCK + tCK;
sc_time tXS;
sc_time tRFC;
sc_time tRFCSB;

26
DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp
View File

@@ -63,23 +63,23 @@ sc_time MemSpecLPDDR4::getRefreshIntervalPB() const
sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_payload &) const
{
if (command == Command::PRE)
return tRPpb + clk;
return tRPpb + tCK;
else if (command == Command::PREA)
return tRPab + clk;
return tRPab + tCK;
else if (command == Command::ACT)
return tRCD + 3 * clk;
return tRCD + 3 * tCK;
else if (command == Command::RD)
return tRL + tDQSCK + burstDuration + 3 * clk;
return tRL + tDQSCK + burstDuration + 3 * tCK;
else if (command == Command::RDA)
return burstDuration + tRTP - 5 * clk + tRPpb;
return burstDuration + tRTP - 5 * tCK + tRPpb;
else if (command == Command::WR)
return tWL + tDQSS + tDQS2DQ + burstDuration + 3 * clk;
return tWL + tDQSS + tDQS2DQ + burstDuration + 3 * tCK;
else if (command == Command::WRA)
return tWL + 4 * clk + burstDuration + tWR + tRPpb;
return tWL + 4 * tCK + burstDuration + tWR + tRPpb;
else if (command == Command::REFA)
return tRFCab + clk;
return tRFCab + tCK;
else if (command == Command::REFB)
return tRFCpb + clk;
return tRFCpb + tCK;
else
{
SC_REPORT_FATAL("getExecutionTime",
@@ -91,11 +91,11 @@ sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_paylo
TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(sc_time_stamp() + tRL + tDQSCK + 3 * clk,
sc_time_stamp() + tRL + tDQSCK + burstDuration + 3 * clk);
return TimeInterval(sc_time_stamp() + tRL + tDQSCK + 3 * tCK,
sc_time_stamp() + tRL + tDQSCK + burstDuration + 3 * tCK);
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(sc_time_stamp() + tWL + tDQSS + tDQS2DQ + 3 * clk,
sc_time_stamp() + tWL + tDQSS + tDQS2DQ + burstDuration + 3 * clk);
return TimeInterval(sc_time_stamp() + tWL + tDQSS + tDQS2DQ + 3 * tCK,
sc_time_stamp() + tWL + tDQSS + tDQS2DQ + burstDuration + 3 * tCK);
else
{
SC_REPORT_FATAL("MemSpecLPDDR4", "Method was called with invalid argument");

2
DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp
View File

@@ -60,7 +60,7 @@ sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_paylo
else if (command == Command::WR)
return tWL + burstDuration;
else if (command == Command::WRA)
return tWL + burstDuration - clk + tWR + tRP;
return tWL + burstDuration - tCK + tWR + tRP;
else if (command == Command::REFA)
return tRFC;
else

4
DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp
View File

@@ -57,11 +57,11 @@ sc_time MemSpecWideIO2::getExecutionTime(Command command, const tlm_generic_payl
else if (command == Command::RD)
return tRL + tDQSCK + burstDuration;
else if (command == Command::RDA)
return burstDuration - 2 * clk + tRTP + tRPpb;
return burstDuration - 2 * tCK + tRTP + tRPpb;
else if (command == Command::WR)
return tWL + tDQSS + burstDuration;
else if (command == Command::WRA)
return tWL + burstDuration + clk + tWR + tRPpb;
return tWL + burstDuration + tCK + tWR + tRPpb;
else if (command == Command::REFA)
return tRFCab;
else if (command == Command::REFB)

4
DRAMSys/library/src/controller/Controller.cpp
View File

@@ -360,14 +360,14 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &trans,
if (phase == BEGIN_REQ)
{
notificationDelay += Configuration::getInstance().memSpec->clk;
notificationDelay += Configuration::getInstance().memSpec->tCK;
payloadToAcquire = &trans;
timeToAcquire = sc_time_stamp() + notificationDelay;
beginReqEvent.notify(notificationDelay);
}
else if (phase = END_RESP)
{
notificationDelay += Configuration::getInstance().memSpec->clk;
notificationDelay += Configuration::getInstance().memSpec->tCK;
timeToRelease = sc_time_stamp() + notificationDelay;
endRespEvent.notify(notificationDelay);
}

6
DRAMSys/library/src/controller/ControllerIF.h
View File

@@ -24,14 +24,14 @@ public:
sc_time activeTime = numberOfTransactionsServed
* Configuration::getInstance().memSpec->burstLength
/ Configuration::getInstance().memSpec->dataRate
* Configuration::getInstance().memSpec->clk;
* Configuration::getInstance().memSpec->tCK;
double bandwidth = (activeTime / sc_time_stamp() * 100);
double bandwidth_IDLE = ((activeTime) / (sc_time_stamp() - idleTime) * 100);
double maxBandwidth = (
// clk in Mhz e.g. 800 [MHz]:
(1000000 / Configuration::getInstance().memSpec->clk.to_double())
// fCK in Mhz e.g. 800 [MHz]:
(1000000 / Configuration::getInstance().memSpec->tCK.to_double())
// DataRate e.g. 2
* Configuration::getInstance().memSpec->dataRate
// BusWidth e.g. 8 or 64

24
DRAMSys/library/src/controller/checker/CheckerDDR3.cpp
View File

@@ -152,12 +152,12 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGr
lastCommandStart = lastScheduledByCommand[Command::RD];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tRL + memSpec->burstDuration + 2 * memSpec->clk - memSpec->tWL);
+ memSpec->tRL + memSpec->burstDuration + 2 * memSpec->tCK - memSpec->tWL);
lastCommandStart = lastScheduledByCommand[Command::RDA];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tRL + memSpec->burstDuration + 2 * memSpec->clk - memSpec->tWL);
+ memSpec->tRL + memSpec->burstDuration + 2 * memSpec->tCK - memSpec->tWL);
lastCommandStart = lastScheduledByCommand[Command::WR];
if (lastCommandStart != SC_ZERO_TIME)
@@ -260,22 +260,22 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGr
lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tRL + 5 * memSpec->clk);
+ memSpec->tRL + 5 * memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tRL + 5 * memSpec->clk);
+ memSpec->tRL + 5 * memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tWL + 4 * memSpec->clk + memSpec->tWR);
+ memSpec->tWL + 4 * memSpec->tCK + memSpec->tWR);
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tWL + 5 * memSpec->clk + memSpec->tWR);
+ memSpec->tWL + 5 * memSpec->tCK + memSpec->tWR);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXA][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
@@ -292,17 +292,17 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGr
lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tRL + 5 * memSpec->clk);
+ memSpec->tRL + 5 * memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tRL + 5 * memSpec->clk);
+ memSpec->tRL + 5 * memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tWL + 5 * memSpec->clk + memSpec->tWR);
+ memSpec->tWL + 5 * memSpec->tCK + memSpec->tWR);
lastCommandStart = lastScheduledByCommandAndRank[Command::PDXP][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
@@ -323,12 +323,12 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGr
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ std::max(memSpec->tRL + 5 * memSpec->clk, memSpec->tAL + memSpec->tRTP + memSpec->tRP));
+ std::max(memSpec->tRL + 5 * memSpec->tCK, memSpec->tAL + memSpec->tRTP + memSpec->tRP));
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ std::max(memSpec->tWL + 5 * memSpec->clk + memSpec->tWR, memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP));
+ std::max(memSpec->tWL + 5 * memSpec->tCK + memSpec->tWR, memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP));
lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
@@ -360,7 +360,7 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGr
reportFatal("CheckerDDR3", "Unknown command!");
// Check if command bus is free
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->tCK);
return earliestTimeToStart;
}

6
DRAMSys/library/src/controller/checker/CheckerDDR4.cpp
View File

@@ -152,12 +152,12 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGr
lastCommandStart = lastScheduledByCommand[Command::RD];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL
+ memSpec->burstDuration + 2 * memSpec->clk - memSpec->tWL);
+ memSpec->burstDuration + 2 * memSpec->tCK - memSpec->tWL);
lastCommandStart = lastScheduledByCommand[Command::RDA];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL
+ memSpec->burstDuration + 2 * memSpec->clk - memSpec->tWL);
+ memSpec->burstDuration + 2 * memSpec->tCK - memSpec->tWL);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()];
if (lastCommandStart != SC_ZERO_TIME)
@@ -243,7 +243,7 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGr
reportFatal("CheckerDDR4", "Unknown command!");
// Check if command bus is free
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->tCK);
return earliestTimeToStart;
}

2
DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp
View File

@@ -308,7 +308,7 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankG
reportFatal("CheckerGDDR5", "Unknown command!");
}
// Check if command bus is free
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->tCK);
return earliestTimeToStart;
}

2
DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp
View File

@@ -308,7 +308,7 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, Bank
reportFatal("CheckerGDDR5X", "Unknown command!");
}
// Check if command bus is free
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->tCK);
return earliestTimeToStart;
}

2
DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp
View File

@@ -301,7 +301,7 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankG
reportFatal("CheckerGDDR6", "Unknown command!");
}
// Check if command bus is free
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->tCK);
return earliestTimeToStart;
}

48
DRAMSys/library/src/controller/checker/CheckerHBM2.cpp
View File

@@ -75,43 +75,43 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr
lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tRTP + memSpec->tRP - memSpec->clk);
+ memSpec->tRTP + memSpec->tRP - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP - memSpec->clk);
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tRP - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP - memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP - memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRP - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC - memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCSB - memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCSB - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD - memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRREFD - memSpec->tCK);
if (lastActivates[rank.ID()].size() == 4)
earliestTimeToStart = std::max(earliestTimeToStart,
lastActivates[rank.ID()].front() + memSpec->tFAW - memSpec->clk);
lastActivates[rank.ID()].front() + memSpec->tFAW - memSpec->tCK);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK);
}
else if (command == Command::RD || command == Command::RDA)
{
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD + memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDRD + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()];
if (lastCommandStart != SC_ZERO_TIME)
@@ -157,12 +157,12 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWTRS);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCasBus + memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCasBus + memSpec->tCK);
}
else if (command == Command::WR || command == Command::WRA)
{
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDWR + memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCDWR + memSpec->tCK);
lastCommandStart = lastScheduledByCommand[Command::RD];
if (lastCommandStart != SC_ZERO_TIME)
@@ -188,12 +188,12 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCDS);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCasBus + memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnCasBus + memSpec->tCK);
}
else if (command == Command::PRE)
{
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
@@ -204,12 +204,12 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK);
}
else if (command == Command::PREA)
{
lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()];
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
@@ -229,13 +229,13 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK);
}
else if (command == Command::REFA)
{
lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
@@ -258,21 +258,21 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFC);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK);
}
else if (command == Command::REFB)
{
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::ACT][bankgroup.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL + memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDL + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDS + memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRDS + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
@@ -303,7 +303,7 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr
if (lastActivates[rank.ID()].size() == 4)
earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnRasBus + memSpec->tCK);
}
else
{
@@ -326,7 +326,7 @@ void CheckerHBM2::insert(Command command, Rank rank, BankGroup bankgroup, Bank b
if (isCasCommand(command))
lastCommandOnCasBus = sc_time_stamp();
else if (command == Command::ACT)
lastCommandOnRasBus = sc_time_stamp() + memSpec->clk;
lastCommandOnRasBus = sc_time_stamp() + memSpec->tCK;
else
lastCommandOnRasBus = sc_time_stamp();

56
DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp
View File

@@ -64,15 +64,15 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, Bank
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->burstDuration
+ memSpec->tWR + memSpec->clk + memSpec->tRPpb);
+ memSpec->tWR + memSpec->tCK + memSpec->tRPpb);
lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPpb - 2 * memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPpb - 2 * memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::PREA][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPab - 2 * memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPab - 2 * memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
@@ -84,18 +84,18 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, Bank
lastCommandStart = lastScheduledByCommandAndRank[Command::REFA][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCab - 2 * memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCab - 2 * memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::REFB][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb - 2 * memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb - 2 * memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD - 2 * memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD - 2 * memSpec->tCK);
if (lastActivates[rank.ID()].size() == 4)
earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW - 3 * memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW - 3 * memSpec->tCK);
}
else if (command == Command::RD || command == Command::RDA)
{
@@ -112,19 +112,19 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, Bank
lastCommandStart = lastScheduledByCommand[Command::WR];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->clk + memSpec->burstDuration + memSpec->tWTR);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCK + memSpec->burstDuration + memSpec->tWTR);
if (command == Command::RDA)
{
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tWL + memSpec->clk + memSpec->burstDuration + memSpec->tWR - memSpec->tRTP);
+ memSpec->tWL + memSpec->tCK + memSpec->burstDuration + memSpec->tWR - memSpec->tRTP);
}
lastCommandStart = lastScheduledByCommand[Command::WRA];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->clk + memSpec->burstDuration + memSpec->tWTR);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->tCK + memSpec->burstDuration + memSpec->tWTR);
}
else if (command == Command::WR || command == Command::WRA)
{
@@ -150,15 +150,15 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, Bank
else if (command == Command::PRE)
{
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + 2 * memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + 2 * memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration + memSpec->tRTP - 6 * memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration + memSpec->tRTP - 6 * memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + 3 * memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + 3 * memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
@@ -167,23 +167,23 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, Bank
else if (command == Command::PREA)
{
lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()];
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + 2 * memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + 2 * memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration + memSpec->tRTP - 6 * memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration + memSpec->tRTP - 6 * memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration + memSpec->tRTP - 6 * memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->burstDuration + memSpec->tRTP - 6 * memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + 3 * memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + 3 * memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + 3 * memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->burstDuration + memSpec->tWR + 3 * memSpec->tCK);
// lastCommandStart = lastScheduledByCommandAndRank[Command::REFB][rank.ID()];
// if (lastCommandStart != SC_ZERO_TIME)
@@ -197,16 +197,16 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, Bank
{
lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tRPpb + 2 * memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tRPpb + 2 * memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRPpb + 2 * memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRPpb + 2 * memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->burstDuration
+ memSpec->tWR + 3 * memSpec->clk + memSpec->tRPpb);
+ memSpec->tWR + 3 * memSpec->tCK + memSpec->tRPpb);
lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
@@ -228,20 +228,20 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, Bank
{
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tRPpb + 2 * memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tRPpb + 2 * memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD + 2 * memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD + 2 * memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRPpb + 2 * memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tRPpb + 2 * memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL + memSpec->burstDuration
+ memSpec->tWR + 3 * memSpec->clk + memSpec->tRPpb);
+ memSpec->tWR + 3 * memSpec->tCK + memSpec->tRPpb);
lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
@@ -260,14 +260,14 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, Bank
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb);
if (lastActivates[rank.ID()].size() == 4)
earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW - memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastActivates[rank.ID()].front() + memSpec->tFAW - memSpec->tCK);
}
else
{
reportFatal("CheckerLPDDR4", "Unknown command!");
}
// Check if command bus is free
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->tCK);
return earliestTimeToStart;
}
@@ -280,7 +280,7 @@ void CheckerLPDDR4::insert(Command command, Rank rank, BankGroup, Bank bank)
lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp();
lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp();
lastScheduledByCommand[command] = sc_time_stamp();
lastCommandOnBus = sc_time_stamp() + memSpec->getCommandLength(command) - memSpec->clk;
lastCommandOnBus = sc_time_stamp() + memSpec->getCommandLength(command) - memSpec->tCK;
if (command == Command::ACT || command == Command::REFB)
{

22
DRAMSys/library/src/controller/checker/CheckerWideIO.cpp
View File

@@ -64,7 +64,7 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, Bank
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
+ memSpec->burstDuration - memSpec->clk + memSpec->tWR + memSpec->tRP);
+ memSpec->burstDuration - memSpec->tCK + memSpec->tWR + memSpec->tRP);
lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
@@ -105,20 +105,20 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, Bank
lastCommandStart = lastScheduledByCommand[Command::WR];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tWL + memSpec->burstDuration - memSpec->clk + memSpec->tWTR);
+ memSpec->tWL + memSpec->burstDuration - memSpec->tCK + memSpec->tWTR);
if (command == Command::RDA)
{
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tWL + memSpec->clk + memSpec->tWR);
+ memSpec->tWL + memSpec->tCK + memSpec->tWR);
}
lastCommandStart = lastScheduledByCommand[Command::WRA];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tWL + memSpec->burstDuration - memSpec->clk + memSpec->tWTR);
+ memSpec->tWL + memSpec->burstDuration - memSpec->tCK + memSpec->tWTR);
}
else if (command == Command::WR || command == Command::WRA)
{
@@ -128,12 +128,12 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, Bank
lastCommandStart = lastScheduledByCommand[Command::RD];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tRL + memSpec->burstDuration + memSpec->clk);
+ memSpec->tRL + memSpec->burstDuration + memSpec->tCK);
lastCommandStart = lastScheduledByCommand[Command::RDA];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tRL + memSpec->burstDuration + memSpec->clk);
+ memSpec->tRL + memSpec->burstDuration + memSpec->tCK);
lastCommandStart = lastScheduledByCommand[Command::WR];
if (lastCommandStart != SC_ZERO_TIME)
@@ -155,7 +155,7 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, Bank
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tWL + memSpec->burstDuration - memSpec->clk + memSpec->tWR);
+ memSpec->tWL + memSpec->burstDuration - memSpec->tCK + memSpec->tWR);
}
else if (command == Command::PREA)
{
@@ -173,12 +173,12 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, Bank
lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tWL + memSpec->burstDuration - memSpec->clk + memSpec->tWR);
+ memSpec->tWL + memSpec->burstDuration - memSpec->tCK + memSpec->tWR);
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tWL + memSpec->burstDuration - memSpec->clk + memSpec->tWR);
+ memSpec->tWL + memSpec->burstDuration - memSpec->tCK + memSpec->tWR);
}
else if (command == Command::REFA)
{
@@ -193,7 +193,7 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, Bank
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tWL + memSpec->burstDuration - memSpec->clk + memSpec->tWR + memSpec->tRP);
+ memSpec->tWL + memSpec->burstDuration - memSpec->tCK + memSpec->tWR + memSpec->tRP);
lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
@@ -212,7 +212,7 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, Bank
reportFatal("CheckerWideIO", "Unknown command!");
}
// Check if command bus is free
earliestTimeToStart = std::max(earliestTimeToStart, lastScheduled + memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastScheduled + memSpec->tCK);
return earliestTimeToStart;
}

38
DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp
View File

@@ -68,12 +68,12 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, Ban
lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->clk + memSpec->tRPpb);
+ memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->tCK + memSpec->tRPpb);
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->clk + memSpec->tRPpb);
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tCK + memSpec->tRPpb);
lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
@@ -114,20 +114,20 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, Ban
lastCommandStart = lastScheduledByCommand[Command::WR];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tWL + memSpec->clk + memSpec->burstDuration + memSpec->tWTR);
+ memSpec->tWL + memSpec->tCK + memSpec->burstDuration + memSpec->tWTR);
if (command == Command::RDA)
{
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tWL + memSpec->clk + memSpec->burstDuration + memSpec->tWR - memSpec->tRTP);
+ memSpec->tWL + memSpec->tCK + memSpec->burstDuration + memSpec->tWR - memSpec->tRTP);
}
lastCommandStart = lastScheduledByCommand[Command::WRA];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tWL + memSpec->clk + memSpec->burstDuration + memSpec->tWTR);
+ memSpec->tWL + memSpec->tCK + memSpec->burstDuration + memSpec->tWTR);
}
else if (command == Command::WR || command == Command::WRA)
{
@@ -137,12 +137,12 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, Ban
lastCommandStart = lastScheduledByCommand[Command::RD];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tRL + memSpec->tDQSCK + memSpec->burstDuration + memSpec->clk - memSpec->tWL);
+ memSpec->tRL + memSpec->tDQSCK + memSpec->burstDuration + memSpec->tCK - memSpec->tWL);
lastCommandStart = lastScheduledByCommand[Command::RDA];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tRL + memSpec->tDQSCK + memSpec->burstDuration + memSpec->clk - memSpec->tWL);
+ memSpec->tRL + memSpec->tDQSCK + memSpec->burstDuration + memSpec->tCK - memSpec->tWL);
lastCommandStart = lastScheduledByCommand[Command::WR];
if (lastCommandStart != SC_ZERO_TIME)
@@ -160,12 +160,12 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, Ban
lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->clk);
+ memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->clk);
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tCK);
}
else if (command == Command::PREA)
{
@@ -175,26 +175,26 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, Ban
lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->clk);
+ memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->clk);
+ memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->clk);
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->clk);
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + 2 * memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + 2 * memSpec->tCK);
}
else if (command == Command::REFA)
{
@@ -205,12 +205,12 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, Ban
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->clk + memSpec->tRPpb);
+ memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->tCK + memSpec->tRPpb);
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->clk + memSpec->tRPpb);
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tCK + memSpec->tRPpb);
lastCommandStart = lastScheduledByCommandAndRank[Command::PRE][rank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
@@ -237,12 +237,12 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, Ban
lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->clk + memSpec->tRPpb);
+ memSpec->burstDuration + memSpec->tRTP - 2 * memSpec->tCK + memSpec->tRPpb);
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->clk + memSpec->tRPpb);
+ memSpec->tWL + memSpec->burstDuration + memSpec->tWR + memSpec->tCK + memSpec->tRPpb);
lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()];
if (lastCommandStart != SC_ZERO_TIME)
@@ -260,7 +260,7 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, Ban
reportFatal("CheckerWideIO2", "Unknown command!");
}
// Check if command bus is free
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->clk);
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->tCK);
return earliestTimeToStart;
}

4
DRAMSys/library/src/error/errormodel.cpp
View File

@@ -497,8 +497,8 @@ double errorModel::getTemperature()
if (thermalSim == true && powerAnalysis == true) {
// TODO
// check if this is best way to request information to DRAMPower.
unsigned long long clk_cycles = sc_time_stamp().value() /
Configuration::getInstance().memSpec->clk.value();
unsigned long long clk_cycles = sc_time_stamp() /
Configuration::getInstance().memSpec->tCK;
DRAMPower->calcWindowEnergy(clk_cycles);
float average_power = (float)DRAMPower->getPower().average_power;
temperature = TemperatureController::getInstance().getTemperature(

6
DRAMSys/library/src/simulation/Arbiter.cpp
View File

@@ -67,8 +67,8 @@ Arbiter::Arbiter(sc_module_name name) :
tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload &payload,
tlm_phase &phase, sc_time &fwDelay)
{
sc_time notDelay = std::ceil((sc_time_stamp() + fwDelay) / Configuration::getInstance().memSpec->clk)
* Configuration::getInstance().memSpec->clk - sc_time_stamp();
sc_time notDelay = std::ceil((sc_time_stamp() + fwDelay) / Configuration::getInstance().memSpec->tCK)
* Configuration::getInstance().memSpec->tCK - sc_time_stamp();
if (phase == BEGIN_REQ)
{
@@ -83,7 +83,7 @@ tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload &payload,
}
else if (phase == END_RESP)
{
notDelay += Configuration::getInstance().memSpec->clk;
notDelay += Configuration::getInstance().memSpec->tCK;
payload.release();
}

10
DRAMSys/library/src/simulation/TraceGenerator.h
View File

@@ -45,13 +45,13 @@ using namespace tlm;
struct TraceGenerator : public TracePlayer
{
public:
TraceGenerator(sc_module_name name, unsigned int clkMhz, TracePlayerListener *listener)
TraceGenerator(sc_module_name name, unsigned int fCKMhz, TracePlayerListener *listener)
: TracePlayer(name, listener), transCounter(0)
{
if (clkMhz == 0)
clk = Configuration::getInstance().memSpec->clk;
if (fCKMhz == 0)
tCK = Configuration::getInstance().memSpec->tCK;
else
clk = sc_time(1.0 / clkMhz, SC_US);
tCK = sc_time(1.0 / fCKMhz, SC_US);
this->burstlenght = Configuration::getInstance().memSpec->burstLength;
}
@@ -81,7 +81,7 @@ public:
private:
unsigned int burstlenght;
sc_time clk;
sc_time tCK;
unsigned int transCounter;
};

2
DRAMSys/library/src/simulation/dram/Dram.cpp
View File

@@ -141,7 +141,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,
unsigned int bank = DramExtension::getExtension(payload).getBank().ID();
// This is only needed for power simulation:
unsigned long long cycle = sc_time_stamp().value() / memSpec->clk.value();
unsigned long long cycle = sc_time_stamp() / memSpec->tCK;
if (phase == BEGIN_PRE)
{

78
DRAMSys/library/src/simulation/dram/DramDDR3.cpp
View File

@@ -52,8 +52,6 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name)
if (Configuration::getInstance().powerAnalysis)
{
sc_time clk = memSpec->clk;
MemArchitectureSpec memArchSpec;
memArchSpec.burstLength = memSpec->burstLength;
memArchSpec.dataRate = memSpec->dataRate;
@@ -67,45 +65,45 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name)
memArchSpec.dll = true;
MemTimingSpec memTimingSpec;
//FIXME: memTimingSpec.FAWB = memSpec->tFAW / clk;
//FIXME: memTimingSpec.RASB = memSpec->tRAS / clk;
//FIXME: memTimingSpec.RCB = memSpec->tRC / clk;
//FIXME: memTimingSpec.RPB = memSpec->tRP / clk;
//FIXME: memTimingSpec.RRDB = memSpec->tRRD / clk;
//FIXME: memTimingSpec.RRDB_L = memSpec->tRRD / clk;
//FIXME: memTimingSpec.RRDB_S = memSpec->tRRD / clk;
memTimingSpec.AL = memSpec->tAL / clk;
memTimingSpec.CCD = memSpec->tCCD / clk;
memTimingSpec.CCD_L = memSpec->tCCD / clk;
memTimingSpec.CCD_S = memSpec->tCCD / clk;
memTimingSpec.CKE = memSpec->tCKE / clk;
memTimingSpec.CKESR = memSpec->tCKESR / clk;
memTimingSpec.clkMhz = memSpec->clkMHz;
//FIXME: memTimingSpec.FAWB = memSpec->tFAW / memSpec->tCK;
//FIXME: memTimingSpec.RASB = memSpec->tRAS / memSpec->tCK;
//FIXME: memTimingSpec.RCB = memSpec->tRC / memSpec->tCK;
//FIXME: memTimingSpec.RPB = memSpec->tRP / memSpec->tCK;
//FIXME: memTimingSpec.RRDB = memSpec->tRRD / memSpec->tCK;
//FIXME: memTimingSpec.RRDB_L = memSpec->tRRD / memSpec->tCK;
//FIXME: memTimingSpec.RRDB_S = memSpec->tRRD / memSpec->tCK;
memTimingSpec.AL = memSpec->tAL / memSpec->tCK;
memTimingSpec.CCD = memSpec->tCCD / memSpec->tCK;
memTimingSpec.CCD_L = memSpec->tCCD / memSpec->tCK;
memTimingSpec.CCD_S = memSpec->tCCD / memSpec->tCK;
memTimingSpec.CKE = memSpec->tCKE / memSpec->tCK;
memTimingSpec.CKESR = memSpec->tCKESR / memSpec->tCK;
memTimingSpec.clkMhz = memSpec->fCKMHz;
// See also MemTimingSpec.cc in DRAMPower
memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz;
memTimingSpec.DQSCK = memSpec->tDQSCK / clk;
memTimingSpec.FAW = memSpec->tFAW / clk;
memTimingSpec.RAS = memSpec->tRAS / clk;
memTimingSpec.RC = memSpec->tRC / clk;
memTimingSpec.RCD = memSpec->tRCD / clk;
memTimingSpec.REFI = memSpec->tREFI / clk;
memTimingSpec.RFC = memSpec->tRFC / clk;
memTimingSpec.RL = memSpec->tRL / clk;
memTimingSpec.RP = memSpec->tRP / clk;
memTimingSpec.RRD = memSpec->tRRD / clk;
memTimingSpec.RRD_L = memSpec->tRRD / clk;
memTimingSpec.RRD_S = memSpec->tRRD / clk;
memTimingSpec.RTP = memSpec->tRTP / clk;
memTimingSpec.TAW = memSpec->tFAW / clk;
memTimingSpec.WL = memSpec->tWL / clk;
memTimingSpec.WR = memSpec->tWR / clk;
memTimingSpec.WTR = memSpec->tWTR / clk;
memTimingSpec.WTR_L = memSpec->tWTR / clk;
memTimingSpec.WTR_S = memSpec->tWTR / clk;
memTimingSpec.XP = memSpec->tXP / clk;
memTimingSpec.XPDLL = memSpec->tXPDLL / clk;
memTimingSpec.XS = memSpec->tXS / clk;
memTimingSpec.XSDLL = memSpec->tXSDLL / clk;
memTimingSpec.clkPeriod = 1000.0 / memSpec->fCKMHz;
memTimingSpec.DQSCK = memSpec->tDQSCK / memSpec->tCK;
memTimingSpec.FAW = memSpec->tFAW / memSpec->tCK;
memTimingSpec.RAS = memSpec->tRAS / memSpec->tCK;
memTimingSpec.RC = memSpec->tRC / memSpec->tCK;
memTimingSpec.RCD = memSpec->tRCD / memSpec->tCK;
memTimingSpec.REFI = memSpec->tREFI / memSpec->tCK;
memTimingSpec.RFC = memSpec->tRFC / memSpec->tCK;
memTimingSpec.RL = memSpec->tRL / memSpec->tCK;
memTimingSpec.RP = memSpec->tRP / memSpec->tCK;
memTimingSpec.RRD = memSpec->tRRD / memSpec->tCK;
memTimingSpec.RRD_L = memSpec->tRRD / memSpec->tCK;
memTimingSpec.RRD_S = memSpec->tRRD / memSpec->tCK;
memTimingSpec.RTP = memSpec->tRTP / memSpec->tCK;
memTimingSpec.TAW = memSpec->tFAW / memSpec->tCK;
memTimingSpec.WL = memSpec->tWL / memSpec->tCK;
memTimingSpec.WR = memSpec->tWR / memSpec->tCK;
memTimingSpec.WTR = memSpec->tWTR / memSpec->tCK;
memTimingSpec.WTR_L = memSpec->tWTR / memSpec->tCK;
memTimingSpec.WTR_S = memSpec->tWTR / memSpec->tCK;
memTimingSpec.XP = memSpec->tXP / memSpec->tCK;
memTimingSpec.XPDLL = memSpec->tXPDLL / memSpec->tCK;
memTimingSpec.XS = memSpec->tXS / memSpec->tCK;
memTimingSpec.XSDLL = memSpec->tXSDLL / memSpec->tCK;
MemPowerSpec memPowerSpec;
memPowerSpec.idd0 = memSpec->iDD0;

78
DRAMSys/library/src/simulation/dram/DramDDR4.cpp
View File

@@ -52,8 +52,6 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name)
if (Configuration::getInstance().powerAnalysis)
{
sc_time clk = memSpec->clk;
MemArchitectureSpec memArchSpec;
memArchSpec.burstLength = memSpec->burstLength;
memArchSpec.dataRate = memSpec->dataRate;
@@ -67,45 +65,45 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name)
memArchSpec.dll = true;
MemTimingSpec memTimingSpec;
//FIXME: memTimingSpec.FAWB = memSpec->tFAW / clk;
//FIXME: memTimingSpec.RASB = memSpec->tRAS / clk;
//FIXME: memTimingSpec.RCB = memSpec->tRC / clk;
//FIXME: memTimingSpec.RPB = memSpec->tRP / clk;
//FIXME: memTimingSpec.RRDB = memSpec->tRRD_S / clk;
//FIXME: memTimingSpec.RRDB_L = memSpec->tRRD_L / clk;
//FIXME: memTimingSpec.RRDB_S = memSpec->tRRD_S / clk;
memTimingSpec.AL = memSpec->tAL / clk;
memTimingSpec.CCD = memSpec->tCCD_S / clk;
memTimingSpec.CCD_L = memSpec->tCCD_L / clk;
memTimingSpec.CCD_S = memSpec->tCCD_S / clk;
memTimingSpec.CKE = memSpec->tCKE / clk;
memTimingSpec.CKESR = memSpec->tCKESR / clk;
memTimingSpec.clkMhz = memSpec->clkMHz;
//FIXME: memTimingSpec.FAWB = memSpec->tFAW / memSpec->tCK;
//FIXME: memTimingSpec.RASB = memSpec->tRAS / memSpec->tCK;
//FIXME: memTimingSpec.RCB = memSpec->tRC / memSpec->tCK;
//FIXME: memTimingSpec.RPB = memSpec->tRP / memSpec->tCK;
//FIXME: memTimingSpec.RRDB = memSpec->tRRD_S / memSpec->tCK;
//FIXME: memTimingSpec.RRDB_L = memSpec->tRRD_L / memSpec->tCK;
//FIXME: memTimingSpec.RRDB_S = memSpec->tRRD_S / memSpec->tCK;
memTimingSpec.AL = memSpec->tAL / memSpec->tCK;
memTimingSpec.CCD = memSpec->tCCD_S / memSpec->tCK;
memTimingSpec.CCD_L = memSpec->tCCD_L / memSpec->tCK;
memTimingSpec.CCD_S = memSpec->tCCD_S / memSpec->tCK;
memTimingSpec.CKE = memSpec->tCKE / memSpec->tCK;
memTimingSpec.CKESR = memSpec->tCKESR / memSpec->tCK;
memTimingSpec.clkMhz = memSpec->fCKMHz;
// See also MemTimingSpec.cc in DRAMPower
memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz;
memTimingSpec.DQSCK = memSpec->tDQSCK / clk;
memTimingSpec.FAW = memSpec->tFAW / clk;
memTimingSpec.RAS = memSpec->tRAS / clk;
memTimingSpec.RC = memSpec->tRC / clk;
memTimingSpec.RCD = memSpec->tRCD / clk;
memTimingSpec.REFI = memSpec->tREFI / clk;
memTimingSpec.RFC = memSpec->tRFC / clk;
memTimingSpec.RL = memSpec->tRL / clk;
memTimingSpec.RP = memSpec->tRP / clk;
memTimingSpec.RRD = memSpec->tRRD_S / clk;
memTimingSpec.RRD_L = memSpec->tRRD_L / clk;
memTimingSpec.RRD_S = memSpec->tRRD_S / clk;
memTimingSpec.RTP = memSpec->tRTP / clk;
memTimingSpec.TAW = memSpec->tFAW / clk;
memTimingSpec.WL = memSpec->tWL / clk;
memTimingSpec.WR = memSpec->tWR / clk;
memTimingSpec.WTR = memSpec->tWTR_S / clk;
memTimingSpec.WTR_L = memSpec->tWTR_L / clk;
memTimingSpec.WTR_S = memSpec->tWTR_S / clk;
memTimingSpec.XP = memSpec->tXP / clk;
memTimingSpec.XPDLL = memSpec->tXPDLL / clk;
memTimingSpec.XS = memSpec->tXS / clk;
memTimingSpec.XSDLL = memSpec->tXSDLL / clk;
memTimingSpec.clkPeriod = 1000.0 / memSpec->fCKMHz;
memTimingSpec.DQSCK = memSpec->tDQSCK / memSpec->tCK;
memTimingSpec.FAW = memSpec->tFAW / memSpec->tCK;
memTimingSpec.RAS = memSpec->tRAS / memSpec->tCK;
memTimingSpec.RC = memSpec->tRC / memSpec->tCK;
memTimingSpec.RCD = memSpec->tRCD / memSpec->tCK;
memTimingSpec.REFI = memSpec->tREFI / memSpec->tCK;
memTimingSpec.RFC = memSpec->tRFC / memSpec->tCK;
memTimingSpec.RL = memSpec->tRL / memSpec->tCK;
memTimingSpec.RP = memSpec->tRP / memSpec->tCK;
memTimingSpec.RRD = memSpec->tRRD_S / memSpec->tCK;
memTimingSpec.RRD_L = memSpec->tRRD_L / memSpec->tCK;
memTimingSpec.RRD_S = memSpec->tRRD_S / memSpec->tCK;
memTimingSpec.RTP = memSpec->tRTP / memSpec->tCK;
memTimingSpec.TAW = memSpec->tFAW / memSpec->tCK;
memTimingSpec.WL = memSpec->tWL / memSpec->tCK;
memTimingSpec.WR = memSpec->tWR / memSpec->tCK;
memTimingSpec.WTR = memSpec->tWTR_S / memSpec->tCK;
memTimingSpec.WTR_L = memSpec->tWTR_L / memSpec->tCK;
memTimingSpec.WTR_S = memSpec->tWTR_S / memSpec->tCK;
memTimingSpec.XP = memSpec->tXP / memSpec->tCK;
memTimingSpec.XPDLL = memSpec->tXPDLL / memSpec->tCK;
memTimingSpec.XS = memSpec->tXS / memSpec->tCK;
memTimingSpec.XSDLL = memSpec->tXSDLL / memSpec->tCK;
MemPowerSpec memPowerSpec;
memPowerSpec.idd0 = memSpec->iDD0;

7
DRAMSys/library/src/simulation/dram/DramRecordable.cpp
View File

@@ -123,7 +123,7 @@ void DramRecordable<BaseDram>::powerWindow()
// At the very beginning (zero clock cycles) the energy is 0, so we wait first
wait(powerWindowSize);
clkCycles = sc_time_stamp().value() / this->memSpec->clk.value();
clkCycles = sc_time_stamp() / this->memSpec->tCK;
DRAMPower->calcWindowEnergy(clkCycles);
@@ -148,11 +148,10 @@ void DramRecordable<BaseDram>::powerWindow()
template class DramRecordable<DramDDR3>;
template class DramRecordable<DramDDR4>;
template class DramRecordable<DramWideIO>;
template class DramRecordable<DramLPDDR4>;
template class DramRecordable<DramWideIO>;
template class DramRecordable<DramWideIO2>;
template class DramRecordable<DramHBM2>;
template class DramRecordable<DramGDDR5>;
template class DramRecordable<DramGDDR5X>;
template class DramRecordable<DramGDDR6>;
template class DramRecordable<DramHBM2>;

2
DRAMSys/library/src/simulation/dram/DramRecordable.h
View File

@@ -58,7 +58,7 @@ private:
TlmRecorder *tlmRecorder;
libDRAMPower *DRAMPower;
sc_time powerWindowSize = Configuration::getInstance().memSpec->clk *
sc_time powerWindowSize = Configuration::getInstance().memSpec->tCK *
Configuration::getInstance().windowSize;
// When working with floats, we have to decide ourselves what is an

70
DRAMSys/library/src/simulation/dram/DramWideIO.cpp
View File

@@ -54,8 +54,6 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name)
if (Configuration::getInstance().powerAnalysis)
{
sc_time clk = memSpec->clk;
MemArchitectureSpec memArchSpec;
memArchSpec.burstLength = memSpec->burstLength;
memArchSpec.dataRate = memSpec->dataRate;
@@ -69,45 +67,45 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name)
memArchSpec.dll = false;
MemTimingSpec memTimingSpec;
//FIXME: memTimingSpec.FAWB = memSpec->tTAW / clk;
//FIXME: memTimingSpec.RASB = memSpec->tRAS / clk;
//FIXME: memTimingSpec.RCB = memSpec->tRC / clk;
//FIXME: memTimingSpec.RPB = memSpec->tRP / clk;
//FIXME: memTimingSpec.RRDB = memSpec->tRRD / clk;
//FIXME: memTimingSpec.RRDB_L = memSpec->tRRD / clk;
//FIXME: memTimingSpec.RRDB_S = memSpec->tRRD / clk;
//FIXME: memTimingSpec.FAWB = memSpec->tTAW / memSpec->tCK;
//FIXME: memTimingSpec.RASB = memSpec->tRAS / memSpec->tCK;
//FIXME: memTimingSpec.RCB = memSpec->tRC / memSpec->tCK;
//FIXME: memTimingSpec.RPB = memSpec->tRP / memSpec->tCK;
//FIXME: memTimingSpec.RRDB = memSpec->tRRD / memSpec->tCK;
//FIXME: memTimingSpec.RRDB_L = memSpec->tRRD / memSpec->tCK;
//FIXME: memTimingSpec.RRDB_S = memSpec->tRRD / memSpec->tCK;
memTimingSpec.AL = 0;
memTimingSpec.CCD = memSpec->burstLength;
memTimingSpec.CCD_L = memSpec->burstLength;
memTimingSpec.CCD_S = memSpec->burstLength;
memTimingSpec.CKE = memSpec->tCKE / clk;
memTimingSpec.CKESR = memSpec->tCKESR / clk;
memTimingSpec.clkMhz = memSpec->clkMHz;
memTimingSpec.CKE = memSpec->tCKE / memSpec->tCK;
memTimingSpec.CKESR = memSpec->tCKESR / memSpec->tCK;
memTimingSpec.clkMhz = memSpec->fCKMHz;
// See also MemTimingSpec.cc in DRAMPower
memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz;
memTimingSpec.DQSCK = memSpec->tDQSCK / clk;
memTimingSpec.FAW = memSpec->tTAW / clk;
memTimingSpec.RAS = memSpec->tRAS / clk;
memTimingSpec.RC = memSpec->tRC / clk;
memTimingSpec.RCD = memSpec->tRCD / clk;
memTimingSpec.REFI = memSpec->tREFI / clk;
memTimingSpec.RFC = memSpec->tRFC / clk;
memTimingSpec.RL = memSpec->tRL / clk;
memTimingSpec.RP = memSpec->tRP / clk;
memTimingSpec.RRD = memSpec->tRRD / clk;
memTimingSpec.RRD_L = memSpec->tRRD / clk;
memTimingSpec.RRD_S = memSpec->tRRD / clk;
memTimingSpec.clkPeriod = 1000.0 / memSpec->fCKMHz;
memTimingSpec.DQSCK = memSpec->tDQSCK / memSpec->tCK;
memTimingSpec.FAW = memSpec->tTAW / memSpec->tCK;
memTimingSpec.RAS = memSpec->tRAS / memSpec->tCK;
memTimingSpec.RC = memSpec->tRC / memSpec->tCK;
memTimingSpec.RCD = memSpec->tRCD / memSpec->tCK;
memTimingSpec.REFI = memSpec->tREFI / memSpec->tCK;
memTimingSpec.RFC = memSpec->tRFC / memSpec->tCK;
memTimingSpec.RL = memSpec->tRL / memSpec->tCK;
memTimingSpec.RP = memSpec->tRP / memSpec->tCK;
memTimingSpec.RRD = memSpec->tRRD / memSpec->tCK;
memTimingSpec.RRD_L = memSpec->tRRD / memSpec->tCK;
memTimingSpec.RRD_S = memSpec->tRRD / memSpec->tCK;
memTimingSpec.RTP = memSpec->burstLength;
memTimingSpec.TAW = memSpec->tTAW / clk;
memTimingSpec.WL = memSpec->tWL / clk;
memTimingSpec.WR = memSpec->tWR / clk;
memTimingSpec.WTR = memSpec->tWTR / clk;
memTimingSpec.WTR_L = memSpec->tWTR / clk;
memTimingSpec.WTR_S = memSpec->tWTR / clk;
memTimingSpec.XP = memSpec->tXP / clk;
memTimingSpec.XPDLL = memSpec->tXP / clk;
memTimingSpec.XS = memSpec->tXS / clk;
memTimingSpec.XSDLL = memSpec->tXS / clk;
memTimingSpec.TAW = memSpec->tTAW / memSpec->tCK;
memTimingSpec.WL = memSpec->tWL / memSpec->tCK;
memTimingSpec.WR = memSpec->tWR / memSpec->tCK;
memTimingSpec.WTR = memSpec->tWTR / memSpec->tCK;
memTimingSpec.WTR_L = memSpec->tWTR / memSpec->tCK;
memTimingSpec.WTR_S = memSpec->tWTR / memSpec->tCK;
memTimingSpec.XP = memSpec->tXP / memSpec->tCK;
memTimingSpec.XPDLL = memSpec->tXP / memSpec->tCK;
memTimingSpec.XS = memSpec->tXS / memSpec->tCK;
memTimingSpec.XSDLL = memSpec->tXS / memSpec->tCK;
MemPowerSpec memPowerSpec;
memPowerSpec.idd0 = memSpec->iDD0;
@@ -178,7 +176,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload,
unsigned int bank = DramExtension::getExtension(payload).getBank().ID();
// This is only needed for power simulation:
unsigned long long cycle = sc_time_stamp().value() / memSpec->clk.value();
unsigned long long cycle = sc_time_stamp().value() / memSpec->tCK.value();
if (phase == BEGIN_PRE)
{